WO2023179411A1 - Semiconductor device and preparation method therefor, and electronic device - Google Patents

Semiconductor device and preparation method therefor, and electronic device Download PDF

Info

Publication number
WO2023179411A1
WO2023179411A1 PCT/CN2023/081450 CN2023081450W WO2023179411A1 WO 2023179411 A1 WO2023179411 A1 WO 2023179411A1 CN 2023081450 W CN2023081450 W CN 2023081450W WO 2023179411 A1 WO2023179411 A1 WO 2023179411A1
Authority
WO
WIPO (PCT)
Prior art keywords
gates
target
sacrificial
dielectric layer
isolation
Prior art date
Application number
PCT/CN2023/081450
Other languages
French (fr)
Chinese (zh)
Inventor
雷电
刘熹
王洪娟
许耀文
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2023179411A1 publication Critical patent/WO2023179411A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method thereof, and electronic equipment.
  • CMOS Complementary Metal Oxide Semiconductor
  • the RMG process can avoid the impact of the source-drain epitaxy process on the gate, it also makes the structure of the semiconductor device more complex, making the topography of the device surface more complex and making the device planarization process more challenging. If the surface of the device is uneven after the planarization process, it will have a negative impact on subsequent processes, which may eventually lead to device failure and reduced yield.
  • Embodiments of the present application provide a semiconductor device, a preparation method thereof, and electronic equipment, which are used to improve the problem of uneven surfaces after the planarization process of the semiconductor device, so as to improve the yield rate of the semiconductor device.
  • a method for manufacturing a semiconductor device includes: forming a plurality of fins on a substrate, the fins extending in a first direction parallel to the substrate; forming a A plurality of first sacrificial gates and a plurality of second sacrificial gates located in the second region, the first sacrificial gates and the second sacrificial gates extend in a second direction parallel to the substrate, the first direction intersects with the second direction; the plurality of first sacrificial gates and the plurality of second sacrificial gates are arranged across the plurality of fins, and the second area is around the first area ; Form an interlayer dielectric layer, the interlayer dielectric layer covers the plurality of first sacrificial gates and the plurality of second sacrificial gates; Planarize the interlayer dielectric layer to expose the plurality of first sacrificial gates; The gate and the plurality of second sacrificial gates are away from the surface of the substrate; an
  • fins are first provided on the substrate, a first sacrificial gate is provided on the first region, and a second sacrificial gate is provided on the second region, and then a fin is formed on the substrate.
  • the interlayer dielectric layer flattens the interlayer dielectric layer, and finally forms an isolation structure to divide the fin into a first fin and a second fin. In this way, before the planarization process is performed, the fins, the first sacrificial gate and the second sacrificial gate in the semiconductor device are relatively evenly distributed on the substrate.
  • some embodiments of the present application provide In the preparation method of the semiconductor device, the size of the isolation structure spaced between the first fin and the second fin, and the first sacrificial gate and the second sacrificial gate can be smaller, so that it is not easy to affect other subsequent planarization processes, and further The yield rate of the semiconductor device is improved and the performance of the semiconductor device is improved.
  • forming the isolation structure includes: etching the second sacrificial gate and the fin in the first preset area to form a first isolation trench; along the second direction, the first preset area Located on one side of the plurality of first sacrificial gates, the first isolation trench extends along the first direction.
  • a first isolation part is formed in the first isolation groove.
  • a second isolation part is formed in the second isolation groove.
  • the isolation structure includes the first isolation part and the second isolation part.
  • the first isolation part and the second isolation part can be used to better separate the first sacrificial gate and the second sacrificial gate, so that the first sacrificial gate is replaced with the first gate, and the second sacrificial gate is replaced with the third sacrificial gate. After the second gate, the first gate and the second gate are better separated to ensure the performance of the first gate.
  • the size of the first isolation portion in the second direction is less than or equal to twice the distance between the center lines of two adjacent fins; and/or, on the substrate At least one first sacrificial gate group is provided, and the first sacrificial gate group includes a plurality of first sacrificial gates; the size of the second isolation portion in the first direction is less than or equal to that of the first sacrificial gate group.
  • the distance between the center lines of two adjacent first sacrificial gates in the first sacrificial gate group adjacent to the two isolation parts is twice. In this way, the size of the first isolation part in the second direction is smaller, and the size of the second isolation part in the first direction is also smaller.
  • the first isolation part and the second isolation part are not easy to cause the first isolation part and the second isolation part to have a small size in the first direction. /or the provision of the second isolation portion results in an obvious height difference on the surface of the semiconductor device, thereby further improving the yield of the semiconductor device.
  • etching the second sacrificial gate and the fin in the first preset area to form a first isolation trench includes: forming a first mask layer on the interlayer dielectric layer, and the third A mask layer includes a first opening extending along the first direction and exposing ends of a plurality of second sacrificial gates close to the plurality of first sacrificial gates. Through the first opening, the exposed ends of the plurality of second sacrificial gates and the fins below the ends are etched to form first isolation trenches.
  • the preparation method before forming the plurality of first sacrificial gates and the plurality of second sacrificial gates, the preparation method further includes: forming an insulating layer on the substrate, and a portion of the fin is embedded in the The rest of the insulating layer protrudes from the upper surface of the insulating layer. and etching the exposed ends of the plurality of second sacrificial gates and the fins below the ends through the first opening to form a first isolation trench, including: etching the exposed ends of the first opening.
  • the exposed ends of the plurality of second sacrificial gates expose the fins below the ends.
  • the fin is etched to form a first recess in the insulating layer and a second recess on the insulating layer.
  • the first isolation groove includes the first recess and the second recess.
  • etching the interlayer dielectric layer and the fins in the second preset area to form a second isolation trench includes: forming a second mask layer on the interlayer dielectric layer, and the third The second mask layer includes a second opening extending along the second direction and exposing an interlayer dielectric layer between the first target sacrificial gate and the second target sacrificial gate; the first target sacrificial gate and the second target sacrificial gate is, along the first direction, the plurality of A sacrificial gate and the closest first sacrificial gate and second sacrificial gate among the plurality of second sacrificial gates.
  • the exposed interlayer dielectric layer and the fins below the interlayer dielectric layer are etched to form a second isolation trench.
  • the etching process is simple, which is beneficial to improving the preparation efficiency of the semiconductor device.
  • the preparation method before forming the interlayer dielectric layer, further includes: forming a dielectric layer covering the plurality of first sacrificial gates and the plurality of second sacrificial gates. Two opposite sides in the first direction. A source electrode and a drain electrode are formed on the fin; along the first direction, the source electrode and the drain electrode are respectively located on both sides of the first sacrificial gate and on both sides of the second sacrificial gate. . An etching stop layer is formed, covering the dielectric layer, the source electrode and the drain electrode.
  • etching the exposed interlayer dielectric layer and the fins under the interlayer dielectric layer through the second opening to form a second isolation trench includes: etching the second The interlayer dielectric layer exposed by the opening exposes the etching stop layer below the interlayer dielectric layer.
  • the exposed etching stop layer is etched to expose the source electrode or drain electrode under the etching stop layer.
  • the exposed source electrode or drain electrode and the fin under the source electrode or drain electrode are etched to form the second isolation trench.
  • the second opening also exposes a portion of the surface of the first target sacrificial gate close to the second target sacrificial gate, and a portion of the second target sacrificial gate close to the first target sacrificial gate. surface.
  • the first target sacrificial gate is also etched. and the second target sacrificial gate. In this way, the size of the second opening in the first direction is larger, and the process of patterning the second mask layer is simpler.
  • the size of the second isolation trench in the first direction is also larger, and the size of the second isolation part is also larger accordingly, so that the first sacrificial gate and the second sacrificial gate can be better separated, and the subsequent The first gate and the second gate are formed to be spaced apart.
  • the dielectric layer covering the side of the first target sacrificial gate close to the second target sacrificial gate is a first target dielectric layer
  • the etching stop layer covering the first target dielectric layer is a first target dielectric layer.
  • Target etch stop layer, the dielectric layer covering the side of the second target sacrificial gate close to the first target sacrificial gate is a second target dielectric layer
  • the etch stop layer covering the second target dielectric layer is a second target etch stop layer.
  • the second opening also exposes end surfaces of the first target dielectric layer, the first target etch stop layer, the second target dielectric layer and the second target etch stop layer away from the substrate.
  • the etching of the interlayer dielectric layer and the fins in the second preset area to form a second isolation trench includes: simultaneously etching the first target sacrificial gate and the first target dielectric through the second opening. layer, the first target etch stop layer, the second target sacrificial gate, the second target dielectric layer, the second target etch stop layer, the first target sacrificial gate and the third target etch stop layer.
  • the interlayer dielectric layer between the two target sacrificial gates forms a third recess; along the direction perpendicular to the substrate, the bottom surface of the third recess is in contact with the first target sacrificial gate and the second target sacrificial gate.
  • first target dielectric layer, first target etching stop layer, second target dielectric layer and second target etching stop layer are etched.
  • the remaining interlayer dielectric layer between the first target sacrificial gate and the second target sacrificial gate is etched to expose the etching stop layer under the interlayer dielectric layer. Etch the remaining first target sacrificial gate and the second target sacrificial gate, the exposed etch stop layer, the source electrode or the drain electrode below the etch stop layer, and the source electrode or the drain electrode below. fins to form a second isolation groove.
  • the plurality of first sacrificial gates there are gaps between the plurality of second sacrificial gates.
  • the gap is less than or equal to the distance between the center lines of two adjacent fins.
  • each fin can be provided with a first sacrificial gate or a second sacrificial gate, so that the first sacrificial gate and the second sacrificial gate are evenly distributed on the substrate, which is beneficial to improving the uneven distribution of the sacrificial gate structure on the substrate.
  • Uniformity causes the problem of uneven surfaces of semiconductor devices after the planarization process, improves the yield rate of semiconductor devices, and improves the performance of semiconductor devices.
  • the preparation method further includes: replacing the first sacrificial gate with a first gate, and replacing the second sacrificial gate with a second gate.
  • a second aspect provides a semiconductor device, which includes a substrate, a plurality of first fins and a plurality of second fins, a plurality of first gates and a plurality of second gates, an interlayer dielectric layer and an isolation structure.
  • a plurality of first fins and a plurality of second fins are provided on the substrate and extend in a first direction parallel to the substrate.
  • a plurality of first gates and a plurality of second gates extend along a second direction parallel to the substrate, and the first direction intersects the second direction; the plurality of first gates are provided across the On the plurality of first fins, the plurality of second gates are provided across the plurality of second fins.
  • the interlayer dielectric layer covers the area between the plurality of first gates and the area between the plurality of second gates, exposing the plurality of first gates and the plurality of second gates away from the the surface of the substrate.
  • Isolation structure spaced between the plurality of first fins and the plurality of second fins, spaced between the plurality of first gates and the plurality of second gates, and surrounding the plurality of first fins and the plurality of second gates Multiple first gates.
  • the plurality of first fins and the plurality of second fins are made of the same material and are arranged in the same layer
  • the plurality of first gates and the plurality of second gates are made of the same material and are arranged in the same layer.
  • the first fin and the second fin are made of the same material and are arranged in the same layer
  • the first gate and the second gate are made of the same material and are arranged in the same layer, that is, the first fin and the second fin are both Cut from fins, the first gate and the second gate are prepared simultaneously. Therefore, in the preparation process of semiconductor devices, fins are first laid evenly on the substrate to form a first sacrificial gate corresponding to the first gate and a second sacrificial gate corresponding to the second gate, and then an interlayer dielectric layer is formed to flatten the semiconductor device.
  • the interlayer dielectric layer is formed, and finally an isolation structure is formed to divide the fin into a first fin and a second fin, and to separate the first sacrificial gate and the second sacrificial gate.
  • an isolation structure is formed to divide the fin into a first fin and a second fin, and to separate the first sacrificial gate and the second sacrificial gate.
  • some embodiments of the present application provide In the semiconductor device, the size of the isolation structure spaced between the first fin and the second fin, and the first sacrificial gate and the second sacrificial gate can be smaller, so that it is not easy to affect other subsequent planarization processes, further improving the efficiency of the semiconductor device.
  • the device yield rate improves the performance of semiconductor devices.
  • the isolation structure includes a first isolation portion and a second isolation portion.
  • a first isolation portion extends along the first direction, and along the second direction, the first isolation portion is located on one side of the plurality of first gates.
  • the second isolation part extends along the second direction, and is located on one side of the plurality of first gates along the first direction. In this way, the first gate and the second gate can be well spaced apart in both the first direction and the second direction.
  • the first isolation portion includes a plurality of isolation sub-portions spaced apart along the first direction, the isolation sub-portions are located on an extension line of the second gate, and the isolation sub-portions The width in the first direction It is equal to the width of the second gate in the first direction.
  • the semiconductor device further includes an insulating layer. Parts of the first fins and the second fins are embedded in the insulating layer, and the remaining parts protrude from the upper surface of the insulating layer.
  • the isolation sub-portion includes a first part embedded in the insulating layer and a second part located on the insulating layer; the size of the first part in the second direction is consistent with the size of the second fin in the second direction. The dimensions in both directions are equal.
  • the closest first gate and second gate among the plurality of first gates and the plurality of second gates are the first target gate and the third gate respectively.
  • the semiconductor device further includes: a first target dielectric layer covering a side of the first target gate close to the second target sacrificial gate; a first target etching stop layer covering the first target dielectric layer; a second target dielectric layer on the side of the second target gate close to the first target sacrificial gate; and a second target etching stop layer covering the second target dielectric layer.
  • the second isolation portion is located between the first target etching stop layer and the second target etching stop layer.
  • the semiconductor device further includes: a first dielectric layer and a second dielectric layer respectively covering two opposite sides of the second isolation part in the first direction.
  • the isolation structure includes two first isolation parts and two second isolation parts.
  • the two first isolation parts are respectively located on the plurality of strips. Opposite sides of the first gate; along the first direction, two second isolation parts are located on opposite sides of the plurality of first gates; two first isolation parts and two The second isolation parts are connected to form a frame shape.
  • the semiconductor device further includes a third dielectric layer, a source electrode and a drain electrode, and a third etching stop layer.
  • a third dielectric layer covers two opposite sides of the plurality of first gates and the plurality of second gates in the first direction; a source electrode and a drain electrode located on the plurality of first fins and On the plurality of second fins; along the first direction, the source electrode and the drain electrode are respectively located on both sides of the first gate and on both sides of the second gate; a third etching stop layer covering the third dielectric layer, the source electrode and the drain electrode.
  • the size of the first isolation portion in the second direction is less than or equal to twice the distance between the center lines of two adjacent first fins; and/or the lining At least one first grid group is provided on the bottom, and the first grid group includes a plurality of the first grids; the size of the second isolation part in the first direction is less than or equal to that of the second isolation part.
  • the distance between the center lines of two adjacent first gates in the first gate group adjacent to the isolation part is twice.
  • the widths of the plurality of first fins and the plurality of second fins are equal; and/or, any two adjacent ones of the plurality of first fins and the plurality of second fins are The spacing between the fins is equal; and/or the widths of the plurality of second gates are equal; and/or the spacing between any two adjacent second gates is equal.
  • the distribution of the first fin, the second fin and the second gate is relatively uniform.
  • the distribution of the fin and the second sacrificial gate is relatively uniform, thereby effectively improving the different polishing rates caused by uneven structural distribution.
  • the problem of different surface heights of semiconductor devices improves the yield of semiconductor devices.
  • an electronic device in a third aspect, includes a printed circuit board and any of the above-mentioned second aspects.
  • the semiconductor device according to an embodiment; the semiconductor device and the printed circuit board are electrically connected.
  • Figure 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application
  • Figures 2A to 7 are structural diagrams of semiconductor devices corresponding to each step in the flow chart shown in Figure 1;
  • Figure 8 is a top view of a semiconductor device provided by an embodiment of the present application.
  • Figure 9 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figure 10 is a top view of a semiconductor device provided by an embodiment of the present application.
  • Figure 11 is a cross-sectional view at D-D’ in Figure 10;
  • Figure 12 is a perspective view of a semiconductor device provided by an embodiment of the present application.
  • Figure 13 is a flow chart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figure 14 is a perspective view of a substrate provided by an embodiment of the present application.
  • Figure 15 is a top view of another semiconductor device provided by an embodiment of the present application.
  • Figure 16 is a perspective view of yet another semiconductor device provided by an embodiment of the present application.
  • Figure 17 is a cross-sectional view at F-F’ in Figure 15;
  • Figure 18 is a perspective view of yet another semiconductor device provided by an embodiment of the present application.
  • Figure 19 is a structure of a semiconductor device provided by an embodiment of the present application.
  • Figure 20 is a top view of yet another semiconductor device provided by an embodiment of the present application.
  • Figure 21 is a cross-sectional view at G-G’ in Figure 20;
  • Figure 22 is a perspective view of yet another semiconductor device provided by an embodiment of the present application.
  • Figure 23 is a top view of another semiconductor device provided by the embodiment of the present application.
  • Figure 24 is a cross-sectional view at H-H' in Figure 23;
  • Figure 25 is a cross-sectional view of Figure 23 at I-I';
  • Figure 26 is a flow chart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figure 27 is a top view of another semiconductor device provided by the embodiment of the present application.
  • Figure 28 is a top view of another semiconductor device provided by the embodiment of the present application.
  • Figure 29 is a top view of another semiconductor device provided by the embodiment of the present application.
  • Figure 30 is a top view of another semiconductor device provided by the embodiment of the present application.
  • Figure 31 is a top view of another semiconductor device provided by the embodiment of the present application.
  • Figure 32 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figures 33 to 34 are structural diagrams of semiconductor devices corresponding to each step in the flow chart shown in Figure 32;
  • Figure 35 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figure 36 is a perspective view of yet another semiconductor device provided by an embodiment of the present application.
  • Figure 37 is a structural diagram of yet another semiconductor device provided by an embodiment of the present application.
  • Figure 38 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figure 39 is a state diagram of a semiconductor device provided by an embodiment of the present application.
  • Figure 40 is a top view of another semiconductor device provided by an embodiment of the present application.
  • Figure 41 is a flow chart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figures 42 and 43 are structural diagrams of semiconductor devices corresponding to each step in the flow chart shown in Figure 41;
  • Figure 44 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figure 45 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figures 46 to 48 are structural diagrams of semiconductor devices corresponding to each step in the flow chart shown in Figure 45;
  • Figure 49 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figures 50 to 53 are state diagrams of the semiconductor devices corresponding to each step in the flow chart shown in Figure 49;
  • Figure 54 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application.
  • Figure 55 is a top view of another semiconductor device provided by the embodiment of the present application.
  • Figure 56 is a top view of another semiconductor device provided by the embodiment of the present application.
  • Figure 57 is a cross-sectional view at J-J’ of Figure 56;
  • Figure 58 is a cross-sectional view at K-K’ in Figure 56;
  • Figure 59 is a structural diagram of another semiconductor device provided by an embodiment of the present application.
  • Figure 60 is a structural diagram of an electronic device provided by an embodiment of the present application.
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • equal includes absolute equality and approximate equality, where the approximate equality may be equal within the acceptable deviation range, for example The difference between the two is less than or equal to 5% of either one.
  • Exemplary embodiments are described in the embodiments of the present application with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • a method of manufacturing a semiconductor device includes:
  • a plurality of first fins 20' extending along the first direction X are formed on the substrate 10'.
  • the substrate 10' includes a plurality of active areas AA and a blank area BB surrounding the active area AA.
  • a plurality of first fins 20' are formed on each active area AA, but no first fin 20' is formed on the blank area BB.
  • the first direction X is parallel to the substrate 10'.
  • a plurality of first sacrificial gates 30' extending along the second direction Y are formed.
  • the first sacrificial gate 30' is disposed across the plurality of first fins 20'.
  • the second direction Y intersects the first direction X, and the second direction Y is parallel to the substrate 10'.
  • S3' as shown in Figure 4A and Figure 4B, form the source electrode 40' and the drain electrode 50'.
  • the source electrode 40' and the drain electrode 50' are located on the first fin 20' and respectively located on both sides of the first sacrificial gate 30' in the first direction X.
  • an interlayer dielectric layer 60' is formed, and the interlayer dielectric layer 60' covers the first sacrificial gate 30'.
  • the interlayer dielectric layer 60' is planarized to expose the surfaces of the plurality of first sacrificial gates 30' away from the substrate 10'.
  • CMP chemical mechanical polishing
  • the etching rate of the chemical mechanical polishing process will be affected by the distribution density of materials and structures, and before forming the interlayer dielectric layer, the first fin 20', the first sacrificial gate 30', Structures such as the source electrode 40' and the drain electrode 50', the first fin 20', the first sacrificial gate 30', the source electrode 40', the drain electrode 50' and other structures are not provided on the blank area BB, and the structures on the different active areas AA
  • the structural distribution of the first fin 20', the first sacrificial gate 30', the source electrode 40' and the drain electrode 50' are also not exactly the same.
  • the height of the surface of the interlayer dielectric layer 60' on the active area AA of the substrate 10' is equal to the height of the surface of the interlayer dielectric layer 60' on the blank area BB of the substrate 10'.
  • the height of the interlayer dielectric layer 60' in different effective areas AA is also likely to be different.
  • the height of the interlayer dielectric layer 60' in different positions of the same effective area AA may also be different. difference.
  • the surface height of the interlayer dielectric layer 60' on the blank area BB may be lower than the surface height of the interlayer dielectric layer 60' on the active area AA.
  • the surface height of the interlayer dielectric layer 60' in the area where the first sacrificial gate 30' is less distributed is lower than the area where the first sacrificial gate 30' is more distributed. The surface height of the interlayer dielectric layer 60'.
  • the uneven surface of the interlayer dielectric layer 60' will have a negative impact on subsequent steps.
  • the first sacrificial gate 30' is subsequently replaced with the first gate 70', when chemical mechanical polishing is required to remove the gate material on the surface of the interlayer dielectric layer 60', the surface height of the interlayer dielectric layer 60' will Non-uniformity will affect the removal of gate material.
  • the gate material on the surface of the blank area BB is not completely removed ((causing the first gate 70' that should not be electrically connected to form an electrical connection)), thus It is easy to cause the semiconductor device to fail after the preparation is completed and the semiconductor device is formed.
  • the first gate 70' provided on the active area AA has been partially or completely removed, which will also cause the semiconductor device to fail.
  • the method of manufacturing a semiconductor device includes forming a circuit structure 101 and a dummy structure 102 on a substrate 10′′. , where the substrate 10′′ includes a plurality of active areas AA and a blank area BB arranged surrounding the active areas AA. A circuit structure is formed on each active area AA, and a plurality of dummy structures 102 are formed on the blank area BB.
  • the circuit structure 101 includes a transistor, and the transistor includes a first fin 20", a first sacrificial gate 30", a source and a drain (not shown).
  • the transistor may be a fin field-effect transistor (FinFET).
  • the dummy structure 102 has a similar structure to the circuit structure 101 and also includes a transistor.
  • the transistor includes a second fin, a second sacrificial gate, a source and a drain.
  • the second fin may be made of the same material as the first fin and spaced apart from the first fin;
  • the second sacrificial gate may be made of the same material as the first sacrificial gate and spaced apart from the second sacrificial gate.
  • the dummy structure 102 has no actual electrical function.
  • the surface of the circuit structure away from the substrate may be flush with the surface of the dummy structure away from the substrate.
  • the dummy structure 102 and the circuit structure 101 are made of the same material and have similar structures, the uneven surface of the interlayer dielectric layer caused by different materials or uneven structural distribution can be effectively alleviated during subsequent planarization of the interlayer dielectric layer. .
  • the placement location of the dummy structure 102 is limited.
  • the size of the gap area between the active areas AA is smaller than the size of the smallest dummy structure 102, the dummy structure 102 cannot be provided correspondingly in the gap area. In this way, the above-mentioned problems still exist in this gap area. That is to say, the area where the dummy structure 102 is not provided will still cause a difference in the polishing rate of the chemical mechanical polishing process.
  • the dummy structure 102 can be provided in more gap areas by designing a smaller size dummy structure 102 .
  • the process is difficult and the cost is high.
  • the dummy structure 102 is prepared after the circuit structure 101 is prepared, when preparing the dummy structure 102, a certain distance needs to be reserved between the dummy structure 102 and the circuit structure 101 for isolation (the distance is at least on the order of microns) ), therefore, there are still many areas (such as the aforementioned intervals) where the problem of polishing rate differences in the chemical mechanical polishing process still exists.
  • some embodiments of the present application provide a method for manufacturing a semiconductor device, as shown in Figure 9, including:
  • a plurality of fins 20 are formed on the substrate 10 , and the fins 20 extend along the first direction X parallel to the substrate 10 .
  • substrate 10 may include a semiconductor material.
  • it can be bulk silicon, bulk germanium, silicon germanium, carbide One of silicon, silicon-on-insulator (SOI), and silicon germanium-on-insulator (SiGe-on-insulator, SGOI).
  • SOI silicon-on-insulator
  • SiGe-on-insulator SiGe-on-insulator
  • the substrate 10 may be a wafer, such as a silicon wafer.
  • the fins 20 can evenly cover the substrate 10 .
  • the lengths d1 of the plurality of fins 20 are equal.
  • the widths d2 of the plurality of fins 20 are equal, and the distance L1 between the center lines O of two adjacent fins 20 is equal.
  • the center line O extends along the first direction X.
  • the distance h1 from the top surface 21 of the plurality of fins 20 to the upper surface of the substrate 10 is equal.
  • This arrangement can facilitate the preparation of the fins 20, simplify the preparation process of the semiconductor device, and at the same time help improve the uniformity of the structure distribution on the substrate 10 before forming the interlayer dielectric layer 50.
  • the length d1 of the fin 20 , the width d2 of the fin 20 , the distance L1 between the center lines O of two adjacent fins 20 , and the distance h1 from the top surface 21 of the fin 20 to the top surface of the substrate 10 are all measured.
  • forming multiple fins 20 on the substrate 10 may include:
  • a substrate 10a is provided.
  • the substrate 10a is etched to form the substrate 10 and a plurality of fins 20 located on the substrate 10.
  • a mask layer may be formed on the substrate 10a, and the substrate may be etched based on the mask layer to form the substrate 10 and the plurality of fins 20 located on the substrate 10.
  • the method of forming the plurality of fins 20 on the substrate 10 in this application is not limited to this.
  • a plurality of first sacrificial gates 30 located in the first region S1 and a plurality of second sacrificial gates 40 located in the second region S2 are formed.
  • the first sacrificial gates 30 and the second sacrificial gates are formed 40 extends along a second direction Y parallel to the substrate 10 , and the first direction X and the second direction Y intersect.
  • the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 are disposed across the plurality of fins 20 , and the second area S2 is located around the first area S1 .
  • the first sacrificial gate 30 and the second sacrificial gate 40 are made of the same material.
  • the materials of the first sacrificial gate 30 and the second sacrificial gate 40 may include, for example, at least one of polysilicon, amorphous silicon, and amorphous carbon. Since materials such as polycrystalline silicon, amorphous silicon, and amorphous carbon are easy to be etched, have good shape retention, and are easy to remove, the first sacrificial gate is formed of at least one material among polycrystalline silicon, amorphous silicon, and amorphous carbon. 30 and the second sacrificial gate 40, the first sacrificial gate 30 and the second sacrificial gate 40 can have good morphology, stable structure, and can be easily removed.
  • the first sacrificial gate 30 and the second sacrificial gate 40 are made of the same material. During the chemical mechanical polishing process, the polishing rates of the first sacrificial gate 30 and the second sacrificial gate 40 are the same, which is beneficial to improving the flatness due to different polishing rates. After the interlayer dielectric layer is melted, the surface of the interlayer dielectric layer is highly uneven.
  • the first sacrificial gate 30 and the second sacrificial gate 40 may be formed simultaneously based on the same mask.
  • the first direction X and the second direction Y intersect.
  • the first direction X and the second direction Y may be perpendicular to each other.
  • a plurality of first sacrificial gates 30 and a plurality of second sacrificial gates 40 are disposed across the plurality of fins 20 . That is, the plurality of first sacrificial gates 30 cover the top surface 21 of the fin 20 and the two opposite side surfaces 22 of the fin 20 in the second direction Y. The plurality of second sacrificial gates 40 also cover the top surface 21 of the fin 20 and the fin 20 faces each other in the second direction Y. Two sides of the pair 22.
  • the substrate 10 includes a first area S1 and a second area S2.
  • the first area S1 corresponds to the effective area AA in the above embodiment
  • the second area S2 corresponds to the blank area BB in the above embodiment.
  • the second area S2 is located around the first area S1
  • the second area S2 surrounds the two opposite sides of the first area S1 in the first direction X, and the first area S1 is in Opposite sides in the second direction Y.
  • the second area S2 is located around the first area S1 may also mean that when the first area S1 is located at the edge of the substrate 10, the second area S2 surrounds the peripheral side of the first area S1 away from the edge.
  • the top surface 31 of the first sacrificial gate 30 is flush or approximately flush with the top surface 41 of the second sacrificial gate 40 . That is, in the third direction Z perpendicular to the substrate 10 , the distance from the top surface 31 of the first sacrificial gate 30 to the upper surface of the substrate 10 and the distance from the top surface 41 of the second sacrificial gate 40 to the substrate 10 are The distance between the upper surfaces is approximately h2.
  • a plurality of second sacrificial gates 40 are arranged around the plurality of first sacrificial gates 30, and the top surfaces 41 of the second sacrificial gates 40 and the top surfaces 31 of the first sacrificial gates 30 are flush or nearly flush.
  • the first sacrificial gate 30 and the second sacrificial gate 40 located in different areas can be polished at the same time. It is not easy for the uneven structure distribution in different areas of the substrate 10 to cause different polishing rates in different areas. The surface of the semiconductor device after grinding is highly uneven, thereby improving the yield of the semiconductor device.
  • the width d3 of the first sacrificial gate 30 and the width d4 of the second sacrificial gate 40 may be equal. In other examples, the width d3 of the first sacrificial gate 30 is greater than the width d4 of the second sacrificial gate 40 . In still other examples, the width d3 of the first sacrificial gate 30 is smaller than the width d4 of the second sacrificial gate 40 .
  • the width d3 of some of the first sacrificial gates 30 and the width d4 of the second sacrificial gate 40 may be equal to each other, and the width d3 of another part of the first sacrificial gates 30 may be equal to the width d4 of the second sacrificial gate 40.
  • d4 varies.
  • the widths of the first sacrificial gate 30 and the second sacrificial gate 40 are not limited and can be designed according to actual requirements.
  • the widths d3 of the plurality of first sacrificial gates 30 may also be equal, and the widths d4 of the plurality of second sacrificial gates 40 may also be equal. In this way, the preparation of the first sacrificial gate 30 and the second sacrificial gate 40 is facilitated, and the preparation process of the semiconductor device is simplified.
  • an interlayer dielectric layer 50 is formed.
  • the interlayer dielectric layer 50 covers the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 .
  • the material of the interlayer dielectric layer 50 may include one or more of silicon carbide, silicon oxycarbide, silicon nitride, silicon oxide, and silicon oxynitride.
  • the interlayer dielectric layer 50 is used to isolate lower-level circuit structures (eg, source and drain electrodes) from upper-level circuit traces.
  • lower-level circuit structures eg, source and drain electrodes
  • the interlayer dielectric layer 50 is planarized to expose the surfaces of the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 away from the substrate 10 .
  • a chemical mechanical polishing process may be used to planarize the interlayer dielectric layer 50 .
  • planarizing the interlayer dielectric layer 50 exposes the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 away from the surface of the substrate 10 , thereby facilitating subsequent placement of the first sacrificial gates 30 and the second sacrificial gates 40 remove, form The first gate and the second gate.
  • an isolation structure 60 is formed.
  • the isolation structure 60 divides the fin 20 into a first fin 201 located under a plurality of first sacrificial gates 30 and a plurality of second sacrificial gates 40. Below the second fin 202 , the isolation structure 60 surrounds the plurality of first fins 201 and the plurality of first sacrificial gates 30 .
  • fins 20 are first provided on both the first region S1 and the second region S2 of the substrate 10 (that is, the fins 20 evenly cover the substrate 10), And the first sacrificial gate 30 is set on the first region S1, and the second sacrificial gate 40 is set on the second region S2, then the interlayer dielectric layer 50 is formed, the interlayer dielectric layer 50 is planarized, and finally an isolation structure is formed. 60 divides the fin 20 into a first fin 201 and a second fin 202 .
  • the distribution of the fins 20 , the first sacrificial gate 30 and the second sacrificial gate 40 in the semiconductor device on the substrate 10 is relatively uniform. Therefore, during the planarization process of the interlayer dielectric layer 50 , it is not easy to Due to the uneven distribution of circuit structures on the substrate and the different materials in different areas, resulting in different grinding speeds in different areas, the problem of large differences in surface heights of semiconductor devices and uneven surface heights occurs, thus effectively improving the yield of semiconductor devices. Improve the performance of semiconductor devices.
  • the circuit structure 101 is first prepared and then the dummy structure 102 is set up in the gap between two adjacent circuit structures 101.
  • the gap between the circuit structure 101 and the dummy structure 102 is relatively large.
  • the fin 20, the first sacrificial gate 30 and the second sacrificial gate are cut to obtain a space between the first fin and the second fin, and the first sacrificial gate.
  • the size of the isolation structure 60 between the sacrificial gate 30 and the second sacrificial gate 40 can be smaller, so that it will not easily affect other subsequent planarization processes, further improving the yield of the semiconductor device and improving the performance of the semiconductor device. performance.
  • step S5 forming the isolation structure 60 includes:
  • the second sacrificial gate 40 and the fin 20 in the first preset area S3 etch the second sacrificial gate 40 and the fin 20 in the first preset area S3 to form a first isolation trench 601.
  • the first preset area S3 is located on one side of the plurality of first sacrificial gates 30 , and the first isolation trench 601 extends along the first direction X.
  • a wet etching or dry etching process may be used to etch the second sacrificial gate 40 and the fin 20 in the first preset area S3 to form the first isolation trench 601.
  • the first isolation portion 61 is formed in the first isolation groove 601.
  • the material of the first isolation part 61 may be oxide or nitride.
  • the semiconductor device can be planarized to remove the material of the first isolation portion 61 located outside the first isolation trench 601 .
  • the second preset area S4 is located on one side of the plurality of first sacrificial gates 30 , and the second isolation trench 602 extends along the second direction Y.
  • a wet etching or dry etching process may be used to etch the interlayer dielectric layer 50 and the fins 20 in the second preset area S4 to form the second isolation trench 602.
  • the second isolation part 62 is formed in the second isolation groove 602 .
  • the isolation structure 60 includes a first isolation part 61 and a second isolation part 62.
  • the material of the second isolation part 62 may be oxide or nitride.
  • the material of the first isolation part 61 may be the same as the material of the second isolation part 62 .
  • the semiconductor device may be planarized to remove bits.
  • first isolation part 61 and the second isolation part 62 may be formed, and the first isolation part 61 may be formed in the first isolation groove 601. Then a second isolation groove 602 is formed, and a second isolation portion 62 is formed in the second isolation groove 602 .
  • the second isolation groove 602 may be formed first, the second isolation part 62 is formed in the second isolation groove 602, and then the first isolation groove 601 is formed, and the first isolation part 61 is formed in the first isolation groove 601. .
  • the first isolation trench 601 is formed on one side of the plurality of first sacrificial gates 30 in the second direction Y, and the first isolation portion 61 is formed in the first isolation trench 601, so that it can be better
  • the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 adjacent in the second direction Y are spaced apart, and then the first sacrificial gates 30 are replaced with first gates, and the second sacrificial gates 40 are replaced. After forming the second gate, it is better to separate the adjacent first gate and the second gate in the second direction Y.
  • second isolation trenches 602 on one side of the plurality of first sacrificial gates 30 in the first direction A plurality of first sacrificial gates 30 and second sacrificial gates 40 adjacent in one direction It is better to separate the first gate and the second gate adjacent in the first direction X to ensure the performance of the first gate.
  • the first isolation trench 601 and the second isolation trench 602 are prepared separately, so that in the development process of semiconductor process nodes being continuously reduced, the first isolation trench 601 and the second isolation trench 602 can be ensured at the same time.
  • the accuracy of the dimensions prevents the required dimensions of the first isolation trench 601 and the second isolation trench 602 (the size in the first direction There is a big difference between the sizes.
  • the dimension d5 of the first isolation portion 61 in the second direction Y is less than or equal to twice the distance L1 between the center lines O of two adjacent fins 20 .
  • the center line O of the fin 20 extends along the first direction X.
  • the size d5 of the first isolation portion 61 in the second direction Y is smaller. Even during other subsequent grinding processes, because the first isolation portion 61 is made of different materials from the first gate and the second gate, the first isolation portion 61 is made of different materials.
  • the polishing rate of the area where the isolation part 61 is located is different from the polishing rate of the area where the first and second gates are located, and the polished height of the area where the first isolation part 61 is located and the area where the first and second gates are located appear.
  • the area of the recessed or protruding parts of the semiconductor device is also smaller, and the semiconductor device is not prone to failure or failure.
  • At least one first sacrificial gate group 301 is provided on the substrate 10 , and the first sacrificial gate group 301 includes a plurality of first sacrificial gates 30 .
  • the center line P of the first sacrificial gate 30 extends along the second direction Y.
  • At least one first sacrificial gate group 301 is provided on the substrate 10 may mean, as shown in FIG. 23, that the substrate 10 is provided with a first sacrificial gate group 301, or it may also mean, as shown in FIG. 31, the substrate 10 is provided with a first sacrificial gate group 301.
  • a plurality of first sacrificial gate groups 301 are provided on the bottom 10 .
  • FIG. 21 illustrates an example in which four first sacrificial gate groups 301 are provided on the substrate. Among them, in the clockwise direction, the four first sacrificial gate groups 301 are respectively the first group 3011, the second group 3012, the third group 3013 and the fourth group 3014.
  • each first sacrificial gate group 301 may correspond to a a first area S1.
  • the width d3 of the first sacrificial gates 30 in the same first sacrificial gate group 301 may be the same.
  • the width d3 of the first sacrificial gates 30 in different first sacrificial gate groups 301 may be the same or different.
  • FIG. 31 illustrates the case where the widths of the first sacrificial gates 30 in different first sacrificial gate groups 301 are different.
  • the circuit structure may be a driving circuit structure, a pixel circuit, an amplifying circuit structure, a power management circuit structure, a charging protection circuit structure, a control circuit structure and an image sensor circuit structure.
  • the embodiments of the present application do not limit this.
  • first sacrificial gates 30 in different first sacrificial gate groups 301 there is no limit to the number of first sacrificial gates 30 in different first sacrificial gate groups 301.
  • four first sacrificial gate groups 301 may each include five first sacrificial gates.
  • the dimension d6 of the second isolation part 62 in the first direction X is smaller, and the area of the upper surface of the second isolation part 62 is also smaller. Therefore, even in the subsequent polishing process, because the second isolation portion 62 is made of different materials from the first gate and the second gate, the polishing rate of the area where the second isolation portion 62 is located is different from that of the first gate and the second gate. The polishing rates of the regions are different, and the problem arises that the polished heights of the region where the second isolation portion 62 is located and the regions where the first gate and the second gate are located are different.
  • the area of the recessed or protruding parts of the semiconductor device is also smaller, and the semiconductor device has a smaller area. Devices are also not prone to failure or failure.
  • the distance L2 between the center lines P of two adjacent first sacrificial gates 30 in different first sacrificial gate groups 301 may be different. equal.
  • the size d6 of the second isolation portion 62 in the first direction X is less than or equal to the multiple first sacrificial gate groups 301 . It is twice the minimum value of the distance L2 between the center lines P of two adjacent first sacrificial gates 30 in the gate group 301 .
  • the size of the second isolation portion 62 in the first direction is also smaller, and the semiconductor device is less likely to fail or be defective.
  • step S51 etching the second sacrificial gate 40 and the fin 20 in the first preset area S3 to form the first isolation trench 601 includes:
  • a first mask layer 51 is formed on the interlayer dielectric layer 50.
  • the first mask layer 51 includes a first opening 511.
  • the first opening 511 extends along the first direction X and exposes a plurality of strips.
  • the second sacrificial gate 40 is close to the ends 42 of the plurality of first sacrificial gates 30 .
  • the first mask layer 51 may be a hard mask.
  • the first opening 511 corresponds to the first preset area S3.
  • the first opening 511 in the first mask layer 51 can be formed by forming a photoresist layer on the first mask layer 51, patterning the photoresist layer, and then based on the patterned photoresist layer. , obtained by etching the first mask layer 51.
  • the preparation method further includes:
  • an insulating layer 70 is formed on the substrate 10 . Parts of the fins 20 are embedded in the insulating layer 70 , and the remaining parts protrude from the upper surface 71 of the insulating layer 70 .
  • the material of the insulating layer 70 may include binary or multi-component compounds composed of silicon (Si), carbon (C), nitrogen (N), oxygen (O) and other elements, such as silicon carbon oxynitride (SiC). x O y N z ), silicon oxycarbide (SiC x O y ), silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ).
  • the material of the insulating layer 70 may also contain one or more elements such as hydrogen (H), fluorine (F), chlorine (Cl), and the like.
  • the insulating material can be deposited first, and then the insulating material can be planarized so that the surface of the insulating material away from the substrate is flush or nearly flush with the top surface of the fin, and then the engraving back process is used to control the engraving back time.
  • the thickness of the insulating layer 70 is controlled so that the upper surface 71 of the insulating layer 70 is lower than the top surface 21 of the fin 20 .
  • the polishing rates in different areas are approximately the same when the insulating material is planarized.
  • the surface of the semiconductor device may be uneven after the insulating material is planarized.
  • a gate oxide layer may be formed.
  • the gate oxide layer is located between the fins 20 and the first sacrificial gates 30 . between the fin 20 and the second sacrificial gate 40 .
  • step S512 is to etch the exposed end portions 42 of the plurality of second sacrificial gates 40 and the fins 20 below the end portions 42 through the first openings 511 to form a first isolation.
  • Slot 601 including:
  • the fin 20 is etched to form a first recess 603 located in the insulating layer 70 and a second recess 604 located on the insulating layer.
  • the first isolation groove 601 includes a first recess 603 and a second recess 604.
  • the first isolation groove 601 includes a plurality of isolation sub-sections 605 spaced apart along the first direction X.
  • Each isolation sub-section 605 includes a first groove 603 and a second groove 604.
  • step S53 etching the interlayer dielectric layer 50 and the fins 20 in the second preset area S4 to form a second isolation trench 602 includes:
  • a second mask layer 52 is formed on the interlayer dielectric layer 50.
  • the second mask layer 52 includes a second opening 521.
  • the second opening 521 extends along the second direction Y and exposes the first
  • the interlayer dielectric layer 50 is between the target sacrificial gate 32 and the second target sacrificial gate 43 .
  • the first target sacrificial gate 32 and the second target sacrificial gate 43 are, along the first direction 40.
  • the second mask layer 52 may be a hard mask.
  • the second opening 521 corresponds to the second preset area S4.
  • the second opening 521 in the second mask layer 52 can be formed by forming a photoresist layer on the second mask layer 52, patterning the photoresist layer, and then based on the patterned photoresist layer. , obtained by etching the second mask layer 52 .
  • the exposed interlayer dielectric layer 50 and the fins 20 below the interlayer dielectric layer 50 are etched through the second opening 521 to form a second isolation trench 602.
  • the preparation method further includes:
  • a dielectric layer 11 is formed.
  • the dielectric layer 11 covers the two opposite sides of the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 in the first direction X.
  • the dielectric layer 11 may be formed after the first sacrificial gate 30 and the second sacrificial gate 40 are formed.
  • the material of the dielectric layer 11 may include silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride carbide, etc.
  • the dielectric layer 11 may be a single-layer structure, and in other examples, the dielectric layer 11 may be a multi-layer structure.
  • the dielectric layer 11 can be used to protect the first sacrificial gate 30 and the second sacrificial gate 40. After the first sacrificial gate 30 is replaced with a first gate and the second sacrificial gate 40 is replaced with a second gate, the dielectric layer 11 will also Can be used to protect the first and second gates.
  • dielectric layer 11 may be a material with a low dielectric constant. In this way, after the first gate and the second gate are formed, the dielectric layer 11 can also be used to reduce the coupling capacitance between the two adjacent first gates in the first direction X, thereby improving the use of the circuit structure in the semiconductor device. stability.
  • the source electrode 12 and the drain electrode 13 are formed on the fin 20. Along the first direction X, the source electrode 12 and the drain electrode 13 are located on both sides of the first sacrificial gate 30 and on both sides of the second sacrificial gate 40 respectively.
  • the source electrode 12 and the drain electrode 13 can be formed on the fin 20 .
  • an epitaxial growth process may be used to form the source electrode 12 and the drain electrode 13 on the fin 20 .
  • the etching stop layer 14 may be formed after the source electrode 12 and the drain electrode 13 are formed on the fin 20 and before the interlayer dielectric layer 50 is formed.
  • step S532 is to etch the exposed interlayer dielectric layer 50 and the fins 20 below the interlayer dielectric layer 50 through the second opening 521 to form a second isolation.
  • Slot 602 including:
  • the interlayer dielectric layer 50 exposed by the second opening 521 is etched to expose the etching stop layer 14 below the interlayer dielectric layer 50.
  • the exposed etching stop layer 14 is etched to expose the source electrode 12 or the drain electrode 13 under the etching stop layer 14.
  • the source electrode 12 may be exposed.
  • the drain electrode 13 may be exposed.
  • the exposed source electrode 12 or drain electrode 13 and the fin 20 below the source electrode 12 or drain electrode 13 are etched to form a second isolation trench 602.
  • the second opening 521 also exposes a portion of the surface of the first target sacrificial gate 32 close to the second target sacrificial gate 43 , and the second target sacrificial gate 43 close to the first target sacrificial gate 32 part of the surface.
  • step S532 during the process of etching the exposed interlayer dielectric layer 50 and the fins 20 below the interlayer dielectric layer 50 through the second opening 521 to form the second isolation trench 602, the first target is also etched. sacrificial gate 32 and Second target sacrificial gate 43.
  • the size of the second opening 521 in the first direction X is larger, and the process of patterning the second mask layer 52 is simpler.
  • the size of the second isolation groove 602 in the first direction X is also larger, and the formed second isolation portion 62 has a larger size in the first direction
  • the first sacrificial gate 30 and the second sacrificial gate 40 are adjacent to each other, thereby better isolating the adjacent first gate and the second gate in the first direction X.
  • the dielectric layer 11 covering the side of the first target sacrificial gate 32 close to the second target sacrificial gate 43 is the first target dielectric layer 111 , covering the etching of the first target dielectric layer 111
  • the stop layer 14 is the first target etching stop layer 141
  • the dielectric layer 11 covering the side of the second target sacrificial gate 43 close to the first target sacrificial gate 32 is the second target dielectric layer 112
  • the etching area covering the second target dielectric layer 112 is
  • the etch stop layer 14 is the second target etch stop layer 142 .
  • the second opening 521 also exposes the end surfaces of the first target dielectric layer 111 , the first target etching stop layer 141 , the second target dielectric layer 112 and the second target etching stop layer 142 away from the substrate 10 .
  • step S53 etching the interlayer dielectric layer 50 and the fins 20 in the second preset area S4 to form a second isolation trench 602 includes:
  • first target dielectric layer 111 As shown in FIG. 51, the remaining first target dielectric layer 111, first target etching stop layer 141, second target dielectric layer 112 and second target etching stop layer 142 are etched.
  • the method of forming the second isolation trench 602 is not limited to this.
  • gaps d7 exist between the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 along the second direction Y.
  • the gap d7 is less than or equal to the distance L1 between the center lines O of two adjacent fins 20 .
  • the gap d7 between the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 is less than or equal to the distance L1 between the center lines O of two adjacent fins 20 , so that the distance between the center lines O of two adjacent fins 20 can be reduced.
  • Both are equipped with a sacrificial gate structure (first sacrificial gate or second sacrificial gate).
  • the sacrificial gate structure is more evenly distributed on the substrate, which is beneficial to improving the uneven distribution of the sacrificial gate structure on the substrate and flattening the interlayer dielectric layer.
  • the surface of the semiconductor device is uneven, and the semiconductor device fails or becomes defective.
  • the preparation method further includes:
  • the first gate 30a may have a single-layer structure.
  • the material of the first gate 30a may include a metal material.
  • the first gate 30a may have a multi-layer structure.
  • the first gate 30a may include a metal layer and a high dielectric constant insulating layer.
  • the second gate 40a may have a single-layer structure.
  • the material of the second gate 40a may include a metal material.
  • the second gate 40a may have a multi-layer structure.
  • the second gate 40a may include a metal layer and a high dielectric constant insulating layer.
  • a semiconductor device 100 is provided.
  • the semiconductor device 100 includes a substrate 10 , a plurality of first fins 201 , a plurality of second fins 202 , a plurality of first gates 30 a , a plurality of second gates 40 a , an interlayer dielectric layer 50 and an isolation structure 60 .
  • the plurality of first fins 201 and the plurality of second fins 202 are provided on the substrate 10 and extend along the first direction X parallel to the substrate 10 .
  • the first fin 201 is disposed on the first area S1 of the substrate 10 .
  • the second fin 202 is disposed on the second area S2 of the substrate 10 .
  • the width of each of the plurality of first fins 201 may be equal.
  • each second fin 202 of the plurality of second fins 202 may be equal.
  • the width of the first fin 201 is the same as the width of the above-mentioned fin 20 .
  • the width of the second fin 202 is the same as the width of the above-mentioned fin 20 . Therefore, in some examples, the width of first fin 201 and the width of second fin 202 may be equal.
  • the spacing between any two adjacent first fins 201 among the plurality of first fins 201 may be equal.
  • the spacing between any two adjacent second fins 202 among the plurality of second fins 202 may be equal.
  • This arrangement can facilitate the production of the first fin 201 and the second fin 202 and simplify the preparation process of the semiconductor device.
  • the plurality of first gates 30a and the plurality of second gates 40a extend along the second direction Y parallel to the substrate 10, and the first direction X intersects the second direction Y.
  • the plurality of first gates 30a are arranged across the plurality of first fins 201, and the plurality of second gates 40a are arranged across the plurality of second fins 202.
  • the first gate 30a is disposed on the first region S1 of the substrate 10 .
  • the second gate 40a is provided on the second region S2 of the substrate 10.
  • the widths of the plurality of second gates 40a may be equal.
  • the spacing between any two adjacent second gates 40a may be equal.
  • This arrangement can facilitate the preparation of the second gate 40a and simplify the preparation process of the semiconductor device.
  • the interlayer dielectric layer 50 covers the area between the plurality of first gates 30a and the area between the plurality of second gates 40a, exposing the surfaces of the plurality of first gates 30a and the plurality of second gates 40a away from the substrate 10.
  • the isolation structure 60 is spaced between a plurality of first fins 201 and a plurality of second fins 202, and a plurality of first gates 30a and a plurality of second gates 40a, and surrounds the plurality of first fins 201 and the plurality of first gates 30a. .
  • the plurality of first fins 201 and the plurality of second fins 202 are made of the same material and are arranged in the same layer.
  • the plurality of first gates 30a and the plurality of second gates 40a are made of the same material and are arranged in the same layer.
  • the plurality of first fins 201 and the plurality of second fins 202 are made of the same material and are arranged on the same layer.
  • the first gate 30a and the plurality of second gates 40a are made of the same material and are arranged in the same layer, that is, the first fin 201 and the second fin 202 are prepared and formed at the same time, and are divided by the fin 20.
  • the first gate 30a and the second gate 40a Preparation and formation at the same time.
  • the semiconductor device provided in some embodiments of the present application is prepared by the preparation method described in any of the above embodiments. Therefore, the beneficial effects that can be achieved by the semiconductor device provided by some embodiments of the present application are the same as the beneficial effects that can be achieved by the preparation method described in any of the above embodiments.
  • the isolation structure 60 includes a first isolation portion 61 and a second isolation portion 62 .
  • the first isolation portion 61 extends along the first direction X, and along the second direction Y, the first isolation portion 61 is located on one side of the plurality of first gates 30a.
  • the second isolation portion 62 extends along the second direction Y, and along the first direction X, the second isolation portion 62 is located on one side of the plurality of first gates 30a.
  • the isolation structure 60 is provided around the first gate 30a, which can better separate the first gate 30a and the second gate 40a and ensure the normal operation of the first gate 30a.
  • the first isolation portion 61 includes a plurality of isolation sub-portions 63 spaced apart along the first direction X.
  • the isolation sub-portions 63 are located on the extension line of the second gate 40a, and the isolation sub-portions
  • the width of 63 in the first direction X is equal to the width of the second gate 40a in the first direction X.
  • the semiconductor device 100 further includes an insulating layer 70 .
  • Parts of the plurality of first fins 201 and the plurality of second fins 202 are embedded in the insulating layer 70 , and the remaining parts protrude from the upper surface 71 of the insulating layer 70 .
  • the isolation sub-portion 63 includes a first portion 631 embedded in the insulating layer 70 and a second portion 632 located on the insulating layer 70 .
  • the size of the first portion 631 in the second direction Y is equal to the size of the second fin 202 in the second direction Y.
  • the semiconductor device 100 further includes a first target dielectric layer 111, a first target etch stop layer 141, a second target dielectric layer 112, and a second target etch stop layer 142.
  • the first target dielectric layer 111 covers the side of the first target gate 31a close to the second target sacrificial gate 41a.
  • the first target etch stop layer 141 covers the first target dielectric layer 111 .
  • the second target dielectric layer 112 covers the side of the second target gate 41a close to the first target sacrificial gate 31a.
  • the second target etch stop layer 142 covers the second target dielectric layer 112 .
  • the second isolation portion 62 is located between the first target etching stop layer 141 and the second target etching stop layer 142 .
  • steps S5321 to S5323 during the process of etching the interlayer dielectric layer 50, the etching stop layer 14, the source electrode 12 or the drain electrode 13, and the fins 20 under the source electrode 12 or the drain electrode 13, it is inevitable that The etching stop layer 14 covering the first target sacrificial gate 32 and the second target sacrificial gate 43 is partially eroded. Therefore, in the obtained semiconductor device 100, the first target etching stop layer 141 and the second target etching stop layer 142 are The thickness of the etching stop layer covering the other first gate 30a or the second gate 40a is thinner.
  • the semiconductor device 100 further includes a first dielectric layer 113 , a second dielectric layer 114 , a first etch stop layer 143 and a second etch stop layer 144 .
  • the first dielectric layer 113 and the second dielectric layer 114 respectively cover two opposite sides of the second isolation part 62 in the first direction X.
  • the first etching stop layer 143 covers the first dielectric layer 113
  • the second etching stop layer 144 covers the second dielectric layer 114 .
  • the isolation structure 60 includes two first isolation portions 61 and two second isolation portions 61.
  • the two first isolation portions 61 are respectively located on opposite sides of the plurality of first gates 30a.
  • the two second isolation portions 62 are respectively located on opposite sides of the plurality of first gates 30a.
  • the two first isolation parts 61 and the two second isolation parts 62 are connected to form a frame shape.
  • the first gates 30a and the second gates 40a are better isolated. , ensuring the working performance of the first gate 30a and improving the performance of the semiconductor device 100.
  • the semiconductor device 100 further includes a third dielectric layer 115 , a source electrode 12 , a drain electrode 13 and a third etching stop layer 145 .
  • the third dielectric layer 115 covers two opposite side surfaces of the plurality of first gates 30a and the plurality of second gates 40a in the first direction X.
  • the source electrode 12 and the drain electrode 13 are located on the plurality of first fins 201 and the plurality of second fins 202.
  • the source electrode 12 and the drain electrode 13 are respectively located on both sides of the first gate 30a and the second gate. 40a on both sides.
  • the third etching stop layer 145 covers the third dielectric layer 115, the source electrode 12 and the drain electrode 13.
  • the size d8 of the first isolation portion 61 in the second direction Y is less than or equal to twice the distance L4 between the center lines M of two adjacent first fins 20 .
  • the centerline M of the first fin 20 extends along the first direction X.
  • the size d8 of the first isolation portion 61 in the second direction Y is smaller, so that after the first isolation portion 61 is formed, the first isolation portion 61 has less impact on the subsequent planarization process, which is beneficial to improving the quality of the semiconductor device. yield and improve the performance of semiconductor devices.
  • At least one first gate group 301a is provided on the substrate 10, and the first gate group 301a includes a plurality of first gates 30a.
  • the size d9 of the second isolation part 62 in the first direction X is less than or equal to the distance L5 between the center lines N of two adjacent first gates 30a in the first gate group 301a adjacent to the second isolation part 62 twice.
  • the center line N of the first gate 30a extends along the second direction Y.
  • the size d9 of the second isolation portion 62 in the first direction yield and improve the performance of semiconductor devices.
  • the electronic device 1000 is, for example, a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, or a financial terminal product.
  • consumer electronic products include mobile phones, tablets, laptops, e-readers, personal computers (PC), personal digital assistants (PDA), desktop monitors, Smart wearable products (such as smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc.
  • Home electronic products include smart door locks, TVs, remote controls, refrigerators, rechargeable small household appliances (such as soymilk machines, sweeping robots), etc.
  • Vehicle-mounted electronic products include car navigation systems, car DVDs, etc.
  • Financial terminal products include ATM machines, self-service terminals, etc. The embodiments of the present application do not place special restrictions on the specific forms of the above-mentioned electronic devices.
  • the above-mentioned electronic device 1000 may include components such as a semiconductor device 100 and a printed circuit board (PCB) 200.
  • the semiconductor device 100 and the printed circuit board 200 are electrically connected to achieve signal interoperability.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present application relates to the technical field of semiconductors. Provided are a semiconductor device and a preparation method therefor, and an electronic device, which are used for solving the problem of semiconductor device surfaces being uneven after the planarization process, so as to increase semiconductor device yield. The preparation method for a semiconductor device comprises: forming a plurality of fins on a substrate; forming a plurality of first sacrificial gates that are located in a first region, and a plurality of second sacrificial gates that are located in a second region; forming an interlayer dielectric layer; planarizing the interlayer dielectric layer to expose the surfaces of the plurality of first sacrificial gates and the plurality of second sacrificial gates that are away from the substrate; and forming an isolation structure, wherein the isolation structure divides the fins into first fins that are located below the plurality of first sacrificial gates, and second fins that are located below the plurality of second sacrificial gates, and the isolation structure surrounding a plurality of first fins and the plurality of first sacrificial gates. The semiconductor device is applied to an electronic device to improve the yield of the electronic device.

Description

半导体器件及其制备方法、电子设备Semiconductor devices and preparation methods thereof, electronic equipment
本申请要求于2022年03月22日提交国家知识产权局、申请号为202210284461.0、申请名称为“半导体器件及其制备方法、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims priority to the Chinese patent application submitted to the State Intellectual Property Office on March 22, 2022, with application number 202210284461.0 and application name "Semiconductor Devices and Preparation Methods and Electronic Equipment", the entire content of which is incorporated by reference. in this application.
技术领域Technical field
本申请涉及半导体技术领域，尤其涉及有一种半导体器件及其制备方法、电子设备。The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method thereof, and electronic equipment.
背景技术Background technique
考虑到源漏外延工艺中的高温处理步骤对互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)中的栅极叠层(gate stack)的性能以及可靠性的影响，半导体制备工艺过程大多从先制备栅极再制备源极和漏极，转变为先制备牺牲栅后制备源极和漏极，再将牺牲栅替换为金属栅极，也即转变为替代金属栅工艺(Replacement Metal Gate，RMG)。Considering the impact of high-temperature processing steps in the source-drain epitaxial process on the performance and reliability of the gate stack in Complementary Metal Oxide Semiconductor (CMOS), most of the semiconductor preparation process starts from the first step. Preparing the gate and then preparing the source and drain changes to preparing the sacrificial gate first and then the source and drain, and then replaces the sacrificial gate with a metal gate, that is, it changes to the replacement metal gate process (Replacement Metal Gate, RMG) .
RMG工艺虽然能够避免源漏外延工艺对栅极的影响，但也会使半导体器件结构更加复杂，从而使器件表面的形貌更加复杂，使得器件的平坦化工艺受到更大挑战。器件在平坦化工艺后，若表面高低不平，则会对后续工艺产生不良影响，最终有可能导致器件失效，良率降低。Although the RMG process can avoid the impact of the source-drain epitaxy process on the gate, it also makes the structure of the semiconductor device more complex, making the topography of the device surface more complex and making the device planarization process more challenging. If the surface of the device is uneven after the planarization process, it will have a negative impact on subsequent processes, which may eventually lead to device failure and reduced yield.
发明内容Contents of the invention
本申请实施例提供一种半导体器件及其制备方法、电子设备，用于改善半导体器件平坦化工艺后表面高低不平的问题，以提高半导体器件的良率。Embodiments of the present application provide a semiconductor device, a preparation method thereof, and electronic equipment, which are used to improve the problem of uneven surfaces after the planarization process of the semiconductor device, so as to improve the yield rate of the semiconductor device.
为达到上述目的，本申请的实施例采用如下技术方案：In order to achieve the above objectives, the embodiments of the present application adopt the following technical solutions:
第一方面，提供了一种半导体器件的制备方法，该制备方法包括：在衬底上形成多条鳍，所述鳍沿平行于所述衬底的第一方向延伸；形成位于第一区域的多条第一牺牲栅和位于第二区域的多条第二牺牲栅，所述第一牺牲栅和所述第二牺牲栅沿平行于所述衬底的第二方向延伸，所述第一方向和所述第二方向相交叉；所述多条第一牺牲栅和所述多条第二牺牲栅跨设在所述多条鳍上，且所述第二区域在所述第一区域的周围；形成层间介质层，所述层间介质层覆盖所述多条第一牺牲栅和所述多条第二牺牲栅；平坦化所述层间介质层，以暴露所述多条第一牺牲栅和所述多条第二牺牲栅远离所述衬底的表面；形成隔离结构，所述隔离结构将所述鳍分割成位于所述多条第一牺牲栅下方的第一鳍和位于所述多条第二牺牲栅下方的第二鳍，所述隔离结构围绕多条所述第一鳍和所述多条第一牺牲栅。In a first aspect, a method for manufacturing a semiconductor device is provided. The preparation method includes: forming a plurality of fins on a substrate, the fins extending in a first direction parallel to the substrate; forming a A plurality of first sacrificial gates and a plurality of second sacrificial gates located in the second region, the first sacrificial gates and the second sacrificial gates extend in a second direction parallel to the substrate, the first direction intersects with the second direction; the plurality of first sacrificial gates and the plurality of second sacrificial gates are arranged across the plurality of fins, and the second area is around the first area ; Form an interlayer dielectric layer, the interlayer dielectric layer covers the plurality of first sacrificial gates and the plurality of second sacrificial gates; Planarize the interlayer dielectric layer to expose the plurality of first sacrificial gates; The gate and the plurality of second sacrificial gates are away from the surface of the substrate; an isolation structure is formed, the isolation structure divides the fin into a first fin located under the plurality of first sacrificial gates and a first fin located under the plurality of first sacrificial gates. second fins below the plurality of second sacrificial gates, and the isolation structure surrounds the plurality of first fins and the plurality of first sacrificial gates.
本申请一些实施例所提供的半导体器件的制备方法中，先在衬底上设置鳍、且在第一区域上设置有第一牺牲栅，在第二区域上设置有第二牺牲栅，然后形成层间介质层，对层间介质层进行平坦化处理，最后形成隔离结构将鳍划分成第一鳍和第二鳍。这样，在进行平坦化处理之前，半导体器件中鳍、第一牺牲栅和第二牺牲栅在衬底上的分布较为均匀，因此在层间介质层平坦化过程中，不容易因衬底上电路结构分布不均匀，不同区域研磨速度不同，出现半导体器件的表面高度差异较大，表面高度不均 匀的问题，从而有效的提高半导体器件的良率，提高半导体器件的性能。In the preparation method of a semiconductor device provided by some embodiments of the present application, fins are first provided on the substrate, a first sacrificial gate is provided on the first region, and a second sacrificial gate is provided on the second region, and then a fin is formed on the substrate. The interlayer dielectric layer flattens the interlayer dielectric layer, and finally forms an isolation structure to divide the fin into a first fin and a second fin. In this way, before the planarization process is performed, the fins, the first sacrificial gate and the second sacrificial gate in the semiconductor device are relatively evenly distributed on the substrate. Therefore, during the planarization process of the interlayer dielectric layer, it is not easy for the circuit on the substrate to The structure distribution is uneven, the grinding speed is different in different areas, the surface height of the semiconductor device is greatly different, and the surface height is uneven. uniformity problem, thereby effectively improving the yield of semiconductor devices and improving the performance of semiconductor devices.
同时，与相关技术中先制备电路结构，再在相邻的两个电路结构间隙中设置虚设结构，电路结构与虚设结构之间的间隙较大的情况相比，本申请一些实施例所提供的半导体器件的制备方法中，间隔在第一鳍和第二鳍，第一牺牲栅和第二牺牲栅之间的隔离结构的尺寸可以更小，从而不容易对后续其他平坦化工艺产生影响，进一步提高了半导体器件的良率，提高了半导体器件的性能。At the same time, compared with the situation in the related art where the circuit structure is first prepared and then a dummy structure is set up in the gap between two adjacent circuit structures, and the gap between the circuit structure and the dummy structure is large, some embodiments of the present application provide In the preparation method of the semiconductor device, the size of the isolation structure spaced between the first fin and the second fin, and the first sacrificial gate and the second sacrificial gate can be smaller, so that it is not easy to affect other subsequent planarization processes, and further The yield rate of the semiconductor device is improved and the performance of the semiconductor device is improved.
在一些实施例中，所述形成隔离结构，包括：刻蚀第一预设区域内的第二牺牲栅和鳍，形成第一隔离槽；沿所述第二方向，所述第一预设区域位于所述多条第一牺牲栅的一侧，所述第一隔离槽沿所述第一方向延伸。在所述第一隔离槽内形成第一隔离部。刻蚀第二预设区域内的层间介质层和鳍，形成第二隔离槽；沿所述第一方向，所述第二预设区域位于所述多条第一牺牲栅的一侧，所述第二隔离槽沿所述第二方向延伸。在所述第二隔离槽内形成第二隔离部。其中，所述隔离结构包括所述第一隔离部和所述第二隔离部。这样，利用第一隔离部和第二隔离部能够较好的将第一牺牲栅和第二牺牲栅间隔开，从而在将第一牺牲栅替换成第一栅，将第二牺牲栅替换成第二栅后，将第一栅和第二栅更好的间隔开，保证第一栅的使用性能。In some embodiments, forming the isolation structure includes: etching the second sacrificial gate and the fin in the first preset area to form a first isolation trench; along the second direction, the first preset area Located on one side of the plurality of first sacrificial gates, the first isolation trench extends along the first direction. A first isolation part is formed in the first isolation groove. Etch the interlayer dielectric layer and fins in the second preset area to form a second isolation trench; along the first direction, the second preset area is located on one side of the plurality of first sacrificial gates, so The second isolation groove extends along the second direction. A second isolation part is formed in the second isolation groove. Wherein, the isolation structure includes the first isolation part and the second isolation part. In this way, the first isolation part and the second isolation part can be used to better separate the first sacrificial gate and the second sacrificial gate, so that the first sacrificial gate is replaced with the first gate, and the second sacrificial gate is replaced with the third sacrificial gate. After the second gate, the first gate and the second gate are better separated to ensure the performance of the first gate.
在一些实施例中，所述第一隔离部在所述第二方向上的尺寸小于或等于，相邻两个鳍的中心线之间的距离的二倍；和/或，所述衬底上设有至少一个第一牺牲栅组，所述第一牺牲栅组包括多条所述第一牺牲栅；所述第二隔离部在所述第一方向上的尺寸小于或等于，与所述第二隔离部相邻的第一牺牲栅组中相邻两个第一牺牲栅的中心线之间的距离的二倍。这样，第一隔离部在第二方向上的尺寸较小，第二隔离部在第一方向上的尺寸也较小，从而在后续进行其他平坦化工艺过程中，不容易因第一隔离部和/或第二隔离部的设置，导致半导体器件表面出现明显的高度差异，从而进一步提高了半导体器件的良率。In some embodiments, the size of the first isolation portion in the second direction is less than or equal to twice the distance between the center lines of two adjacent fins; and/or, on the substrate At least one first sacrificial gate group is provided, and the first sacrificial gate group includes a plurality of first sacrificial gates; the size of the second isolation portion in the first direction is less than or equal to that of the first sacrificial gate group. The distance between the center lines of two adjacent first sacrificial gates in the first sacrificial gate group adjacent to the two isolation parts is twice. In this way, the size of the first isolation part in the second direction is smaller, and the size of the second isolation part in the first direction is also smaller. Therefore, during other subsequent planarization processes, it is not easy to cause the first isolation part and the second isolation part to have a small size in the first direction. /or the provision of the second isolation portion results in an obvious height difference on the surface of the semiconductor device, thereby further improving the yield of the semiconductor device.
在一些实施例中，所述刻蚀第一预设区域内的第二牺牲栅和鳍，形成第一隔离槽，包括：在所述层间介质层上形成第一掩膜层，所述第一掩膜层包括第一开口，所述第一开口沿所述第一方向延伸，且暴露多条所述第二牺牲栅靠近所述多条第一牺牲栅的端部。经由所述第一开口，刻蚀多条所述第二牺牲栅所暴露的端部，以及所述端部下方的鳍，形成第一隔离槽。In some embodiments, etching the second sacrificial gate and the fin in the first preset area to form a first isolation trench includes: forming a first mask layer on the interlayer dielectric layer, and the third A mask layer includes a first opening extending along the first direction and exposing ends of a plurality of second sacrificial gates close to the plurality of first sacrificial gates. Through the first opening, the exposed ends of the plurality of second sacrificial gates and the fins below the ends are etched to form first isolation trenches.
在一些实施例中，在所述形成多条第一牺牲栅和多条第二牺牲栅之前，所述制备方法还包括：在所述衬底上形成绝缘层，所述鳍的部分嵌入所述绝缘层中，其余部分凸出于所述绝缘层的上表面。所述经由所述第一开口，刻蚀所述多条第二牺牲栅所暴露的端部，以及所述端部下方的鳍，形成第一隔离槽，包括：刻蚀所述第一开口所暴露的多条所述第二牺牲栅的端部，暴露出所述端部下方的鳍。刻蚀所述鳍，形成位于所述绝缘层中的第一凹陷，和位于所述绝缘层上的第二凹陷。其中，所述第一隔离槽包括所述第一凹陷和所述第二凹陷。In some embodiments, before forming the plurality of first sacrificial gates and the plurality of second sacrificial gates, the preparation method further includes: forming an insulating layer on the substrate, and a portion of the fin is embedded in the The rest of the insulating layer protrudes from the upper surface of the insulating layer. and etching the exposed ends of the plurality of second sacrificial gates and the fins below the ends through the first opening to form a first isolation trench, including: etching the exposed ends of the first opening. The exposed ends of the plurality of second sacrificial gates expose the fins below the ends. The fin is etched to form a first recess in the insulating layer and a second recess on the insulating layer. Wherein, the first isolation groove includes the first recess and the second recess.
在一些实施例中，所述刻蚀第二预设区域内的层间介质层和鳍，形成第二隔离槽，包括：在所述层间介质层上形成第二掩膜层，所述第二掩膜层包括第二开口，所述第二开口沿所述第二方向延伸，且暴露第一目标牺牲栅和第二目标牺牲栅之间的层间介质层；所述第一目标牺牲栅和所述第二目标牺牲栅为，沿所述第一方向，所述多条第 一牺牲栅和所述多条第二牺牲栅中距离最近的第一牺牲栅和第二牺牲栅。经由所述第二开口，刻蚀所暴露的层间介质层，以及所述层间介质层下方的鳍，形成第二隔离槽。这样，在形成第二隔离槽的过程中，刻蚀的材料较少，刻蚀工艺简单，有利于提高半导体器件的制备效率。In some embodiments, etching the interlayer dielectric layer and the fins in the second preset area to form a second isolation trench includes: forming a second mask layer on the interlayer dielectric layer, and the third The second mask layer includes a second opening extending along the second direction and exposing an interlayer dielectric layer between the first target sacrificial gate and the second target sacrificial gate; the first target sacrificial gate and the second target sacrificial gate is, along the first direction, the plurality of A sacrificial gate and the closest first sacrificial gate and second sacrificial gate among the plurality of second sacrificial gates. Through the second opening, the exposed interlayer dielectric layer and the fins below the interlayer dielectric layer are etched to form a second isolation trench. In this way, during the process of forming the second isolation trench, less material is etched, and the etching process is simple, which is beneficial to improving the preparation efficiency of the semiconductor device.
在一些实施例中，在所述形成层间介质层之前，所述制备方法还包括：形成介质层，所述介质层覆盖所述多条第一牺牲栅和所述多条第二牺牲栅在所述第一方向上相对的两个侧面。在所述鳍上形成源极和漏极；沿所述第一方向，所述源极和所述漏极分别位于所述第一牺牲栅的两侧，以及所述第二牺牲栅的两侧。形成刻蚀停止层，所述刻蚀停止层覆盖所述介质层，以及所述源极和所述漏极。In some embodiments, before forming the interlayer dielectric layer, the preparation method further includes: forming a dielectric layer covering the plurality of first sacrificial gates and the plurality of second sacrificial gates. Two opposite sides in the first direction. A source electrode and a drain electrode are formed on the fin; along the first direction, the source electrode and the drain electrode are respectively located on both sides of the first sacrificial gate and on both sides of the second sacrificial gate. . An etching stop layer is formed, covering the dielectric layer, the source electrode and the drain electrode.
在一些实施例中，所述经由所述第二开口，刻蚀所暴露的层间介质层，以及所述层间介质层下方的鳍，形成第二隔离槽，包括：刻蚀所述第二开口所暴露的层间介质层，暴露出所述层间介质层下方的刻蚀停止层。刻蚀所暴露的刻蚀停止层，暴露出所述刻蚀停止层下方的源极或漏极。刻蚀所暴露的源极或漏极，以及所述源极或所述漏极下方的鳍，形成所述第二隔离槽。In some embodiments, etching the exposed interlayer dielectric layer and the fins under the interlayer dielectric layer through the second opening to form a second isolation trench includes: etching the second The interlayer dielectric layer exposed by the opening exposes the etching stop layer below the interlayer dielectric layer. The exposed etching stop layer is etched to expose the source electrode or drain electrode under the etching stop layer. The exposed source electrode or drain electrode and the fin under the source electrode or drain electrode are etched to form the second isolation trench.
在一些实施例中，所述第二开口还暴露所述第一目标牺牲栅靠近所述第二目标牺牲栅的部分表面，以及所述第二目标牺牲栅靠近所述第一目标牺牲栅的部分表面。在所述经由所述第二开口，刻蚀所暴露的层间介质层，以及所述层间介质层下方的鳍，形成第二隔离槽的过程中，还刻蚀所述第一目标牺牲栅和所述第二目标牺牲栅。这样，第二开口在第一方向上的尺寸较大，图案化第二掩膜层的工艺较为简单。同时，第二隔离槽在第一方向上的尺寸也较大，第二隔离部的尺寸也随之较大，从而能够更好的将第一牺牲栅和第二牺牲栅间隔开，也将后续形成的第一栅和第二栅间隔开。In some embodiments, the second opening also exposes a portion of the surface of the first target sacrificial gate close to the second target sacrificial gate, and a portion of the second target sacrificial gate close to the first target sacrificial gate. surface. During the process of etching the exposed interlayer dielectric layer and the fins under the interlayer dielectric layer through the second opening to form a second isolation trench, the first target sacrificial gate is also etched. and the second target sacrificial gate. In this way, the size of the second opening in the first direction is larger, and the process of patterning the second mask layer is simpler. At the same time, the size of the second isolation trench in the first direction is also larger, and the size of the second isolation part is also larger accordingly, so that the first sacrificial gate and the second sacrificial gate can be better separated, and the subsequent The first gate and the second gate are formed to be spaced apart.
在一些实施例中，覆盖所述第一目标牺牲栅靠近所述第二目标牺牲栅的侧面的介质层为第一目标介质层，覆盖所述第一目标介质层的刻蚀停止层为第一目标刻蚀停止层，覆盖所述第二目标牺牲栅靠近所述第一目标牺牲栅的侧面的介质层为第二目标介质层，覆盖所述第二目标介质层的刻蚀停止层为第二目标刻蚀停止层。所述第二开口还暴露所述第一目标介质层、所述第一目标刻蚀停止层、所述第二目标介质层和所述第二目标刻蚀停止层远离所述衬底的端面。In some embodiments, the dielectric layer covering the side of the first target sacrificial gate close to the second target sacrificial gate is a first target dielectric layer, and the etching stop layer covering the first target dielectric layer is a first target dielectric layer. Target etch stop layer, the dielectric layer covering the side of the second target sacrificial gate close to the first target sacrificial gate is a second target dielectric layer, and the etch stop layer covering the second target dielectric layer is a second target etch stop layer. Target etch stop layer. The second opening also exposes end surfaces of the first target dielectric layer, the first target etch stop layer, the second target dielectric layer and the second target etch stop layer away from the substrate.
所述刻蚀第二预设区域内的层间介质层和鳍，形成第二隔离槽，包括：经由所述第二开口，同步刻蚀所述第一目标牺牲栅、所述第一目标介质层、所述第一目标刻蚀停止层、所述第二目标牺牲栅、所述第二目标介质层、所述第二目标刻蚀停止层，以及所述第一目标牺牲栅和所述第二目标牺牲栅之间的层间介质层，形成第三凹陷；沿垂直于所述衬底的方向，所述第三凹陷的底面与位于所述第一目标牺牲栅和所述第二目标牺牲栅之间的源极或漏极的上表面之间具有间距。刻蚀剩余的第一目标介质层、第一目标刻蚀停止层、第二目标介质层和第二目标刻蚀停止层。刻蚀所述第一目标牺牲栅和所述第二目标牺牲栅之间剩余的层间介质层，暴露出所述层间介质层下方的刻蚀停止层。刻蚀剩余的第一目标牺牲栅和第二目标牺牲栅、暴露出的刻蚀停止层、所述刻蚀停止层下方的源极或漏极，以及所述源极或所述漏极下方的鳍，形成第二隔离槽。The etching of the interlayer dielectric layer and the fins in the second preset area to form a second isolation trench includes: simultaneously etching the first target sacrificial gate and the first target dielectric through the second opening. layer, the first target etch stop layer, the second target sacrificial gate, the second target dielectric layer, the second target etch stop layer, the first target sacrificial gate and the third target etch stop layer. The interlayer dielectric layer between the two target sacrificial gates forms a third recess; along the direction perpendicular to the substrate, the bottom surface of the third recess is in contact with the first target sacrificial gate and the second target sacrificial gate. There is a spacing between the gates and the upper surface of the source or drain. The remaining first target dielectric layer, first target etching stop layer, second target dielectric layer and second target etching stop layer are etched. The remaining interlayer dielectric layer between the first target sacrificial gate and the second target sacrificial gate is etched to expose the etching stop layer under the interlayer dielectric layer. Etch the remaining first target sacrificial gate and the second target sacrificial gate, the exposed etch stop layer, the source electrode or the drain electrode below the etch stop layer, and the source electrode or the drain electrode below. fins to form a second isolation groove.
在一些实施例中，在形成隔离结构之前，沿所述第二方向，所述多条第一牺牲栅 与所述多条第二牺牲栅之间存在间隙。所述间隙小于或等于相邻两条鳍的中心线之间的距离。这样，各条鳍上可以均设置有第一牺牲栅或第二牺牲栅，使得第一牺牲栅和第二牺牲栅在衬底上均匀分布，从而有利于改善因衬底上牺牲栅结构分布不均匀，导致的半导体器件在平坦化工艺后表面高低不平的问题，提高半导体器件的良率，提高半导体器件的性能。In some embodiments, before forming the isolation structure, along the second direction, the plurality of first sacrificial gates There are gaps between the plurality of second sacrificial gates. The gap is less than or equal to the distance between the center lines of two adjacent fins. In this way, each fin can be provided with a first sacrificial gate or a second sacrificial gate, so that the first sacrificial gate and the second sacrificial gate are evenly distributed on the substrate, which is beneficial to improving the uneven distribution of the sacrificial gate structure on the substrate. Uniformity causes the problem of uneven surfaces of semiconductor devices after the planarization process, improves the yield rate of semiconductor devices, and improves the performance of semiconductor devices.
在一些实施例中，所述制备方法还包括：将所述第一牺牲栅替换成第一栅，将所述第二牺牲栅替换成第二栅。In some embodiments, the preparation method further includes: replacing the first sacrificial gate with a first gate, and replacing the second sacrificial gate with a second gate.
第二方面，提供了一种半导体器件，该半导体器件包括衬底、多条第一鳍和多条第二鳍、多条第一栅和多条第二栅、层间介质层和隔离结构。多条第一鳍和多条第二鳍，设于所述衬底上，且沿平行于所述衬底的第一方向延伸。多条第一栅和多条第二栅，沿平行于所述衬底的第二方向延伸，所述第一方向与所述第二方向相交叉；所述多条第一栅跨设在所述多条第一鳍上，所述多条第二栅跨设在所述多条第二鳍上。所述层间介质层覆盖所述多条第一栅之间的区域和所述多条第二栅之间的区域，暴露出所述多条第一栅和所述多条第二栅远离所述衬底的表面。隔离结构，间隔所述多条第一鳍和所述多条第二鳍，以及间隔所述多条第一栅和所述多条第二栅，且围绕所述多条第一鳍和所述多条第一栅。其中，所述多条第一鳍和所述多条第二鳍材料相同且同层设置，所述多条第一栅和所述多条第二栅材料相同且同层设置。A second aspect provides a semiconductor device, which includes a substrate, a plurality of first fins and a plurality of second fins, a plurality of first gates and a plurality of second gates, an interlayer dielectric layer and an isolation structure. A plurality of first fins and a plurality of second fins are provided on the substrate and extend in a first direction parallel to the substrate. A plurality of first gates and a plurality of second gates extend along a second direction parallel to the substrate, and the first direction intersects the second direction; the plurality of first gates are provided across the On the plurality of first fins, the plurality of second gates are provided across the plurality of second fins. The interlayer dielectric layer covers the area between the plurality of first gates and the area between the plurality of second gates, exposing the plurality of first gates and the plurality of second gates away from the the surface of the substrate. Isolation structure, spaced between the plurality of first fins and the plurality of second fins, spaced between the plurality of first gates and the plurality of second gates, and surrounding the plurality of first fins and the plurality of second gates Multiple first gates. Wherein, the plurality of first fins and the plurality of second fins are made of the same material and are arranged in the same layer, and the plurality of first gates and the plurality of second gates are made of the same material and are arranged in the same layer.
本申请一些实施例所提供的半导体器件中，第一鳍和第二鳍材料相同且同层设置，第一栅和第二栅材料相同，且同层设置，即第一鳍和第二鳍均由鳍切割得到，第一栅和第二栅同时制备。因此，在半导体器件的制备过程中，是在衬底上先均匀铺设鳍，形成第一栅所对应的第一牺牲栅和第二栅对应的第二牺牲栅，然后形成层间介质层，平坦化层间介质层，最后形成隔离结构将鳍分割成第一鳍和第二鳍，且将第一牺牲栅和第二牺牲栅间隔开来的。这样，在进行平坦化处理之前，半导体器件中鳍、第一牺牲栅和第二牺牲栅在衬底上的分布较为均匀，因此在层间介质层平坦化过程中，不容易因衬底上电路结构分布不均匀，不同区域研磨速度不同，出现半导体器件的表面高度差异较大，表面高度不均匀的问题，从而有效的提高半导体器件的良率，提高半导体器件的性能。In the semiconductor device provided by some embodiments of the present application, the first fin and the second fin are made of the same material and are arranged in the same layer, and the first gate and the second gate are made of the same material and are arranged in the same layer, that is, the first fin and the second fin are both Cut from fins, the first gate and the second gate are prepared simultaneously. Therefore, in the preparation process of semiconductor devices, fins are first laid evenly on the substrate to form a first sacrificial gate corresponding to the first gate and a second sacrificial gate corresponding to the second gate, and then an interlayer dielectric layer is formed to flatten the semiconductor device. The interlayer dielectric layer is formed, and finally an isolation structure is formed to divide the fin into a first fin and a second fin, and to separate the first sacrificial gate and the second sacrificial gate. In this way, before the planarization process, the distribution of the fins, the first sacrificial gate and the second sacrificial gate in the semiconductor device on the substrate is relatively uniform. Therefore, during the planarization process of the interlayer dielectric layer, it is not easy for the circuit on the substrate to The structure is unevenly distributed and the grinding speed is different in different areas. The surface height of the semiconductor device is greatly different and the surface height is uneven. This can effectively improve the yield of the semiconductor device and improve the performance of the semiconductor device.
同时，与相关技术中先制备电路结构，再在相邻的两个电路结构间隙中设置虚设结构，电路结构与虚设结构之间的间隙较大的情况相比，本申请一些实施例所提供的半导体器件中，间隔在第一鳍和第二鳍，第一牺牲栅和第二牺牲栅之间的隔离结构的尺寸可以更小，从而不容易对后续其他平坦化工艺产生影响，进一步提高了半导体器件的良率，提高了半导体器件的性能。At the same time, compared with the situation in the related art where the circuit structure is first prepared and then a dummy structure is set up in the gap between two adjacent circuit structures, and the gap between the circuit structure and the dummy structure is large, some embodiments of the present application provide In the semiconductor device, the size of the isolation structure spaced between the first fin and the second fin, and the first sacrificial gate and the second sacrificial gate can be smaller, so that it is not easy to affect other subsequent planarization processes, further improving the efficiency of the semiconductor device. The device yield rate improves the performance of semiconductor devices.
在一些实施例中，所述隔离结构包括第一隔离部和第二隔离部。第一隔离部，沿所述第一方向延伸，且沿所述第二方向，所述第一隔离部位于所述多条第一栅的一侧。第二隔离部，沿所述第二方向延伸，且沿所述第一方向，所述第二隔离部位于所述多条第一栅的一侧。这样，在第一方向和第二方向上均可以较好的将第一栅和第二栅间隔开。In some embodiments, the isolation structure includes a first isolation portion and a second isolation portion. A first isolation portion extends along the first direction, and along the second direction, the first isolation portion is located on one side of the plurality of first gates. The second isolation part extends along the second direction, and is located on one side of the plurality of first gates along the first direction. In this way, the first gate and the second gate can be well spaced apart in both the first direction and the second direction.
在一些实施例中，所述第一隔离部包括沿所述第一方向间隔排列的多个隔离子部，所述隔离子部位于所述第二栅的延长线上，且所述隔离子部在所述第一方向上的宽度 与所述第二栅在所述第一方向上的宽度相等。In some embodiments, the first isolation portion includes a plurality of isolation sub-portions spaced apart along the first direction, the isolation sub-portions are located on an extension line of the second gate, and the isolation sub-portions The width in the first direction It is equal to the width of the second gate in the first direction.
在一些实施例中，半导体器件还包括绝缘层。所述多条第一鳍和所述多条第二鳍的部分嵌入所述绝缘层中，其余部分凸出于所述绝缘层的上表面。所述隔离子部包括嵌入所述绝缘层中的第一部分和位于所述绝缘层上的第二部分；所述第一部分在所述第二方向上的尺寸与所述第二鳍在所述第二方向上的尺寸相等。In some embodiments, the semiconductor device further includes an insulating layer. Parts of the first fins and the second fins are embedded in the insulating layer, and the remaining parts protrude from the upper surface of the insulating layer. The isolation sub-portion includes a first part embedded in the insulating layer and a second part located on the insulating layer; the size of the first part in the second direction is consistent with the size of the second fin in the second direction. The dimensions in both directions are equal.
在一些实施例中，沿所述第一方向，所述多条第一栅和所述多条第二栅中距离最近的第一栅和第二栅，分别为第一目标栅和所述第二目标栅。所述半导体器件还包括：覆盖所述第一目标栅靠近所述第二目标牺牲栅的侧面的第一目标介质层；覆盖所述第一目标介质层的第一目标刻蚀停止层；覆盖所述第二目标栅靠近所述第一目标牺牲栅的侧面的第二目标介质层；覆盖所述第二目标介质层的第二目标刻蚀停止层。其中，沿所述第一方向，所述第二隔离部位于所述第一目标刻蚀停止层和所述第二目标刻蚀停止层之间。In some embodiments, along the first direction, the closest first gate and second gate among the plurality of first gates and the plurality of second gates are the first target gate and the third gate respectively. Two target grid. The semiconductor device further includes: a first target dielectric layer covering a side of the first target gate close to the second target sacrificial gate; a first target etching stop layer covering the first target dielectric layer; a second target dielectric layer on the side of the second target gate close to the first target sacrificial gate; and a second target etching stop layer covering the second target dielectric layer. Wherein, along the first direction, the second isolation portion is located between the first target etching stop layer and the second target etching stop layer.
在一些实施例中，所述半导体器件还包括：第一介质层和第二介质层，分别覆盖所述第二隔离部在所述第一方向上相对的两个侧面。第一刻蚀停止层和第二刻蚀停止层，所述第一刻蚀停止层覆盖所述第一介质层，所述第二刻蚀停止层覆盖所述第二介质层。In some embodiments, the semiconductor device further includes: a first dielectric layer and a second dielectric layer respectively covering two opposite sides of the second isolation part in the first direction. A first etching stop layer and a second etching stop layer, the first etching stop layer covers the first dielectric layer, and the second etching stop layer covers the second dielectric layer.
在一些实施例中，所述隔离结构包括两个所述第一隔离部和两个所述第二隔离部，沿所述第二方向，两个所述第一隔离部分别位于所述多条第一栅的相对两侧；沿所述第一方向，两个所述第二隔离部分别位于所述多条第一栅的相对两侧；两个所述第一隔离部和两个所述第二隔离部相连成框形。In some embodiments, the isolation structure includes two first isolation parts and two second isolation parts. Along the second direction, the two first isolation parts are respectively located on the plurality of strips. Opposite sides of the first gate; along the first direction, two second isolation parts are located on opposite sides of the plurality of first gates; two first isolation parts and two The second isolation parts are connected to form a frame shape.
在一些实施例中，所述半导体器件还包括第三介质层、源极和漏极，以及第三刻蚀停止层。第三介质层，覆盖所述多条第一栅和所述多条第二栅在所述第一方向上的相对的两个侧面；源极和漏极，位于所述多条第一鳍和所述多条第二鳍上；沿所述第一方向，所述源极和所述漏极分别位于所述第一栅的两侧和所述第二栅的两侧；第三刻蚀停止层，覆盖所述第三介质层、所述源极和所述漏极。In some embodiments, the semiconductor device further includes a third dielectric layer, a source electrode and a drain electrode, and a third etching stop layer. A third dielectric layer covers two opposite sides of the plurality of first gates and the plurality of second gates in the first direction; a source electrode and a drain electrode located on the plurality of first fins and On the plurality of second fins; along the first direction, the source electrode and the drain electrode are respectively located on both sides of the first gate and on both sides of the second gate; a third etching stop layer covering the third dielectric layer, the source electrode and the drain electrode.
在一些实施例中，所述第一隔离部在所述第二方向上的尺寸小于或等于，相邻两个第一鳍的中心线之间的距离的二倍；和/或，所述衬底上设有至少一个第一栅组，所述第一栅组包括多条所述第一栅；所述第二隔离部在所述第一方向上的尺寸小于或等于，与所述第二隔离部相邻的第一栅组中相邻两个第一栅的中心线之间的距离的二倍。通过这样设置，第一隔离部和/或第二隔离部的尺寸较小，在后续进行其他平坦化工艺时，不容易因第一隔离部和/或第二隔离部与第一栅、第二栅的材料不同，出现平坦化工艺后半导体器件表面高低不平的问题，有效的提高了半导体器件的良率。In some embodiments, the size of the first isolation portion in the second direction is less than or equal to twice the distance between the center lines of two adjacent first fins; and/or the lining At least one first grid group is provided on the bottom, and the first grid group includes a plurality of the first grids; the size of the second isolation part in the first direction is less than or equal to that of the second isolation part. The distance between the center lines of two adjacent first gates in the first gate group adjacent to the isolation part is twice. By being arranged in this way, the size of the first isolation part and/or the second isolation part is smaller. When other planarization processes are subsequently performed, it is not easy for the first isolation part and/or the second isolation part to interact with the first gate and the second isolation part. The gate materials are different, and the surface of the semiconductor device is uneven after the planarization process, which effectively improves the yield rate of the semiconductor device.
在一些实施例中，所述多条第一鳍和所述多条第二鳍的宽度相等；和/或，所述多条第一鳍和所述多条第二鳍中任意相邻两条鳍之间的间距相等；和/或，所述多条第二栅的宽度相等；和/或，任意相邻两条所述第二栅之间的间距相等。这样，第一鳍、第二鳍以及第二栅的分别较为均匀，在制备半导体器件时，鳍和第二牺牲栅的分布较为均匀，从而有效的改善了因结构分布不均匀导致研磨速率不同，半导体器件表面高度不同的问题，提高了半导体器件的良率。In some embodiments, the widths of the plurality of first fins and the plurality of second fins are equal; and/or, any two adjacent ones of the plurality of first fins and the plurality of second fins are The spacing between the fins is equal; and/or the widths of the plurality of second gates are equal; and/or the spacing between any two adjacent second gates is equal. In this way, the distribution of the first fin, the second fin and the second gate is relatively uniform. When preparing a semiconductor device, the distribution of the fin and the second sacrificial gate is relatively uniform, thereby effectively improving the different polishing rates caused by uneven structural distribution. The problem of different surface heights of semiconductor devices improves the yield of semiconductor devices.
第三方面，提供了一种电子设备，该电子设备包括印刷电路板和上述第二方面任 一实施例所述的半导体器件；所述半导体器件和所述印刷电路板电连接。In a third aspect, an electronic device is provided. The electronic device includes a printed circuit board and any of the above-mentioned second aspects. The semiconductor device according to an embodiment; the semiconductor device and the printed circuit board are electrically connected.
附图说明Description of the drawings
图1为本申请实施例提供的一种半导体器件的制备方法的流程图；Figure 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;
图2A～图7为图1所示流程图中各步骤对应的半导体器件的结构图；Figures 2A to 7 are structural diagrams of semiconductor devices corresponding to each step in the flow chart shown in Figure 1;
图8为本申请实施例提供的一种半导体器件的俯视图；Figure 8 is a top view of a semiconductor device provided by an embodiment of the present application;
图9为本申请实施例提供的另一种半导体器件的制备方法的流程图；Figure 9 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present application;
图10为本申请实施例提供的一种半导体器件的俯视图；Figure 10 is a top view of a semiconductor device provided by an embodiment of the present application;
图11为图10在D-D’处的截面图；Figure 11 is a cross-sectional view at D-D’ in Figure 10;
图12为本申请实施例提供的一种半导体器件的立体图；Figure 12 is a perspective view of a semiconductor device provided by an embodiment of the present application;
图13为本申请实施例提供的又一种半导体器件的制备方法的流程图；Figure 13 is a flow chart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present application;
图14为本申请实施例提供的一种基底的立体图；Figure 14 is a perspective view of a substrate provided by an embodiment of the present application;
图15为本申请实施例提供的另一种半导体器件的俯视图；Figure 15 is a top view of another semiconductor device provided by an embodiment of the present application;
图16为本申请实施例提供的又一种半导体器件的立体图；Figure 16 is a perspective view of yet another semiconductor device provided by an embodiment of the present application;
图17为图15在F-F’处的截面图；Figure 17 is a cross-sectional view at F-F’ in Figure 15;
图18为本申请实施例提供的又一种半导体器件的立体图；Figure 18 is a perspective view of yet another semiconductor device provided by an embodiment of the present application;
图19为本申请实施例提供的一种半导体器件的结构；Figure 19 is a structure of a semiconductor device provided by an embodiment of the present application;
图20为本申请实施例提供的再一种半导体器件的俯视图；Figure 20 is a top view of yet another semiconductor device provided by an embodiment of the present application;
图21为图20在G-G’处的截面图；Figure 21 is a cross-sectional view at G-G’ in Figure 20;
图22为本申请实施例提供的又一种半导体器件的立体图；Figure 22 is a perspective view of yet another semiconductor device provided by an embodiment of the present application;
图23为本申请实施例提供的又一种半导体器件的俯视图；Figure 23 is a top view of another semiconductor device provided by the embodiment of the present application;
图24为图23在H-H’处的截面图；Figure 24 is a cross-sectional view at H-H' in Figure 23;
图25为图23在I-I’处的截面图；Figure 25 is a cross-sectional view of Figure 23 at I-I';
图26为本申请实施例提供的又一种半导体器件的制备方法的流程图；Figure 26 is a flow chart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present application;
图27为本申请实施例提供的又一种半导体器件的俯视图；Figure 27 is a top view of another semiconductor device provided by the embodiment of the present application;
图28为本申请实施例提供的又一种半导体器件的俯视图；Figure 28 is a top view of another semiconductor device provided by the embodiment of the present application;
图29为本申请实施例提供的又一种半导体器件的俯视图；Figure 29 is a top view of another semiconductor device provided by the embodiment of the present application;
图30为本申请实施例提供的又一种半导体器件的俯视图；Figure 30 is a top view of another semiconductor device provided by the embodiment of the present application;
图31为本申请实施例提供的又一种半导体器件的俯视图；Figure 31 is a top view of another semiconductor device provided by the embodiment of the present application;
图32为本申请实施例提供的又一种半导体器件的制备方法的流程图；Figure 32 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application;
图33～图34为图32所示流程图中各步骤对应的半导体器件的结构图；Figures 33 to 34 are structural diagrams of semiconductor devices corresponding to each step in the flow chart shown in Figure 32;
图35为本申请实施例提供的又一种半导体器件的制备方法的流程图；Figure 35 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application;
图36为本申请实施例提供的又一种半导体器件的立体图；Figure 36 is a perspective view of yet another semiconductor device provided by an embodiment of the present application;
图37为本申请实施例提供的又一种半导体器件的结构图；Figure 37 is a structural diagram of yet another semiconductor device provided by an embodiment of the present application;
图38为本申请实施例提供的又一种半导体器件的制备方法的流程图；Figure 38 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application;
图39为本申请实施例提供的一种半导体器件的状态图；Figure 39 is a state diagram of a semiconductor device provided by an embodiment of the present application;
图40为本申请实施例提供的又一种半导体器件的俯视图；Figure 40 is a top view of another semiconductor device provided by an embodiment of the present application;
图41为本申请实施例提供的又一种半导体器件的制备方法的流程图；Figure 41 is a flow chart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present application;
图42和图43为图41所示流程图中各步骤对应的半导体器件的结构图；Figures 42 and 43 are structural diagrams of semiconductor devices corresponding to each step in the flow chart shown in Figure 41;
图44为本申请实施例提供的又一种半导体器件的制备方法的流程图； Figure 44 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application;
图45为本申请实施例提供的又一种半导体器件的制备方法的流程图；Figure 45 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application;
图46～图48为图45所示流程图中各步骤对应的半导体器件的结构图；Figures 46 to 48 are structural diagrams of semiconductor devices corresponding to each step in the flow chart shown in Figure 45;
图49为本申请实施例提供的又一种半导体器件的制备方法的流程图；Figure 49 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application;
图50～图53为图49所示流程图中各步骤对应的半导体器件的状态图；Figures 50 to 53 are state diagrams of the semiconductor devices corresponding to each step in the flow chart shown in Figure 49;
图54为本申请实施例提供的又一种半导体器件的制备方法的流程图；Figure 54 is a flow chart of yet another method of manufacturing a semiconductor device provided by an embodiment of the present application;
图55为本申请实施例提供的又一种半导体器件的俯视图；Figure 55 is a top view of another semiconductor device provided by the embodiment of the present application;
图56为本申请实施例提供的又一种半导体器件的俯视图；Figure 56 is a top view of another semiconductor device provided by the embodiment of the present application;
图57为图56在J-J’处的截面图；Figure 57 is a cross-sectional view at J-J’ of Figure 56;
图58为图56在K-K’处的截面图；Figure 58 is a cross-sectional view at K-K’ in Figure 56;
图59为本申请实施例提供的又一种半导体器件的结构图；Figure 59 is a structural diagram of another semiconductor device provided by an embodiment of the present application;
图60为本申请实施例提供的一种电子设备的结构图。Figure 60 is a structural diagram of an electronic device provided by an embodiment of the present application.
具体实施方式Detailed ways
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments.
以下，本申请实施例中，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。In the following, in the embodiments of the present application, the terms "first", "second", etc. are only used for convenience of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, features defined by "first," "second," etc. may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise stated, "plurality" means two or more.
本申请实施例中，“上”、“下”、“左”以及“右不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。In the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to the orientations schematically placed relative to the components in the drawings. It should be understood that these directional terms may be relative concepts. , they are used for relative description and clarification, which may change accordingly according to changes in the orientation of the components in the drawings.
在本申请实施例中，除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。In the embodiments of this application, unless the context requires otherwise, throughout the description and claims, the term "comprise" is interpreted as having an open and inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" and the like are intended to indicate specific features associated with the embodiment or example. , structures, materials or characteristics are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be included in any suitable manner in any one or more embodiments or examples.
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。As used herein, "about," "approximately," or "approximately" includes the stated value as well as an average within an acceptable range of deviations from the particular value, as determined by one of ordinary skill in the art. Determined taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system).
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的 两者之间的差值小于或等于其中任一者的5％。As used herein, "parallel,""perpendicular," and "equal" include the stated situation as well as situations that are approximate to the stated situation within an acceptable deviation range, where Such acceptable deviation ranges are as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (ie, the limitations of the measurement system). For example, "parallel" includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°; "perpendicular" includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°. "Equal" includes absolute equality and approximate equality, where the approximate equality may be equal within the acceptable deviation range, for example The difference between the two is less than or equal to 5% of either one.
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。It will be understood that when a layer or element is referred to as being on another layer or substrate, this can mean that the layer or element is directly on the other layer or substrate, or that the layer or element can be coupled to the other layer or substrate There is an intermediate layer in between.
本申请实施例中参照作为理想化示例性附图的剖视图和/或平面图和/或等效电路图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。Exemplary embodiments are described in the embodiments of the present application with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
在一些实施例中，如图1所示，提供了一种半导体器件的制备方法。该半导体器件的制备方法包括：In some embodiments, as shown in FIG. 1 , a method of manufacturing a semiconductor device is provided. The preparation method of the semiconductor device includes:
S1’、如图2A和图2B所示，在衬底10’上形成多条沿第一方向X延伸的第一鳍20’。衬底10’包括多个有效区AA和包围有效区AA的空白区BB，每个有效区AA上形成有多条第一鳍20’，而空白区BB上未形成第一鳍20’。其中，第一方向X平行于衬底10’。S1', as shown in Figures 2A and 2B, a plurality of first fins 20' extending along the first direction X are formed on the substrate 10'. The substrate 10' includes a plurality of active areas AA and a blank area BB surrounding the active area AA. A plurality of first fins 20' are formed on each active area AA, but no first fin 20' is formed on the blank area BB. Wherein, the first direction X is parallel to the substrate 10'.
S2’、如图3A和图3B所示，形成多条沿第二方向Y延伸的第一牺牲栅30’。第一牺牲栅30’跨设在多条第一鳍20’上。其中，第二方向Y与第一方向X相交叉，且第二方向Y平行于衬底10’。S2', as shown in Figures 3A and 3B, a plurality of first sacrificial gates 30' extending along the second direction Y are formed. The first sacrificial gate 30' is disposed across the plurality of first fins 20'. Wherein, the second direction Y intersects the first direction X, and the second direction Y is parallel to the substrate 10'.
S3’、如图4A和图4B所示，形成源极40’和漏极50’。源极40’和漏极50’位于第一鳍20’上，且分别位于第一牺牲栅30’在第一方向X上的两侧。S3', as shown in Figure 4A and Figure 4B, form the source electrode 40' and the drain electrode 50'. The source electrode 40' and the drain electrode 50' are located on the first fin 20' and respectively located on both sides of the first sacrificial gate 30' in the first direction X.
S4’、如图5所示，形成层间介质层60’，层间介质层60’覆盖第一牺牲栅30’。S4', as shown in Figure 5, an interlayer dielectric layer 60' is formed, and the interlayer dielectric layer 60' covers the first sacrificial gate 30'.
S5’、如图6所示，平坦化层间介质层60’，以暴露出所述多条第一牺牲栅30’远离衬底10’的表面。S5', as shown in Figure 6, the interlayer dielectric layer 60' is planarized to expose the surfaces of the plurality of first sacrificial gates 30' away from the substrate 10'.
示例性的，可以采用化学机械研磨工艺(chemical mechanical polishing，CMP)平坦化层间介质层60’。For example, a chemical mechanical polishing (CMP) process can be used to planarize the interlayer dielectric layer 60'.
S6’、如图7所示，将第一牺牲栅30’替换成第一栅70’。S6', as shown in Figure 7, replace the first sacrificial gate 30' with the first gate 70'.
可以理解，由于化学机械研磨工艺的刻蚀速率会受到材料和结构分布密度的影响，且在形成层间介质层前，有效区AA上设置有第一鳍20’、第一牺牲栅30’、源极40’和漏极50’等结构，空白区BB上未设置第一鳍20’、第一牺牲栅30’、源极40’和漏极50’等结构，且不同有效区AA上的第一鳍20’、第一牺牲栅30’源极40’和漏极50’的结构分布也不完全相同。因此，在平坦化层间介质层60’之后，衬底10’的有效区AA上层间介质层60’的表面的高度与衬底10’的空白区BB上层间介质层60’的表面的高度同一出现差异，不同有效区AA上的层间介质层60’的表面的高度也容易出现差异，同一有效区AA的不同位置上的层间介质层60’的表面的高度也可能会出现差异。It can be understood that the etching rate of the chemical mechanical polishing process will be affected by the distribution density of materials and structures, and before forming the interlayer dielectric layer, the first fin 20', the first sacrificial gate 30', Structures such as the source electrode 40' and the drain electrode 50', the first fin 20', the first sacrificial gate 30', the source electrode 40', the drain electrode 50' and other structures are not provided on the blank area BB, and the structures on the different active areas AA The structural distribution of the first fin 20', the first sacrificial gate 30', the source electrode 40' and the drain electrode 50' are also not exactly the same. Therefore, after planarizing the interlayer dielectric layer 60', the height of the surface of the interlayer dielectric layer 60' on the active area AA of the substrate 10' is equal to the height of the surface of the interlayer dielectric layer 60' on the blank area BB of the substrate 10'. The height of the interlayer dielectric layer 60' in different effective areas AA is also likely to be different. The height of the interlayer dielectric layer 60' in different positions of the same effective area AA may also be different. difference.
示例性的，在平坦化层间介质层之后，空白区BB上的层间介质层60’表面高度可以低于有效区AA上的层间介质层60’表面高度。对于有效区AA来说，第一牺牲栅30’分布较少区域层间介质层60’的表面高度低于第一牺牲栅30’分布较多区域 层间介质层60’的表面高度。For example, after planarizing the interlayer dielectric layer, the surface height of the interlayer dielectric layer 60' on the blank area BB may be lower than the surface height of the interlayer dielectric layer 60' on the active area AA. For the active area AA, the surface height of the interlayer dielectric layer 60' in the area where the first sacrificial gate 30' is less distributed is lower than the area where the first sacrificial gate 30' is more distributed. The surface height of the interlayer dielectric layer 60'.
而这种，在平坦化层间介质层60’后，层间介质层60’表面高低不平的现象又会对后续步骤造成不良影响。例如，在后续将第一牺牲栅30’的替换成第一栅70’后，需要进行化学机械研磨去除层间介质层60’表面上的栅极材料时，层间介质层60’表面高度的不均一，会影响到栅极材料的去除。比如，当研磨到有效区AA上的第一栅70’表面时，空白区BB表面的栅极材料未能完全去除((导致不应该电连接的第一栅70’形成电连接))，从而容易在制备完后成半导体器件后，导致该半导体器件失效。或者，直接研磨至空白区BB上的栅极材料时，有效区AA上所设置的第一栅70’已经被去除了一部分，或被全部去除掉，也会导致半导体器件失效。However, after the interlayer dielectric layer 60' is planarized, the uneven surface of the interlayer dielectric layer 60' will have a negative impact on subsequent steps. For example, after the first sacrificial gate 30' is subsequently replaced with the first gate 70', when chemical mechanical polishing is required to remove the gate material on the surface of the interlayer dielectric layer 60', the surface height of the interlayer dielectric layer 60' will Non-uniformity will affect the removal of gate material. For example, when grinding the surface of the first gate 70' on the active area AA, the gate material on the surface of the blank area BB is not completely removed ((causing the first gate 70' that should not be electrically connected to form an electrical connection)), thus It is easy to cause the semiconductor device to fail after the preparation is completed and the semiconductor device is formed. Alternatively, when grinding directly to the gate material on the blank area BB, the first gate 70' provided on the active area AA has been partially or completely removed, which will also cause the semiconductor device to fail.
基于此，在另一些实施例中，如图8所示，还提供了另一种半导体器件的制备方法，该半导体器件的制备方法包括，在衬底10”上形成电路结构101和虚设结构102，其中衬底10”包括多个有效区AA和包围有效区AA设置的空白区BB。每个有效区AA上形成有一个电路结构，空白区BB上形成有多个虚设结构102。Based on this, in other embodiments, as shown in FIG. 8 , another method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes forming a circuit structure 101 and a dummy structure 102 on a substrate 10″. , where the substrate 10″ includes a plurality of active areas AA and a blank area BB arranged surrounding the active areas AA. A circuit structure is formed on each active area AA, and a plurality of dummy structures 102 are formed on the blank area BB.
其中，电路结构101包括晶体管，晶体管包括第一鳍20”、第一牺牲栅30”、源极和漏极(未示出)。示例性的，晶体管可以为例如鳍式场效应晶体管(finfield-effect-transistor，FinFET)。Wherein, the circuit structure 101 includes a transistor, and the transistor includes a first fin 20", a first sacrificial gate 30", a source and a drain (not shown). For example, the transistor may be a fin field-effect transistor (FinFET).
虚设结构102与电路结构101的结构类似，也包括晶体管，晶体管中包括第二鳍，第二牺牲栅、源极和漏极。其中，第二鳍可以和第一鳍的材料相同，且与第一鳍间隔设置；第二牺牲栅可以与第一牺牲栅的材料相同，且与第二牺牲栅间隔设置。但虚设结构102不具有实际的电学功能。The dummy structure 102 has a similar structure to the circuit structure 101 and also includes a transistor. The transistor includes a second fin, a second sacrificial gate, a source and a drain. The second fin may be made of the same material as the first fin and spaced apart from the first fin; the second sacrificial gate may be made of the same material as the first sacrificial gate and spaced apart from the second sacrificial gate. However, the dummy structure 102 has no actual electrical function.
示例性的，电路结构远离衬底的表面可以与虚设结构远离衬底的表面平齐。For example, the surface of the circuit structure away from the substrate may be flush with the surface of the dummy structure away from the substrate.
由于虚设结构102与电路结构101的材料相同，结构相似，在后续进行平坦化层间介质层时，从而能够有效的缓解因材料不同或结构分布不均匀导致的层间介质层表面高低不平的问题。Since the dummy structure 102 and the circuit structure 101 are made of the same material and have similar structures, the uneven surface of the interlayer dielectric layer caused by different materials or uneven structural distribution can be effectively alleviated during subsequent planarization of the interlayer dielectric layer. .
然而，由于虚设结构102的尺寸是固定的，因此，虚设结构102的设置位置受到限制。当有效区AA之间的间隙区域的尺寸比最小的虚设结构102的尺寸还要小时，该间隙区域就无法对应设置虚设结构102。这样一来，这个间隙区域就依旧存在上述问题。也就是说，未设置虚设结构102的区域还是会造成化学机械研磨工艺研磨速率的差异。However, since the size of the dummy structure 102 is fixed, the placement location of the dummy structure 102 is limited. When the size of the gap area between the active areas AA is smaller than the size of the smallest dummy structure 102, the dummy structure 102 cannot be provided correspondingly in the gap area. In this way, the above-mentioned problems still exist in this gap area. That is to say, the area where the dummy structure 102 is not provided will still cause a difference in the polishing rate of the chemical mechanical polishing process.
虽然，可以通过设计更小尺寸的虚设结构102，来实现在更多的间隙区域设置虚设结构102。但是，一方面，工艺难度较大，成本高。另一方面，由于虚设结构102在电路结构101制备完后制备，在制备虚设结构102时，需要在虚设结构102和电路结构101之间保留一定的间隔用于隔离(间隔至少在微米量级以上)，因此，仍有较多的区域(例如前述间隔处)依旧存在化学机械研磨工艺研磨速率差异的问题。Although the dummy structure 102 can be provided in more gap areas by designing a smaller size dummy structure 102 . However, on the one hand, the process is difficult and the cost is high. On the other hand, since the dummy structure 102 is prepared after the circuit structure 101 is prepared, when preparing the dummy structure 102, a certain distance needs to be reserved between the dummy structure 102 and the circuit structure 101 for isolation (the distance is at least on the order of microns) ), therefore, there are still many areas (such as the aforementioned intervals) where the problem of polishing rate differences in the chemical mechanical polishing process still exists.
为解决上述问题，本申请一些实施例提供了一种半导体器件的制备方法，如图9所示，包括：In order to solve the above problems, some embodiments of the present application provide a method for manufacturing a semiconductor device, as shown in Figure 9, including:
S1、如图10～图12所示，在衬底10上形成多条鳍20，鳍20沿平行于衬底10的第一方向X延伸。S1. As shown in FIGS. 10 to 12 , a plurality of fins 20 are formed on the substrate 10 , and the fins 20 extend along the first direction X parallel to the substrate 10 .
示例性的，衬底10可以包括半导体材料。例如，可以为体硅、体锗、硅锗、碳化 硅、绝缘体上硅(silicon-on-insulator，SOI)、绝缘体上锗硅(SiGe-on-insulator，SGOI)中的一种。By way of example, substrate 10 may include a semiconductor material. For example, it can be bulk silicon, bulk germanium, silicon germanium, carbide One of silicon, silicon-on-insulator (SOI), and silicon germanium-on-insulator (SiGe-on-insulator, SGOI).
示例性的，衬底10可以为晶圆，例如，硅晶圆。Exemplarily, the substrate 10 may be a wafer, such as a silicon wafer.
示例性的，如图10所示，鳍20可以均匀的铺满衬底10。For example, as shown in FIG. 10 , the fins 20 can evenly cover the substrate 10 .
在一些示例中，如图10所示，沿第一方向X，多条鳍20的长度d1相等。沿第二方向Y，多条鳍20的宽度d2相等，相邻两条鳍20的中心线O之间的距离L1相等。其中，如图10所示，中心线O沿第一方向X延伸。如图11所示，多条鳍20的顶面21到衬底10的上表面的距离h1相等。In some examples, as shown in FIG. 10 , along the first direction X, the lengths d1 of the plurality of fins 20 are equal. Along the second direction Y, the widths d2 of the plurality of fins 20 are equal, and the distance L1 between the center lines O of two adjacent fins 20 is equal. As shown in FIG. 10 , the center line O extends along the first direction X. As shown in FIG. 11 , the distance h1 from the top surface 21 of the plurality of fins 20 to the upper surface of the substrate 10 is equal.
这样设置，可以便于鳍20的制备，简化半导体器件的制备工艺，同时有利于提高形成层间介质层50前，衬底10上结构分布的均一性。This arrangement can facilitate the preparation of the fins 20, simplify the preparation process of the semiconductor device, and at the same time help improve the uniformity of the structure distribution on the substrate 10 before forming the interlayer dielectric layer 50.
本申请中对鳍20的长度d1、鳍20的宽度d2、相邻两条鳍20的中心线O之间的距离L1，以及鳍20的顶面21到衬底10的上表面的距离h1均不做限制，可以根据半导体器件的具体需求以及工艺条件进行设置。本申请中对于鳍20的数目也不做限制。图10中以形成16条鳍进行示例。In this application, the length d1 of the fin 20 , the width d2 of the fin 20 , the distance L1 between the center lines O of two adjacent fins 20 , and the distance h1 from the top surface 21 of the fin 20 to the top surface of the substrate 10 are all measured. There is no restriction and can be set according to the specific needs of the semiconductor device and process conditions. There is no limit to the number of fins 20 in this application. In Figure 10, 16 fins are formed as an example.
在一些示例中，如图13所示，S1、在衬底10上形成多条鳍20，可以包括：In some examples, as shown in Figure 13, S1, forming multiple fins 20 on the substrate 10 may include:
S11、如图14所示，提供基底10a。S11. As shown in Figure 14, a substrate 10a is provided.
S12、参阅图12，刻蚀基底10a，形成衬底10和位于衬底10上的多条鳍20。S12. Referring to FIG. 12, the substrate 10a is etched to form the substrate 10 and a plurality of fins 20 located on the substrate 10.
示例性的，可以在基底10a上形成掩膜层，基于掩膜层刻蚀基底，形成衬底10和位于衬底10上的多条鳍20。For example, a mask layer may be formed on the substrate 10a, and the substrate may be etched based on the mask layer to form the substrate 10 and the plurality of fins 20 located on the substrate 10.
可以理解，本申请中在衬底10上形成多条鳍20的方式并不仅限于此。It can be understood that the method of forming the plurality of fins 20 on the substrate 10 in this application is not limited to this.
S2、如图15～图17所示，形成位于第一区域S1的多条第一牺牲栅30和位于第二区域S2的多条第二牺牲栅40，第一牺牲栅30和第二牺牲栅40沿平行于衬底10的第二方向Y延伸，第一方向X和第二方向Y相交叉。多条第一牺牲栅30和多条第二牺牲栅40跨设在多条鳍20上，且第二区域S2位于第一区域S1周围。S2. As shown in Figures 15 to 17, a plurality of first sacrificial gates 30 located in the first region S1 and a plurality of second sacrificial gates 40 located in the second region S2 are formed. The first sacrificial gates 30 and the second sacrificial gates are formed 40 extends along a second direction Y parallel to the substrate 10 , and the first direction X and the second direction Y intersect. The plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 are disposed across the plurality of fins 20 , and the second area S2 is located around the first area S1 .
示例性的，第一牺牲栅30和第二牺牲栅40的材料相同。当第一牺牲栅30和第二牺牲栅40的材料相同时，第一牺牲栅30和第二牺牲栅40的材料例如可以包括多晶硅、非晶硅、非晶碳中的至少一种。由于多晶硅、非晶硅、非晶碳等材料易于被刻蚀、保型性良好、且易于被去除，因此，以多晶硅、非晶硅、非晶碳中的至少一种材料形成第一牺牲栅30和第二牺牲栅40时，能够使第一牺牲栅30和第二牺牲栅40的形貌良好、结构稳定，且易于被去除。For example, the first sacrificial gate 30 and the second sacrificial gate 40 are made of the same material. When the materials of the first sacrificial gate 30 and the second sacrificial gate 40 are the same, the materials of the first sacrificial gate 30 and the second sacrificial gate 40 may include, for example, at least one of polysilicon, amorphous silicon, and amorphous carbon. Since materials such as polycrystalline silicon, amorphous silicon, and amorphous carbon are easy to be etched, have good shape retention, and are easy to remove, the first sacrificial gate is formed of at least one material among polycrystalline silicon, amorphous silicon, and amorphous carbon. 30 and the second sacrificial gate 40, the first sacrificial gate 30 and the second sacrificial gate 40 can have good morphology, stable structure, and can be easily removed.
第一牺牲栅30和第二牺牲栅40的材料相同，这样进行化学机械研磨的过程中，第一牺牲栅30和第二牺牲栅40的研磨速率相同，从而有利于改善因研磨速率不同，平坦化层间介质层后，层间介质层的表面高度不均匀的问题。The first sacrificial gate 30 and the second sacrificial gate 40 are made of the same material. During the chemical mechanical polishing process, the polishing rates of the first sacrificial gate 30 and the second sacrificial gate 40 are the same, which is beneficial to improving the flatness due to different polishing rates. After the interlayer dielectric layer is melted, the surface of the interlayer dielectric layer is highly uneven.
在一些示例中，第一牺牲栅30和第二牺牲栅40可以基于同一掩膜板同时形成。In some examples, the first sacrificial gate 30 and the second sacrificial gate 40 may be formed simultaneously based on the same mask.
其中，第一方向X和第二方向Y相交叉，例如可以是第一方向X和第二方向Y相互垂直。The first direction X and the second direction Y intersect. For example, the first direction X and the second direction Y may be perpendicular to each other.
可以理解，参阅图16，多条第一牺牲栅30和多条第二牺牲栅40跨设在多条鳍20上。即，多条第一牺牲栅30覆盖鳍20的顶面21以及鳍20在第二方向Y上相对的两个侧面22。多条第二牺牲栅40同样覆盖鳍20的顶面21以及鳍20在第二方向Y上相 对的两个侧面22。It can be understood that, referring to FIG. 16 , a plurality of first sacrificial gates 30 and a plurality of second sacrificial gates 40 are disposed across the plurality of fins 20 . That is, the plurality of first sacrificial gates 30 cover the top surface 21 of the fin 20 and the two opposite side surfaces 22 of the fin 20 in the second direction Y. The plurality of second sacrificial gates 40 also cover the top surface 21 of the fin 20 and the fin 20 faces each other in the second direction Y. Two sides of the pair 22.
示例性的，如图15所示，衬底10包括第一区域S1和第二区域S2。其中，第一区域S1与上述实施例中的有效区AA相对应，第二区域S2与上述实施例中的空白区BB相对应。For example, as shown in FIG. 15 , the substrate 10 includes a first area S1 and a second area S2. The first area S1 corresponds to the effective area AA in the above embodiment, and the second area S2 corresponds to the blank area BB in the above embodiment.
其中，“第二区域S2位于第一区域S1周围”，可以是如图15所示，第二区域S2包围第一区域S1在第一方向X上相对的两侧，以及在第一区域S1在第二方向Y上相对的两侧。或者，“第二区域S2位于第一区域S1周围”，还可以是在第一区域S1位于衬底10的边缘时，第二区域S2包围第一区域S1远离边缘的周侧。Among them, "the second area S2 is located around the first area S1" can be as shown in Figure 15. The second area S2 surrounds the two opposite sides of the first area S1 in the first direction X, and the first area S1 is in Opposite sides in the second direction Y. Alternatively, "the second area S2 is located around the first area S1" may also mean that when the first area S1 is located at the edge of the substrate 10, the second area S2 surrounds the peripheral side of the first area S1 away from the edge.
可以理解，第一区域S1和第二区域S2之间不交叠。It can be understood that there is no overlap between the first area S1 and the second area S2.
在一些示例中，参阅图17，第一牺牲栅30的顶面31与第二牺牲栅40的顶面41平齐或近似平齐。也即，在垂直于衬底10的第三方向Z上，第一牺牲栅30的顶面31到衬底10的上表面的距离和第二牺牲栅40的顶面41上到衬底10的上表面的距离均为大致为h2。In some examples, referring to FIG. 17 , the top surface 31 of the first sacrificial gate 30 is flush or approximately flush with the top surface 41 of the second sacrificial gate 40 . That is, in the third direction Z perpendicular to the substrate 10 , the distance from the top surface 31 of the first sacrificial gate 30 to the upper surface of the substrate 10 and the distance from the top surface 41 of the second sacrificial gate 40 to the substrate 10 are The distance between the upper surfaces is approximately h2.
这样，在多条第一牺牲栅30的周围设置多条第二牺牲栅40，且第二牺牲栅40的顶面41和第一牺牲栅30的顶面31平齐或近似平齐，在后续平坦化层间介质层时，可以同时研磨到位于不同区域的第一牺牲栅30和第二牺牲栅40，不容易因衬底10不同区域上结构分布不均匀，导致不同区域出现研磨速率不同，研磨后半导体器件表面高度不均一的问题，从而提高了半导体器件的良率。In this way, a plurality of second sacrificial gates 40 are arranged around the plurality of first sacrificial gates 30, and the top surfaces 41 of the second sacrificial gates 40 and the top surfaces 31 of the first sacrificial gates 30 are flush or nearly flush. When planarizing the interlayer dielectric layer, the first sacrificial gate 30 and the second sacrificial gate 40 located in different areas can be polished at the same time. It is not easy for the uneven structure distribution in different areas of the substrate 10 to cause different polishing rates in different areas. The surface of the semiconductor device after grinding is highly uneven, thereby improving the yield of the semiconductor device.
在一些示例中，第一牺牲栅30的宽度d3和第二牺牲栅40的宽度d4可以相等。在另一些示例中，第一牺牲栅30的宽度d3大于第二牺牲栅40的宽度d4。在又一些示例中，第一牺牲栅30的宽度d3小于第二牺牲栅40的宽度d4。In some examples, the width d3 of the first sacrificial gate 30 and the width d4 of the second sacrificial gate 40 may be equal. In other examples, the width d3 of the first sacrificial gate 30 is greater than the width d4 of the second sacrificial gate 40 . In still other examples, the width d3 of the first sacrificial gate 30 is smaller than the width d4 of the second sacrificial gate 40 .
可以理解，多条第一牺牲栅30中可以部分第一牺牲栅30的宽度d3和第二牺牲栅40的宽度d4相等，另一部分第一牺牲栅30的宽度d3和第二牺牲栅40的宽度d4不等。It can be understood that among the plurality of first sacrificial gates 30, the width d3 of some of the first sacrificial gates 30 and the width d4 of the second sacrificial gate 40 may be equal to each other, and the width d3 of another part of the first sacrificial gates 30 may be equal to the width d4 of the second sacrificial gate 40. d4 varies.
本申请一些实施例中，对第一牺牲栅30和第二牺牲栅40的宽度不做限制，可以根据实际需求进行设计。In some embodiments of the present application, the widths of the first sacrificial gate 30 and the second sacrificial gate 40 are not limited and can be designed according to actual requirements.
示例性的，沿第一方向X，多个第一牺牲栅30的宽度d3也可以相等，多个第二牺牲栅40的宽度d4也可以相等。这样，有利于第一牺牲栅30和第二牺牲栅40的制备，简化半导体器件的制备工艺。For example, along the first direction X, the widths d3 of the plurality of first sacrificial gates 30 may also be equal, and the widths d4 of the plurality of second sacrificial gates 40 may also be equal. In this way, the preparation of the first sacrificial gate 30 and the second sacrificial gate 40 is facilitated, and the preparation process of the semiconductor device is simplified.
S3、如图18和图19所示，形成层间介质层50，层间介质层50覆盖多条第一牺牲栅30和多条第二牺牲栅40。S3. As shown in FIGS. 18 and 19 , an interlayer dielectric layer 50 is formed. The interlayer dielectric layer 50 covers the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 .
示例性的，层间介质层50的材料可以包括碳化硅、碳氧化硅、氮化硅、氧化硅和氮氧化硅中的一种或多种。For example, the material of the interlayer dielectric layer 50 may include one or more of silicon carbide, silicon oxycarbide, silicon nitride, silicon oxide, and silicon oxynitride.
层间介质层50用于将隔离下层电路结构(例如，源极和漏极)和上层电路走线。The interlayer dielectric layer 50 is used to isolate lower-level circuit structures (eg, source and drain electrodes) from upper-level circuit traces.
S4、如图20～图22所示，平坦化层间介质层50，以暴露多条第一牺牲栅30和多条第二牺牲栅40远离衬底10的表面。S4. As shown in FIGS. 20 to 22 , the interlayer dielectric layer 50 is planarized to expose the surfaces of the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 away from the substrate 10 .
示例性的，可以利用化学机械研磨工艺平坦化层间介质层50。For example, a chemical mechanical polishing process may be used to planarize the interlayer dielectric layer 50 .
可以理解，平坦化层间介质层50，暴露出多条第一牺牲栅30和多条第二牺牲栅40远离衬底10的表面，从而便于后续将第一牺牲栅30和第二牺牲栅40去除，形成 第一栅和第二栅。It can be understood that planarizing the interlayer dielectric layer 50 exposes the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 away from the surface of the substrate 10 , thereby facilitating subsequent placement of the first sacrificial gates 30 and the second sacrificial gates 40 remove, form The first gate and the second gate.
S5、如图23、图24和图25所示，形成隔离结构60，隔离结构60将鳍20分割成位于多条第一牺牲栅30下方的第一鳍201和位于多条第二牺牲栅40下方的第二鳍202，隔离结构60围绕多条第一鳍201和多条第一牺牲栅30。S5. As shown in Figures 23, 24 and 25, an isolation structure 60 is formed. The isolation structure 60 divides the fin 20 into a first fin 201 located under a plurality of first sacrificial gates 30 and a plurality of second sacrificial gates 40. Below the second fin 202 , the isolation structure 60 surrounds the plurality of first fins 201 and the plurality of first sacrificial gates 30 .
本申请一些实施例所提供的半导体器件的制备方法中，先在衬底10的第一区域S1上和第二区域S2上均设置鳍20(即，鳍20均匀的铺满衬底10)、且在第一区域S1上设置第一牺牲栅30，在第二区域S2上设置第二牺牲栅40，然后形成层间介质层50，对层间介质层50进行平坦化处理，最后形成隔离结构60将鳍20划分成第一鳍201和第二鳍202。这样，在进行平坦化处理之前，半导体器件中鳍20、第一牺牲栅30和第二牺牲栅40在衬底10上的分布较为均匀，因此在层间介质层50平坦化过程中，不容易因衬底上电路结构分布不均匀，不同区域材料不同，导致不同区域研磨速度不同，出现半导体器件的表面高度差异较大，表面高度不均匀的问题，从而有效的提高了半导体器件的良率，提高半导体器件的性能。In the manufacturing method of a semiconductor device provided by some embodiments of the present application, fins 20 are first provided on both the first region S1 and the second region S2 of the substrate 10 (that is, the fins 20 evenly cover the substrate 10), And the first sacrificial gate 30 is set on the first region S1, and the second sacrificial gate 40 is set on the second region S2, then the interlayer dielectric layer 50 is formed, the interlayer dielectric layer 50 is planarized, and finally an isolation structure is formed. 60 divides the fin 20 into a first fin 201 and a second fin 202 . In this way, before the planarization process is performed, the distribution of the fins 20 , the first sacrificial gate 30 and the second sacrificial gate 40 in the semiconductor device on the substrate 10 is relatively uniform. Therefore, during the planarization process of the interlayer dielectric layer 50 , it is not easy to Due to the uneven distribution of circuit structures on the substrate and the different materials in different areas, resulting in different grinding speeds in different areas, the problem of large differences in surface heights of semiconductor devices and uneven surface heights occurs, thus effectively improving the yield of semiconductor devices. Improve the performance of semiconductor devices.
同时，与相关技术中先制备电路结构101，再在相邻的两个电路结构101间隙中设置虚设结构102，电路结构101与虚设结构102之间的间隙较大的情况相比，本申请一些实施例所提供的半导体器件的制备方法中，在平坦化层间介质层后对鳍20、第一牺牲栅30和第二牺牲栅进行切割，得到间隔在第一鳍和第二鳍，第一牺牲栅30和第二牺牲栅40之间的隔离结构60，隔离结构60的尺寸可以更小，从而不容易对后续其他平坦化工艺产生影响，进一步提高了半导体器件的良率，提高半导体器件的性能。At the same time, compared with the situation in the related art where the circuit structure 101 is first prepared and then the dummy structure 102 is set up in the gap between two adjacent circuit structures 101. The gap between the circuit structure 101 and the dummy structure 102 is relatively large. In the preparation method of the semiconductor device provided by the embodiment, after planarizing the interlayer dielectric layer, the fin 20, the first sacrificial gate 30 and the second sacrificial gate are cut to obtain a space between the first fin and the second fin, and the first sacrificial gate. The size of the isolation structure 60 between the sacrificial gate 30 and the second sacrificial gate 40 can be smaller, so that it will not easily affect other subsequent planarization processes, further improving the yield of the semiconductor device and improving the performance of the semiconductor device. performance.
在一些实施例中，如图26所示，步骤S5、形成隔离结构60，包括：In some embodiments, as shown in Figure 26, step S5, forming the isolation structure 60 includes:
S51、如图27和图28所示，刻蚀第一预设区域S3内的第二牺牲栅40和鳍20，形成第一隔离槽601。沿第二方向Y，第一预设区域S3位于多条第一牺牲栅30的一侧，第一隔离槽601沿第一方向X延伸。S51. As shown in FIG. 27 and FIG. 28, etch the second sacrificial gate 40 and the fin 20 in the first preset area S3 to form a first isolation trench 601. Along the second direction Y, the first preset area S3 is located on one side of the plurality of first sacrificial gates 30 , and the first isolation trench 601 extends along the first direction X.
示例性的，可以利用湿法刻蚀或干法刻蚀工艺，刻蚀第一预设区域S3内的第二牺牲栅40和鳍20，形成第一隔离槽601。For example, a wet etching or dry etching process may be used to etch the second sacrificial gate 40 and the fin 20 in the first preset area S3 to form the first isolation trench 601.
S52、参阅图24和图29，在第一隔离槽601内形成第一隔离部61。S52. Referring to Figures 24 and 29, the first isolation portion 61 is formed in the first isolation groove 601.
示例性的，第一隔离部61的材料可以是氧化物或氮化物。For example, the material of the first isolation part 61 may be oxide or nitride.
示例性的，在形成第一隔离部61后，可以对半导体器件进行平坦化处理，去除位于第一隔离槽601外的第一隔离部61的材料。For example, after the first isolation portion 61 is formed, the semiconductor device can be planarized to remove the material of the first isolation portion 61 located outside the first isolation trench 601 .
S53、如图30所示，刻蚀第二预设区域S4内的层间介质层50和鳍20，形成第二隔离槽602。沿第一方向X，第二预设区域S4位于多条第一牺牲栅30的一侧，第二隔离槽602沿第二方向Y延伸。S53. As shown in FIG. 30, etch the interlayer dielectric layer 50 and the fins 20 in the second preset region S4 to form a second isolation trench 602. Along the first direction X, the second preset area S4 is located on one side of the plurality of first sacrificial gates 30 , and the second isolation trench 602 extends along the second direction Y.
示例性的，可以利用湿法刻蚀或干法刻蚀工艺，刻蚀第二预设区域S4内的层间介质层50和鳍20，形成第二隔离槽602。For example, a wet etching or dry etching process may be used to etch the interlayer dielectric layer 50 and the fins 20 in the second preset area S4 to form the second isolation trench 602.
S54、参阅图23和图25，在第二隔离槽602内形成第二隔离部62。S54. Referring to FIG. 23 and FIG. 25 , the second isolation part 62 is formed in the second isolation groove 602 .
其中，隔离结构60包括第一隔离部61和第二隔离部62。Wherein, the isolation structure 60 includes a first isolation part 61 and a second isolation part 62.
示例性的，第二隔离部62的材料可以是氧化物或氮化物。For example, the material of the second isolation part 62 may be oxide or nitride.
在一些示例中，第一隔离部61的材料可以和第二隔离部62的材料相同。In some examples, the material of the first isolation part 61 may be the same as the material of the second isolation part 62 .
示例性的，在形成第二隔离部62后，可以对半导体器件进行平坦化处理，去除位 于第二隔离槽602外的第二隔离部62的材料。For example, after the second isolation portion 62 is formed, the semiconductor device may be planarized to remove bits. The material of the second isolation part 62 outside the second isolation groove 602.
可以理解，本申请对第一隔离部61和第二隔离部62的形成顺序不做限制，示例性的，可以形成第一隔离槽601，在第一隔离槽601内形成第一隔离部61，然后形成第二隔离槽602，在第二隔离槽602内形成第二隔离部62。或者，示例性的，可以先形成第二隔离槽602，在第二隔离槽602内形成第二隔离部62，再形成第一隔离槽601，在第一隔离槽601内形成第一隔离部61。It can be understood that this application does not limit the formation order of the first isolation part 61 and the second isolation part 62. For example, the first isolation groove 601 may be formed, and the first isolation part 61 may be formed in the first isolation groove 601. Then a second isolation groove 602 is formed, and a second isolation portion 62 is formed in the second isolation groove 602 . Or, for example, the second isolation groove 602 may be formed first, the second isolation part 62 is formed in the second isolation groove 602, and then the first isolation groove 601 is formed, and the first isolation part 61 is formed in the first isolation groove 601. .
本申请一些实施例中，通过在多条第一牺牲栅30在第二方向Y上的一侧形成第一隔离槽601，在第一隔离槽601内形成第一隔离部61，从而能够较好的将在第二方向Y上相邻的多条第一牺牲栅30和多条第二牺牲栅40间隔开，进而在将第一牺牲栅30替换成第一栅，将第二牺牲栅40替换成第二栅后，较好的将在第二方向Y上相邻的第一栅和第二栅间隔开。In some embodiments of the present application, the first isolation trench 601 is formed on one side of the plurality of first sacrificial gates 30 in the second direction Y, and the first isolation portion 61 is formed in the first isolation trench 601, so that it can be better The plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 adjacent in the second direction Y are spaced apart, and then the first sacrificial gates 30 are replaced with first gates, and the second sacrificial gates 40 are replaced. After forming the second gate, it is better to separate the adjacent first gate and the second gate in the second direction Y.
同样的，通过在多条第一牺牲栅30在第一方向X上的一侧形成第二隔离槽602，在第二隔离槽602内形成第二隔离部62，从而能够较好的将在第一方向X上相邻的多条第一牺牲栅30和第二牺牲栅40间隔开，进而在将第一牺牲栅30替换成第一栅，将第二牺牲栅40替换成第二栅后，较好的将在第一方向X上相邻的第一栅和第二栅间隔开，保证第一栅的使用性能。Similarly, by forming second isolation trenches 602 on one side of the plurality of first sacrificial gates 30 in the first direction A plurality of first sacrificial gates 30 and second sacrificial gates 40 adjacent in one direction It is better to separate the first gate and the second gate adjacent in the first direction X to ensure the performance of the first gate.
在本申请一些实施例中，第一隔离槽601和第二隔离槽602分开制备，从而可以在半导体工艺节点不断减小的发展进程中，同时保证第一隔离槽601和第二隔离槽602的尺寸的准确性，避免因半导体尺寸减小，第一隔离槽601和第二隔离槽602的需求尺寸(第一方向X上的尺寸和/或第二方向Y上的尺寸)，与实际制备得到的尺寸之间相差较大的问题。In some embodiments of the present application, the first isolation trench 601 and the second isolation trench 602 are prepared separately, so that in the development process of semiconductor process nodes being continuously reduced, the first isolation trench 601 and the second isolation trench 602 can be ensured at the same time. The accuracy of the dimensions prevents the required dimensions of the first isolation trench 601 and the second isolation trench 602 (the size in the first direction There is a big difference between the sizes.
在一些实施例中，如图23所示，第一隔离部61在第二方向Y上的尺寸d5小于或等于，相邻两个鳍20的中心线O之间的距离L1的二倍。In some embodiments, as shown in FIG. 23 , the dimension d5 of the first isolation portion 61 in the second direction Y is less than or equal to twice the distance L1 between the center lines O of two adjacent fins 20 .
其中，如图23所示，鳍20的中心线O沿第一方向X延伸。As shown in FIG. 23 , the center line O of the fin 20 extends along the first direction X.
通过这样设置，第一隔离部61在第二方向Y上的尺寸d5较小，即使在后续进行其他研磨工艺过程中，因第一隔离部61与第一栅、第二栅材料不同，第一隔离部61所在的区域的研磨速率与第一栅、第二栅所在的区域的研磨速率不同，出现第一隔离部61所在的区域和第一栅、第二栅所在的区域的研磨后的高度不同的问题，半导体器件中凹陷或凸出的部分面积也较小，半导体器件也不容易失效或出现不良。With this arrangement, the size d5 of the first isolation portion 61 in the second direction Y is smaller. Even during other subsequent grinding processes, because the first isolation portion 61 is made of different materials from the first gate and the second gate, the first isolation portion 61 is made of different materials. The polishing rate of the area where the isolation part 61 is located is different from the polishing rate of the area where the first and second gates are located, and the polished height of the area where the first isolation part 61 is located and the area where the first and second gates are located appear. Different problems, the area of the recessed or protruding parts of the semiconductor device is also smaller, and the semiconductor device is not prone to failure or failure.
在一些实施例中，如图31所示，衬底10上设有至少一个第一牺牲栅组301，第一牺牲栅组301包括多条第一牺牲栅30。第二隔离部62在第一方向上X的尺寸d6小于或等于，与第二隔离部62相邻的第一牺牲栅组301中相邻两个第一牺牲栅30的中心线P之间的距离L2的二倍。In some embodiments, as shown in FIG. 31 , at least one first sacrificial gate group 301 is provided on the substrate 10 , and the first sacrificial gate group 301 includes a plurality of first sacrificial gates 30 . The size d6 of the second isolation portion 62 in the first direction twice the distance from L2.
其中，第一牺牲栅30的中心线P沿第二方向Y延伸。The center line P of the first sacrificial gate 30 extends along the second direction Y.
“衬底10上设有至少一个第一牺牲栅组301”可以是，如图23所示，衬底10上设有一个第一牺牲栅组301，还可以是，如图31所示，衬底10上设有多个第一牺牲栅组301。图21以衬底上设置有四个第一牺牲栅组301进行示例。其中，沿顺时针方向，四个第一牺牲栅组301分别为第一组3011、第二组3012、第三组3013和第四组3014。"At least one first sacrificial gate group 301 is provided on the substrate 10" may mean, as shown in FIG. 23, that the substrate 10 is provided with a first sacrificial gate group 301, or it may also mean, as shown in FIG. 31, the substrate 10 is provided with a first sacrificial gate group 301. A plurality of first sacrificial gate groups 301 are provided on the bottom 10 . FIG. 21 illustrates an example in which four first sacrificial gate groups 301 are provided on the substrate. Among them, in the clockwise direction, the four first sacrificial gate groups 301 are respectively the first group 3011, the second group 3012, the third group 3013 and the fourth group 3014.
当衬底10上设置有多个第一牺牲栅组301时，可以每个第一牺牲栅组301对应一 个第一区域S1。When multiple first sacrificial gate groups 301 are provided on the substrate 10, each first sacrificial gate group 301 may correspond to a a first area S1.
当衬底10上设有多个第一牺牲栅组301时，同一第一牺牲栅组301内的第一牺牲栅30的宽度d3可相同。不同的第一牺牲栅组301中的第一牺牲栅30的宽度d3可以相同，也可以不同。图31以不同第一牺牲栅组301内第一牺牲栅30的宽度不同的情况进行示例。When multiple first sacrificial gate groups 301 are provided on the substrate 10 , the width d3 of the first sacrificial gates 30 in the same first sacrificial gate group 301 may be the same. The width d3 of the first sacrificial gates 30 in different first sacrificial gate groups 301 may be the same or different. FIG. 31 illustrates the case where the widths of the first sacrificial gates 30 in different first sacrificial gate groups 301 are different.
不同第一牺牲栅组301可以用于构建不同的电路结构，该不同电路结构可以具有不同的性能，用于实现不同的功能。示例性的，该电路结构可以为驱动电路结构、像素电路、放大电路结构、电源管理电路结构、充电保护电路结构、控制电路结构和图像传感器电路结构。本申请实施例对此不做限定。Different first sacrificial gate groups 301 can be used to construct different circuit structures, and the different circuit structures can have different performances and be used to implement different functions. For example, the circuit structure may be a driving circuit structure, a pixel circuit, an amplifying circuit structure, a power management circuit structure, a charging protection circuit structure, a control circuit structure and an image sensor circuit structure. The embodiments of the present application do not limit this.
本申请中对不同第一牺牲栅组301内的第一牺牲栅30数目不做限制，示例性的，如图21所示，四个第一牺牲栅组301可以分别包括5条第一牺牲栅30、7条第一牺牲栅30、8条第一牺牲栅30和11条第一牺牲栅30。In this application, there is no limit to the number of first sacrificial gates 30 in different first sacrificial gate groups 301. For example, as shown in FIG. 21, four first sacrificial gate groups 301 may each include five first sacrificial gates. 30. 7 first sacrificial gates 30 , 8 first sacrificial gates 30 and 11 first sacrificial gates 30 .
本申请一些实施例中，第二隔离部62在第一方向上X的尺寸d6较小，第二隔离部62的上表面的面积也较小。因此，即使在后续进行其他研磨工艺过程中，因第二隔离部62与第一栅、第二栅材料不同，第二隔离部62所在的区域的研磨速率与第一栅、第二栅所在的区域的研磨速率不同，出现第二隔离部62所在的区域和第一栅、第二栅所在的区域的研磨后的高度不同的问题，半导体器件中凹陷或凸出的部分面积也较小，半导体器件也不容易失效或出现不良。In some embodiments of the present application, the dimension d6 of the second isolation part 62 in the first direction X is smaller, and the area of the upper surface of the second isolation part 62 is also smaller. Therefore, even in the subsequent polishing process, because the second isolation portion 62 is made of different materials from the first gate and the second gate, the polishing rate of the area where the second isolation portion 62 is located is different from that of the first gate and the second gate. The polishing rates of the regions are different, and the problem arises that the polished heights of the region where the second isolation portion 62 is located and the regions where the first gate and the second gate are located are different. The area of the recessed or protruding parts of the semiconductor device is also smaller, and the semiconductor device has a smaller area. Devices are also not prone to failure or failure.
在一些示例中，当衬底10上设有多个第一牺牲栅组301时，不同第一牺牲栅组301中相邻两个第一牺牲栅30的中心线P之间的距离L2可以不相等。In some examples, when multiple first sacrificial gate groups 301 are provided on the substrate 10 , the distance L2 between the center lines P of two adjacent first sacrificial gates 30 in different first sacrificial gate groups 301 may be different. equal.
在一些实施例中，参阅图31，当衬底10上设有多个第一牺牲栅组301时，第二隔离部62在第一方向上X的尺寸d6小于或等于，多个第一牺牲栅组301中相邻两个第一牺牲栅30的中心线P之间的距离L2中最小值的二倍。In some embodiments, referring to FIG. 31 , when multiple first sacrificial gate groups 301 are provided on the substrate 10 , the size d6 of the second isolation portion 62 in the first direction X is less than or equal to the multiple first sacrificial gate groups 301 . It is twice the minimum value of the distance L2 between the center lines P of two adjacent first sacrificial gates 30 in the gate group 301 .
通过这样设置，第二隔离部62在第一方向X上的尺寸更小，第二隔离部62的上表面的面积也更小，在后续进行其他研磨工艺后，半导体器件中可能出现的凹陷或凸出的部分面积也更小，半导体器件也更加不容易失效或出现不良。With this arrangement, the size of the second isolation portion 62 in the first direction The area of the protruding part is also smaller, and the semiconductor device is less likely to fail or be defective.
在一些实施例中，如图32所示，步骤S51、刻蚀第一预设区域S3内的第二牺牲栅40和鳍20，形成第一隔离槽601，包括：In some embodiments, as shown in FIG. 32 , step S51 , etching the second sacrificial gate 40 and the fin 20 in the first preset area S3 to form the first isolation trench 601 includes:
S511、如图33所示，在层间介质层50上形成第一掩膜层51，第一掩膜层51包括第一开口511，第一开口511沿第一方向X延伸，且暴露多条第二牺牲栅40靠近多条第一牺牲栅30的端部42。S511. As shown in FIG. 33, a first mask layer 51 is formed on the interlayer dielectric layer 50. The first mask layer 51 includes a first opening 511. The first opening 511 extends along the first direction X and exposes a plurality of strips. The second sacrificial gate 40 is close to the ends 42 of the plurality of first sacrificial gates 30 .
示例性的，第一掩膜层51可以为硬掩膜。For example, the first mask layer 51 may be a hard mask.
可以理解，第一开口511与第一预设区域S3对应。It can be understood that the first opening 511 corresponds to the first preset area S3.
示例性的，第一掩膜层51中的第一开口511，可通过在第一掩膜层51上形成光刻胶层，图案化光刻胶层，然后基于图案化后的光刻胶层，刻蚀第一掩膜层51得到。For example, the first opening 511 in the first mask layer 51 can be formed by forming a photoresist layer on the first mask layer 51, patterning the photoresist layer, and then based on the patterned photoresist layer. , obtained by etching the first mask layer 51.
S512、如图34所示，经由第一开口511，刻蚀多条第二牺牲栅40所暴露的端部42，以及端部42下方的鳍20，形成第一隔离槽601。S512. As shown in FIG. 34, the exposed end portions 42 of the plurality of second sacrificial gates 40 and the fins 20 below the end portions 42 are etched through the first openings 511 to form first isolation trenches 601.
在一些实施例中，如图35所示，在步骤S2、形成多条第一牺牲栅30和多条第二牺牲栅40之前，制备方法还包括： In some embodiments, as shown in FIG. 35 , before step S2 and forming a plurality of first sacrificial gates 30 and a plurality of second sacrificial gates 40 , the preparation method further includes:
S21、如图36和图37所示，在衬底10上形成绝缘层70，鳍20的部分嵌入绝缘层70中，其余部分凸出于绝缘层70的上表面71。S21. As shown in FIGS. 36 and 37 , an insulating layer 70 is formed on the substrate 10 . Parts of the fins 20 are embedded in the insulating layer 70 , and the remaining parts protrude from the upper surface 71 of the insulating layer 70 .
示例性的，绝缘层70的材料可以包括硅(Si)、碳(C)、氮(N)、氧(O)等元素组成的二元或多元化合物，例如可以包括碳氧氮化硅(SiCxOyNz)、碳氧化硅(SiCxOy)、氮化硅(SiNx)、氧化硅(SiOx)或氮氧化硅(SiOxNy)中的至少一种。或者，绝缘层70的材料还可以含有氢(H)、氟(F)、氯(Cl)等元素中的一种或多种。For example, the material of the insulating layer 70 may include binary or multi-component compounds composed of silicon (Si), carbon (C), nitrogen (N), oxygen (O) and other elements, such as silicon carbon oxynitride (SiC). x O y N z ), silicon oxycarbide (SiC x O y ), silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ). Alternatively, the material of the insulating layer 70 may also contain one or more elements such as hydrogen (H), fluorine (F), chlorine (Cl), and the like.
示例性的，可以先沉积绝缘材料，然后对绝缘材料进行平坦化处理，使绝缘材料远离衬底的表面和鳍的顶面平齐或近似平齐，再利用回刻工艺，通过控制回刻时间控制绝缘层70的厚度，使绝缘层70的上表面71低于鳍20的顶面21。For example, the insulating material can be deposited first, and then the insulating material can be planarized so that the surface of the insulating material away from the substrate is flush or nearly flush with the top surface of the fin, and then the engraving back process is used to control the engraving back time. The thickness of the insulating layer 70 is controlled so that the upper surface 71 of the insulating layer 70 is lower than the top surface 21 of the fin 20 .
可以理解，由于鳍20均匀的铺设在衬底10上，因此，在对绝缘材料进行平坦化处理时不同区域的研磨率大致相同，半导体器件在绝缘材料平坦化后表面不同出现高低不平的现象。It can be understood that since the fins 20 are evenly laid on the substrate 10, the polishing rates in different areas are approximately the same when the insulating material is planarized. The surface of the semiconductor device may be uneven after the insulating material is planarized.
在一些示例中，在形成绝缘层70后，形成多条第一牺牲栅30和多条第二牺牲栅40之前，还可以形成栅氧化层，栅氧化层位于鳍20与第一牺牲栅30之间，鳍20与第二牺牲栅40之间。In some examples, after forming the insulating layer 70 and before forming the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 , a gate oxide layer may be formed. The gate oxide layer is located between the fins 20 and the first sacrificial gates 30 . between the fin 20 and the second sacrificial gate 40 .
在一些实施例中，如图38所示，步骤S512、经由第一开口511，刻蚀多条第二牺牲栅40所暴露的端部42，以及端部42下方的鳍20，形成第一隔离槽601，包括：In some embodiments, as shown in FIG. 38 , step S512 is to etch the exposed end portions 42 of the plurality of second sacrificial gates 40 and the fins 20 below the end portions 42 through the first openings 511 to form a first isolation. Slot 601, including:
S5121、如图39所示，刻蚀第一开口511所暴露的多条第二牺牲栅40的端部42，暴露出端部42下方的鳍20。S5121. As shown in FIG. 39, the end portions 42 of the plurality of second sacrificial gates 40 exposed by the first openings 511 are etched to expose the fins 20 below the end portions 42.
S5122、如图34所示，刻蚀鳍20，形成位于绝缘层70中的第一凹陷603，和位于绝缘层上的第二凹陷604。S5122. As shown in FIG. 34, the fin 20 is etched to form a first recess 603 located in the insulating layer 70 and a second recess 604 located on the insulating layer.
其中，第一隔离槽601包括第一凹陷603和第二凹陷604。Wherein, the first isolation groove 601 includes a first recess 603 and a second recess 604.
在一些实施例中，如图40所示，第一隔离槽601包括沿第一方向X间隔排布的多个隔离子部605。每个隔离子部605均包括第一凹槽603和第二凹槽604。In some embodiments, as shown in FIG. 40 , the first isolation groove 601 includes a plurality of isolation sub-sections 605 spaced apart along the first direction X. Each isolation sub-section 605 includes a first groove 603 and a second groove 604.
在一些实施例中，如图41所示，步骤S53、刻蚀第二预设区域S4内的层间介质层50和鳍20，形成第二隔离槽602，包括：In some embodiments, as shown in FIG. 41 , step S53 , etching the interlayer dielectric layer 50 and the fins 20 in the second preset area S4 to form a second isolation trench 602 includes:
S531、如图42所示，在层间介质层50上形成第二掩膜层52，第二掩膜层52包括第二开口521，第二开口521沿第二方向Y延伸，且暴露第一目标牺牲栅32和第二目标牺牲栅43之间的层间介质层50。第一目标牺牲栅32和第二目标牺牲栅43为，沿第一方向X，多条第一牺牲栅30和多条第二牺牲栅40中距离最近的第一牺牲栅30和第二牺牲栅40。S531. As shown in FIG. 42, a second mask layer 52 is formed on the interlayer dielectric layer 50. The second mask layer 52 includes a second opening 521. The second opening 521 extends along the second direction Y and exposes the first The interlayer dielectric layer 50 is between the target sacrificial gate 32 and the second target sacrificial gate 43 . The first target sacrificial gate 32 and the second target sacrificial gate 43 are, along the first direction 40.
示例性的，第二掩膜层52可以为硬掩膜。For example, the second mask layer 52 may be a hard mask.
可以理解，第二开口521与第二预设区域S4对应。It can be understood that the second opening 521 corresponds to the second preset area S4.
示例性的，第二掩膜层52中的第二开口521，可以通过在第二掩膜层52上形成光刻胶层，图案化光刻胶层，然后基于图案化后的光刻胶层，刻蚀第二掩膜层52得到。For example, the second opening 521 in the second mask layer 52 can be formed by forming a photoresist layer on the second mask layer 52, patterning the photoresist layer, and then based on the patterned photoresist layer. , obtained by etching the second mask layer 52 .
S532、如图43所示，经由第二开口521，刻蚀所暴露的层间介质层50，以及层间介质层50下方的鳍20，形成第二隔离槽602。S532. As shown in FIG. 43, the exposed interlayer dielectric layer 50 and the fins 20 below the interlayer dielectric layer 50 are etched through the second opening 521 to form a second isolation trench 602.
这样，在形成第二隔离槽602的过程中，刻蚀的材料较少，刻蚀工艺简单，有利 于提高半导体器件的制备效率。In this way, during the process of forming the second isolation trench 602, less material is etched, and the etching process is simple, which is advantageous. To improve the production efficiency of semiconductor devices.
在一些实施例中，如图44所示，在步骤S3、形成层间介质层50之前，制备方法还包括：In some embodiments, as shown in FIG. 44 , before step S3 and forming the interlayer dielectric layer 50 , the preparation method further includes:
S31、参阅图21，形成介质层11，介质层11覆盖多条第一牺牲栅30和多条第二牺牲栅40在第一方向X上相对的两个侧面。S31. Referring to FIG. 21, a dielectric layer 11 is formed. The dielectric layer 11 covers the two opposite sides of the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 in the first direction X.
示例性的，可以在形成第一牺牲栅30和第二牺牲栅40之后，再形成介质层11。For example, the dielectric layer 11 may be formed after the first sacrificial gate 30 and the second sacrificial gate 40 are formed.
示例性的，介质层11的材料可以包括氮化硅、氧化硅、氮氧化硅、氮氧碳化硅等。For example, the material of the dielectric layer 11 may include silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride carbide, etc.
在一些示例中，介质层11可以为单层结构，在另一些示例中，介质层11可以为多层结构。In some examples, the dielectric layer 11 may be a single-layer structure, and in other examples, the dielectric layer 11 may be a multi-layer structure.
介质层11可以用于保护第一牺牲栅30和第二牺牲栅40，在后续将第一牺牲栅30替换成第一栅，将第二牺牲栅40替换成第二栅后，介质层11还可以用于保护第一栅和第二栅。The dielectric layer 11 can be used to protect the first sacrificial gate 30 and the second sacrificial gate 40. After the first sacrificial gate 30 is replaced with a first gate and the second sacrificial gate 40 is replaced with a second gate, the dielectric layer 11 will also Can be used to protect the first and second gates.
在一些示例中，介质层11可以为具有低介电常数的材料。这样，在形成第一栅和第二栅后，利用介质层11还可以降低在的第一方向X上相邻的两个第一栅之间的耦合电容，提高半导体器件中的电路结构的使用稳定性。In some examples, dielectric layer 11 may be a material with a low dielectric constant. In this way, after the first gate and the second gate are formed, the dielectric layer 11 can also be used to reduce the coupling capacitance between the two adjacent first gates in the first direction X, thereby improving the use of the circuit structure in the semiconductor device. stability.
S32、参阅图21，在鳍20上形成源极12和漏极13。沿第一方向X，源极12和漏极13分别位于第一牺牲栅30的两侧，以及第二牺牲栅40的两侧。S32. Referring to FIG. 21, the source electrode 12 and the drain electrode 13 are formed on the fin 20. Along the first direction X, the source electrode 12 and the drain electrode 13 are located on both sides of the first sacrificial gate 30 and on both sides of the second sacrificial gate 40 respectively.
示例性的，可以在形成第一牺牲栅30和第二牺牲栅40之后，形成介质层11之后，再在鳍20上形成源极12和漏极13。For example, after the first sacrificial gate 30 and the second sacrificial gate 40 are formed, and after the dielectric layer 11 is formed, the source electrode 12 and the drain electrode 13 can be formed on the fin 20 .
示例性的，可以采用外延生长工艺，在鳍20上形成源极12和漏极13。For example, an epitaxial growth process may be used to form the source electrode 12 and the drain electrode 13 on the fin 20 .
S33、形成刻蚀停止层14，刻蚀停止层14覆盖介质层11，以及源极12和漏极13。S33. Form an etching stop layer 14, which covers the dielectric layer 11, the source electrode 12 and the drain electrode 13.
示例性的，可以在鳍20上形成源极12和漏极13之后，形成层间介质层50之前，再形成刻蚀停止层14。For example, the etching stop layer 14 may be formed after the source electrode 12 and the drain electrode 13 are formed on the fin 20 and before the interlayer dielectric layer 50 is formed.
基于此，在一些实施例中，如图45所示，步骤S532、经由第二开口521，刻蚀所暴露的层间介质层50，以及层间介质层50下方的鳍20，形成第二隔离槽602，包括：Based on this, in some embodiments, as shown in FIG. 45 , step S532 is to etch the exposed interlayer dielectric layer 50 and the fins 20 below the interlayer dielectric layer 50 through the second opening 521 to form a second isolation. Slot 602, including:
S5321、如图46所示，刻蚀第二开口521所暴露的层间介质层50，暴露出层间介质层50下方的刻蚀停止层14。S5321. As shown in FIG. 46, the interlayer dielectric layer 50 exposed by the second opening 521 is etched to expose the etching stop layer 14 below the interlayer dielectric layer 50.
S5322、如图47所示，刻蚀所暴露的刻蚀停止层14，暴露出刻蚀停止层14下方的源极12或漏极13。S5322. As shown in FIG. 47, the exposed etching stop layer 14 is etched to expose the source electrode 12 or the drain electrode 13 under the etching stop layer 14.
在一些示例中，如图47所示，刻蚀所暴露的刻蚀停止层14后，暴露出的可以是源极12。或者，在另一些示例中，刻蚀所暴露的刻蚀停止层14后，暴露出的可以是漏极13。In some examples, as shown in FIG. 47 , after etching the exposed etch stop layer 14 , the source electrode 12 may be exposed. Or, in other examples, after etching the exposed etch stop layer 14 , the drain electrode 13 may be exposed.
S5323、参阅图43，刻蚀所暴露的源极12或漏极13，以及源极12或漏极13下方的鳍20，形成第二隔离槽602。S5323. Referring to FIG. 43, the exposed source electrode 12 or drain electrode 13 and the fin 20 below the source electrode 12 or drain electrode 13 are etched to form a second isolation trench 602.
在一些实施例中，如图48所示，第二开口521还暴露第一目标牺牲栅32靠近第二目标牺牲栅43的部分表面，以及第二目标牺牲栅43靠近第一目标牺牲栅32的部分表面。In some embodiments, as shown in FIG. 48 , the second opening 521 also exposes a portion of the surface of the first target sacrificial gate 32 close to the second target sacrificial gate 43 , and the second target sacrificial gate 43 close to the first target sacrificial gate 32 part of the surface.
这样，步骤S532、在经由第二开口521，刻蚀所暴露的层间介质层50，以及层间介质层50下方的鳍20，形成第二隔离槽602的过程中，还刻蚀第一目标牺牲栅32和 第二目标牺牲栅43。In this way, in step S532, during the process of etching the exposed interlayer dielectric layer 50 and the fins 20 below the interlayer dielectric layer 50 through the second opening 521 to form the second isolation trench 602, the first target is also etched. sacrificial gate 32 and Second target sacrificial gate 43.
通过这样设置，第二开口521在第一方向X上的尺寸较大，图案化第二掩膜层52的工艺较为简单。同时，第二隔离槽602在第一方向X上的尺寸也较大，形成的第二隔离部62在第一方向X上的尺寸较大，从而可以更好的隔离在第一方向X上相邻的第一牺牲栅30和第二牺牲栅40，从而更好的隔离在第一方向X上相邻的第一栅和第二栅。With this arrangement, the size of the second opening 521 in the first direction X is larger, and the process of patterning the second mask layer 52 is simpler. At the same time, the size of the second isolation groove 602 in the first direction X is also larger, and the formed second isolation portion 62 has a larger size in the first direction The first sacrificial gate 30 and the second sacrificial gate 40 are adjacent to each other, thereby better isolating the adjacent first gate and the second gate in the first direction X.
在一些实施例中，如图48所示，覆盖第一目标牺牲栅32靠近第二目标牺牲栅43的侧面的介质层11为第一目标介质层111，覆盖第一目标介质层111的刻蚀停止层14为第一目标刻蚀停止层141，覆盖第二目标牺牲栅43靠近第一目标牺牲栅32的侧面的介质层11为第二目标介质层112，覆盖第二目标介质层112的刻蚀停止层14为第二目标刻蚀停止层142。In some embodiments, as shown in FIG. 48 , the dielectric layer 11 covering the side of the first target sacrificial gate 32 close to the second target sacrificial gate 43 is the first target dielectric layer 111 , covering the etching of the first target dielectric layer 111 The stop layer 14 is the first target etching stop layer 141, the dielectric layer 11 covering the side of the second target sacrificial gate 43 close to the first target sacrificial gate 32 is the second target dielectric layer 112, and the etching area covering the second target dielectric layer 112 is The etch stop layer 14 is the second target etch stop layer 142 .
第二开口521还暴露第一目标介质层111、第一目标刻蚀停止层141、第二目标介质层112和第二目标刻蚀停止层142远离衬底10的端面。The second opening 521 also exposes the end surfaces of the first target dielectric layer 111 , the first target etching stop layer 141 , the second target dielectric layer 112 and the second target etching stop layer 142 away from the substrate 10 .
基于此，在一些实施例中，如图49所示，步骤S53、刻蚀第二预设区域S4内的层间介质层50和鳍20，形成第二隔离槽602，包括：Based on this, in some embodiments, as shown in FIG. 49 , step S53 , etching the interlayer dielectric layer 50 and the fins 20 in the second preset area S4 to form a second isolation trench 602 includes:
S533、如图50所示，经由第二开口521，同步刻蚀第一目标牺牲栅32、第一目标介质层111、第一目标刻蚀停止层141、第二目标牺牲栅43、第二目标介质层112、第二目标刻蚀停止层142，以及第一目标牺牲栅32和第二目标牺牲栅43之间的层间介质层50，形成第三凹陷606。沿垂直于衬底10的方向，第三凹陷606的底面与位于第一目标牺牲栅32和第二目标牺牲栅43之间的源极12或漏极13的上表面之间具有间距L3。S533. As shown in FIG. 50, synchronously etch the first target sacrificial gate 32, the first target dielectric layer 111, the first target etching stop layer 141, the second target sacrificial gate 43, and the second target through the second opening 521. The dielectric layer 112, the second target etch stop layer 142, and the interlayer dielectric layer 50 between the first target sacrificial gate 32 and the second target sacrificial gate 43 form a third recess 606. Along the direction perpendicular to the substrate 10 , there is a distance L3 between the bottom surface of the third recess 606 and the upper surface of the source electrode 12 or the drain electrode 13 located between the first target sacrificial gate 32 and the second target sacrificial gate 43 .
S534、如图51所示，刻蚀剩余的第一目标介质层111、第一目标刻蚀停止层141、第二目标介质层112和第二目标刻蚀停止层142。S534. As shown in FIG. 51, the remaining first target dielectric layer 111, first target etching stop layer 141, second target dielectric layer 112 and second target etching stop layer 142 are etched.
S535、如图52所示，刻蚀第一目标牺牲栅32和第二目标牺牲栅43之间剩余的层间介质层50，暴露出层间介质层50下方的刻蚀停止层14。S535 , as shown in FIG. 52 , etch the remaining interlayer dielectric layer 50 between the first target sacrificial gate 32 and the second target sacrificial gate 43 to expose the etching stop layer 14 below the interlayer dielectric layer 50 .
S536、如图53所示，刻蚀剩余的第一目标牺牲栅32和第二目标牺牲栅43、暴露出的刻蚀停止层14、刻蚀停止层14下方的源极12或漏极13，以及源极12或漏极13下方的鳍20，形成第二隔离槽602。S536. As shown in FIG. 53, etch the remaining first target sacrificial gate 32 and the second target sacrificial gate 43, the exposed etching stop layer 14, and the source electrode 12 or the drain electrode 13 under the etching stop layer 14. And the fin 20 under the source electrode 12 or the drain electrode 13 forms a second isolation trench 602 .
可以理解，本申请实施例中，形成第二隔离槽602的方法并不仅限于此。It can be understood that in the embodiment of the present application, the method of forming the second isolation trench 602 is not limited to this.
在一些实施例中，参阅图15，在形成隔离结构60之前，沿第二方向Y，多条第一牺牲栅30与多条第二牺牲栅40之间存在间隙d7。间隙d7小于或等于相邻两条鳍20的中心线O之间的距离L1。In some embodiments, referring to FIG. 15 , before the isolation structure 60 is formed, gaps d7 exist between the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 along the second direction Y. The gap d7 is less than or equal to the distance L1 between the center lines O of two adjacent fins 20 .
这样，多条第一牺牲栅30与多条第二牺牲栅40之间的间隙d7，小于或等于相邻两条鳍20的中心线O之间的距离L1，从而可以使得各条鳍20上均设置有牺牲栅结构(第一牺牲栅或第二牺牲栅)，牺牲栅结构在衬底上分布更加均匀，从而有利于改善因衬底上牺牲栅结构分布不均匀，平坦化层间介质层后，半导体器件表面高低不平，半导体器件失效或者出现不良等问题。In this way, the gap d7 between the plurality of first sacrificial gates 30 and the plurality of second sacrificial gates 40 is less than or equal to the distance L1 between the center lines O of two adjacent fins 20 , so that the distance between the center lines O of two adjacent fins 20 can be reduced. Both are equipped with a sacrificial gate structure (first sacrificial gate or second sacrificial gate). The sacrificial gate structure is more evenly distributed on the substrate, which is beneficial to improving the uneven distribution of the sacrificial gate structure on the substrate and flattening the interlayer dielectric layer. Finally, the surface of the semiconductor device is uneven, and the semiconductor device fails or becomes defective.
在一些实施例中，如图54所示，制备方法还包括：In some embodiments, as shown in Figure 54, the preparation method further includes:
S6、如图55所示，将第一牺牲栅30替换成第一栅30a，将第二牺牲栅40替换成 第二栅40a。S6. As shown in Figure 55, replace the first sacrificial gate 30 with the first gate 30a, and replace the second sacrificial gate 40 with Second gate 40a.
在一些实施例中，第一栅30a可以为单层结构，此时，示例性的，第一栅30a的材料可以包括金属材料。In some embodiments, the first gate 30a may have a single-layer structure. In this case, for example, the material of the first gate 30a may include a metal material.
在另一些实施例中，第一栅30a可以为多层结构，此时，示例性的，第一栅30a可以包括金属层和高介电常数绝缘层。In other embodiments, the first gate 30a may have a multi-layer structure. In this case, for example, the first gate 30a may include a metal layer and a high dielectric constant insulating layer.
同理，在一些实施例中，第二栅40a可以为单层结构，此时，示例性的，第二栅40a的材料可以包括金属材料。Similarly, in some embodiments, the second gate 40a may have a single-layer structure. In this case, for example, the material of the second gate 40a may include a metal material.
在另一些实施例中，第二栅40a可以为多层结构，此时，示例性的，第二栅40a可以包括金属层和高介电常数绝缘层。In other embodiments, the second gate 40a may have a multi-layer structure. In this case, for example, the second gate 40a may include a metal layer and a high dielectric constant insulating layer.
如图55所示，本申请一些实施例中，提供了一种半导体器件100。该半导体器件100包括衬底10、多条第一鳍201、多条第二鳍202、多条第一栅30a、多条第二栅40a、层间介质层50和隔离结构60。其中，多条第一鳍201和多条第二鳍202，设于衬底10上，且沿平行于衬底10的第一方向X延伸。As shown in Figure 55, in some embodiments of the present application, a semiconductor device 100 is provided. The semiconductor device 100 includes a substrate 10 , a plurality of first fins 201 , a plurality of second fins 202 , a plurality of first gates 30 a , a plurality of second gates 40 a , an interlayer dielectric layer 50 and an isolation structure 60 . The plurality of first fins 201 and the plurality of second fins 202 are provided on the substrate 10 and extend along the first direction X parallel to the substrate 10 .
示例性的，第一鳍201设置在衬底10的第一区域S1上。第二鳍202设置在衬底10的第二区域S2上。Exemplarily, the first fin 201 is disposed on the first area S1 of the substrate 10 . The second fin 202 is disposed on the second area S2 of the substrate 10 .
在一些示例中，多条第一鳍201中各个第一鳍201的宽度可以相等。In some examples, the width of each of the plurality of first fins 201 may be equal.
在一些示例中，多条第二鳍202中各个第二鳍202的宽度可以相等。In some examples, the width of each second fin 202 of the plurality of second fins 202 may be equal.
可以理解，第一鳍201的宽度与上述鳍20的宽度相同。第二鳍202的宽度与上述鳍20的宽度相同。因此，在一些示例中，第一鳍201的宽度和第二鳍202的宽度可以相等。It can be understood that the width of the first fin 201 is the same as the width of the above-mentioned fin 20 . The width of the second fin 202 is the same as the width of the above-mentioned fin 20 . Therefore, in some examples, the width of first fin 201 and the width of second fin 202 may be equal.
在一些示例中，多条第一鳍201中任意相邻两条第一鳍201之间的间距可以相等。In some examples, the spacing between any two adjacent first fins 201 among the plurality of first fins 201 may be equal.
在一些示例中，多条第二鳍202中任意相邻两条第二鳍202之间的间距可以相等。In some examples, the spacing between any two adjacent second fins 202 among the plurality of second fins 202 may be equal.
这样设置，可以便于第一鳍201和第二鳍202的制作，简化半导体器件的制备工艺。This arrangement can facilitate the production of the first fin 201 and the second fin 202 and simplify the preparation process of the semiconductor device.
多条第一栅30a和多条第二栅40a，沿平行于衬底10的第二方向Y延伸，第一方向X与第二方向Y相交叉。多条第一栅30a跨设在多条第一鳍201上，多条第二栅40a跨设在多条第二鳍202上。The plurality of first gates 30a and the plurality of second gates 40a extend along the second direction Y parallel to the substrate 10, and the first direction X intersects the second direction Y. The plurality of first gates 30a are arranged across the plurality of first fins 201, and the plurality of second gates 40a are arranged across the plurality of second fins 202.
示例性的，第一栅30a设置在衬底10的第一区域S1上。第二栅40a设置在衬底10的第二区域S2上。Exemplarily, the first gate 30a is disposed on the first region S1 of the substrate 10 . The second gate 40a is provided on the second region S2 of the substrate 10.
在一些示例中，多条第二栅40a的宽度可以相等。In some examples, the widths of the plurality of second gates 40a may be equal.
在一些示例中，任意相邻的两条第二栅40a之间的间距可以相等。In some examples, the spacing between any two adjacent second gates 40a may be equal.
这样设置，可以便于第二栅40a的制备，简化半导体器件的制备工艺。This arrangement can facilitate the preparation of the second gate 40a and simplify the preparation process of the semiconductor device.
层间介质层50覆盖多条第一栅30a之间的区域和多条第二栅40a之间的区域，暴露出多条第一栅30a和多条第二栅40a远离衬底10的表面。The interlayer dielectric layer 50 covers the area between the plurality of first gates 30a and the area between the plurality of second gates 40a, exposing the surfaces of the plurality of first gates 30a and the plurality of second gates 40a away from the substrate 10.
隔离结构60，间隔多条第一鳍201和多条第二鳍202，以及间隔多条第一栅30a和多条第二栅40a，且围绕多条第一鳍201和多条第一栅30a。The isolation structure 60 is spaced between a plurality of first fins 201 and a plurality of second fins 202, and a plurality of first gates 30a and a plurality of second gates 40a, and surrounds the plurality of first fins 201 and the plurality of first gates 30a. .
其中，多条第一鳍201和多条第二鳍202材料相同且同层设置，多条第一栅30a和多条第二栅40a材料相同且同层设置。The plurality of first fins 201 and the plurality of second fins 202 are made of the same material and are arranged in the same layer. The plurality of first gates 30a and the plurality of second gates 40a are made of the same material and are arranged in the same layer.
需要说明的是，“多条第一鳍201和多条第二鳍202材料相同且同层设置，多条 第一栅30a和多条第二栅40a材料相同且同层设置”，即，第一鳍201和第二鳍202同时制备形成，均由鳍20分割得到。第一栅30a和第二栅40a同时制备形成。It should be noted that “the plurality of first fins 201 and the plurality of second fins 202 are made of the same material and are arranged on the same layer. The first gate 30a and the plurality of second gates 40a are made of the same material and are arranged in the same layer, that is, the first fin 201 and the second fin 202 are prepared and formed at the same time, and are divided by the fin 20. The first gate 30a and the second gate 40a Preparation and formation at the same time.
可以理解，本申请一些实施例所提供的半导体器由上述任一实施例所述的制备方法制备而成。因此，本申请一些实施例所提供的半导体器件所能够达到的有益效果与上述任一实施例所述的制备方法所能够达到的有益效果相同。It can be understood that the semiconductor device provided in some embodiments of the present application is prepared by the preparation method described in any of the above embodiments. Therefore, the beneficial effects that can be achieved by the semiconductor device provided by some embodiments of the present application are the same as the beneficial effects that can be achieved by the preparation method described in any of the above embodiments.
在一些实施例中，如图55所示，隔离结构60包括第一隔离部61和第二隔离部62。In some embodiments, as shown in FIG. 55 , the isolation structure 60 includes a first isolation portion 61 and a second isolation portion 62 .
第一隔离部61，沿第一方向X延伸，且沿第二方向Y，第一隔离部61位于多条第一栅30a的一侧。第二隔离部62，沿第二方向Y延伸，且沿第一方向X，第二隔离部62位于多条第一栅30a的一侧。The first isolation portion 61 extends along the first direction X, and along the second direction Y, the first isolation portion 61 is located on one side of the plurality of first gates 30a. The second isolation portion 62 extends along the second direction Y, and along the first direction X, the second isolation portion 62 is located on one side of the plurality of first gates 30a.
通过这样设置，在第一栅30a的周围均设置有隔离结构60，从而能够更好将第一栅30a与第二栅40a间隔开，保障第一栅30a正常工作。Through this arrangement, the isolation structure 60 is provided around the first gate 30a, which can better separate the first gate 30a and the second gate 40a and ensure the normal operation of the first gate 30a.
在一些实施例中如图56所示，第一隔离部61包括沿第一方向X间隔排列的多个隔离子部63，隔离子部63位于第二栅40a的延长线上，且隔离子部63在第一方向X上的宽度与第二栅40a在第一方向X上的宽度相等。In some embodiments, as shown in FIG. 56 , the first isolation portion 61 includes a plurality of isolation sub-portions 63 spaced apart along the first direction X. The isolation sub-portions 63 are located on the extension line of the second gate 40a, and the isolation sub-portions The width of 63 in the first direction X is equal to the width of the second gate 40a in the first direction X.
在一些实施例中，如图57所示，半导体器件100还包括绝缘层70。多条第一鳍201和多条第二鳍202的部分嵌入绝缘层70中，其余部分凸出于绝缘层70的上表面71。隔离子部63包括嵌入绝缘层70中的第一部分631和位于绝缘层70上的第二部分632。第一部分631在第二方向Y上的尺寸与第二鳍202在第二方向Y上的尺寸相等。In some embodiments, as shown in FIG. 57 , the semiconductor device 100 further includes an insulating layer 70 . Parts of the plurality of first fins 201 and the plurality of second fins 202 are embedded in the insulating layer 70 , and the remaining parts protrude from the upper surface 71 of the insulating layer 70 . The isolation sub-portion 63 includes a first portion 631 embedded in the insulating layer 70 and a second portion 632 located on the insulating layer 70 . The size of the first portion 631 in the second direction Y is equal to the size of the second fin 202 in the second direction Y.
在一些实施例中，如图58所示，沿第一方向X，多条第一栅30a和多条第二栅40a中距离最近的第一栅30a和第二栅40a，分别为第一目标栅31a和第二目标栅41a。半导体器件100还包括第一目标介质层111、第一目标刻蚀停止层141、第二目标介质层112和第二目标刻蚀停止层142。In some embodiments, as shown in Figure 58, along the first direction Gate 31a and second target gate 41a. The semiconductor device 100 further includes a first target dielectric layer 111, a first target etch stop layer 141, a second target dielectric layer 112, and a second target etch stop layer 142.
第一目标介质层111，覆盖第一目标栅31a靠近第二目标牺牲栅41a的侧面。第一目标刻蚀停止层141覆盖第一目标介质层111。第二目标介质层112覆盖第二目标栅41a靠近第一目标牺牲栅31a的侧面。第二目标刻蚀停止层142覆盖第二目标介质层112。其中，沿第一方向X，第二隔离部62位于第一目标刻蚀停止层141和第二目标刻蚀停止层142之间。The first target dielectric layer 111 covers the side of the first target gate 31a close to the second target sacrificial gate 41a. The first target etch stop layer 141 covers the first target dielectric layer 111 . The second target dielectric layer 112 covers the side of the second target gate 41a close to the first target sacrificial gate 31a. The second target etch stop layer 142 covers the second target dielectric layer 112 . Wherein, along the first direction X, the second isolation portion 62 is located between the first target etching stop layer 141 and the second target etching stop layer 142 .
可以理解，在步骤S5321～S5323，刻蚀层间介质层50、刻蚀停止层14、源极12或漏极13，以及源极12或漏极13下方的鳍20的过程中，难免会对覆盖第一目标牺牲栅32和第二目标牺牲栅43的刻蚀停止层14产生部分侵蚀，因此得到的半导体器件100中，第一目标刻蚀停止层141和第二目标刻蚀停止层142，相比于覆盖其他第一栅30a或第二栅40a的刻蚀停止层的厚度较薄。It can be understood that in steps S5321 to S5323, during the process of etching the interlayer dielectric layer 50, the etching stop layer 14, the source electrode 12 or the drain electrode 13, and the fins 20 under the source electrode 12 or the drain electrode 13, it is inevitable that The etching stop layer 14 covering the first target sacrificial gate 32 and the second target sacrificial gate 43 is partially eroded. Therefore, in the obtained semiconductor device 100, the first target etching stop layer 141 and the second target etching stop layer 142 are The thickness of the etching stop layer covering the other first gate 30a or the second gate 40a is thinner.
在一些实施例中，如图59所示，半导体器件100还包括第一介质层113、第二介质层114、第一刻蚀停止层143和第二刻蚀停止层144。In some embodiments, as shown in FIG. 59 , the semiconductor device 100 further includes a first dielectric layer 113 , a second dielectric layer 114 , a first etch stop layer 143 and a second etch stop layer 144 .
第一介质层113和第二介质层114，分别覆盖第二隔离部62在第一方向X上相对的两个侧面。第一刻蚀停止层143覆盖第一介质层113，第二刻蚀停止层144覆盖第二介质层114。The first dielectric layer 113 and the second dielectric layer 114 respectively cover two opposite sides of the second isolation part 62 in the first direction X. The first etching stop layer 143 covers the first dielectric layer 113 , and the second etching stop layer 144 covers the second dielectric layer 114 .
在一些实施例中，如图55所示，隔离结构60包括两个第一隔离部61和两个第二 隔离部62，沿第二方向Y，两个第一隔离部61分别位于多条第一栅30a的相对两侧。沿第一方向X，两个第二隔离部62分别位于多条第一栅30a的相对两侧。两个第一隔离部61和两个第二隔离部62相连成框形。In some embodiments, as shown in Figure 55, the isolation structure 60 includes two first isolation portions 61 and two second isolation portions 61. In the isolation portion 62, along the second direction Y, the two first isolation portions 61 are respectively located on opposite sides of the plurality of first gates 30a. Along the first direction X, the two second isolation portions 62 are respectively located on opposite sides of the plurality of first gates 30a. The two first isolation parts 61 and the two second isolation parts 62 are connected to form a frame shape.
这样，通过在多条第一栅30a在第一方向X上的两侧，和第二方向Y上的两侧均设置隔离结构60，从而更好将第一栅30a与第二栅40a隔离开，保证第一栅30a的工作性能，提高半导体器件100的使用性能。In this way, by providing isolation structures 60 on both sides of the plurality of first gates 30a in the first direction X and on both sides in the second direction Y, the first gates 30a and the second gates 40a are better isolated. , ensuring the working performance of the first gate 30a and improving the performance of the semiconductor device 100.
在一些实施例中，如图59所示，半导体器件100还包括第三介质层115、源极12、漏极13和第三刻蚀停止层145。第三介质层115，覆盖多条第一栅30a和多条第二栅40a在第一方向X上的相对的两个侧面。源极12和漏极13，位于多条第一鳍201和多条第二鳍202上，沿第一方向X，源极12和漏极13分别位于第一栅30a的两侧和第二栅40a的两侧。第三刻蚀停止层145，覆盖第三介质层115、源极12和漏极13。In some embodiments, as shown in FIG. 59 , the semiconductor device 100 further includes a third dielectric layer 115 , a source electrode 12 , a drain electrode 13 and a third etching stop layer 145 . The third dielectric layer 115 covers two opposite side surfaces of the plurality of first gates 30a and the plurality of second gates 40a in the first direction X. The source electrode 12 and the drain electrode 13 are located on the plurality of first fins 201 and the plurality of second fins 202. Along the first direction X, the source electrode 12 and the drain electrode 13 are respectively located on both sides of the first gate 30a and the second gate. 40a on both sides. The third etching stop layer 145 covers the third dielectric layer 115, the source electrode 12 and the drain electrode 13.
在一些实施例中，如图56所示，第一隔离部61在第二方向Y上的尺寸d8小于或等于，相邻两个第一鳍20的中心线M之间的距离L4的二倍。In some embodiments, as shown in FIG. 56 , the size d8 of the first isolation portion 61 in the second direction Y is less than or equal to twice the distance L4 between the center lines M of two adjacent first fins 20 .
其中，第一鳍20的中心线M沿第一方向X延伸。The centerline M of the first fin 20 extends along the first direction X.
这样，第一隔离部61在第二方向Y上的尺寸d8较小，从而在形成第一隔离部61后，第一隔离部61对后续平坦化工艺的影响较小，有利于提高把半导体器件的良率，提高半导体器件的性能。In this way, the size d8 of the first isolation portion 61 in the second direction Y is smaller, so that after the first isolation portion 61 is formed, the first isolation portion 61 has less impact on the subsequent planarization process, which is beneficial to improving the quality of the semiconductor device. yield and improve the performance of semiconductor devices.
在一些实施例中，参阅图56，衬底10上设有至少一个第一栅组301a，第一栅组301a包括多条第一栅30a。第二隔离部62在第一方向X上的尺寸d9小于或等于，与第二隔离部62相邻的第一栅组301a中相邻两个第一栅30a的中心线N之间的距离L5的二倍。In some embodiments, referring to FIG. 56, at least one first gate group 301a is provided on the substrate 10, and the first gate group 301a includes a plurality of first gates 30a. The size d9 of the second isolation part 62 in the first direction X is less than or equal to the distance L5 between the center lines N of two adjacent first gates 30a in the first gate group 301a adjacent to the second isolation part 62 twice.
其中，第一栅30a的中心线N沿第二方向Y延伸。The center line N of the first gate 30a extends along the second direction Y.
这样，第二隔离部62在第一方向X上的尺寸d9较小，从而在形成第二隔离部62后，第二隔离部62对后续平坦化工艺的影响较小，有利于提高把半导体器件的良率，提高半导体器件的性能。In this way, the size d9 of the second isolation portion 62 in the first direction yield and improve the performance of semiconductor devices.
如图60所示，本申请一些实施例还提供一种电子设备1000，该电子设备1000例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品。其中，消费性电子产品如为手机(mobile phone)、平板电脑(pad)、笔记本电脑、电子阅读器、个人计算机(personal computer，PC)、个人数字助理(personal digital assistant，PDA)、桌面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、无人机等。家居式电子产品如为智能门锁、电视、遥控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。车载式电子产品如为车载导航仪、车载DVD等。金融终端产品如为ATM机、自助办理业务的终端等。本申请实施例对上述电子设备的具体形式不做特殊限制。As shown in Figure 60, some embodiments of the present application also provide an electronic device 1000. The electronic device 1000 is, for example, a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, or a financial terminal product. Among them, consumer electronic products include mobile phones, tablets, laptops, e-readers, personal computers (PC), personal digital assistants (PDA), desktop monitors, Smart wearable products (such as smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, remote controls, refrigerators, rechargeable small household appliances (such as soymilk machines, sweeping robots), etc. Vehicle-mounted electronic products include car navigation systems, car DVDs, etc. Financial terminal products include ATM machines, self-service terminals, etc. The embodiments of the present application do not place special restrictions on the specific forms of the above-mentioned electronic devices.
上述电子设备1000可以包括半导体器件100和印刷电路板(printed circuit board，PCB)200等元件，半导体器件100与印刷电路板200电连接，以实现信号互通。The above-mentioned electronic device 1000 may include components such as a semiconductor device 100 and a printed circuit board (PCB) 200. The semiconductor device 100 and the printed circuit board 200 are electrically connected to achieve signal interoperability.
本申请一些实施例所提供的电子设备1000所能够达到的技术效果与上述任一实施例所述的半导体器件的制备方法所能够达到的技术效果相同，在此不再赘述。 The technical effects that can be achieved by the electronic device 1000 provided by some embodiments of the present application are the same as those that can be achieved by the method of manufacturing a semiconductor device described in any of the above embodiments, and will not be described again here.
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。 The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (23)

  1. 一种半导体器件的制备方法，其特征在于，所述制备方法包括：A method of manufacturing a semiconductor device, characterized in that the preparation method includes:
    在衬底上形成多条鳍，所述鳍沿平行于所述衬底的第一方向延伸；forming a plurality of fins on the substrate, the fins extending in a first direction parallel to the substrate;
    形成位于第一区域的多条第一牺牲栅和位于第二区域的多条第二牺牲栅，所述第一牺牲栅和所述第二牺牲栅沿平行于所述衬底的第二方向延伸，所述第一方向和所述第二方向相交叉；所述多条第一牺牲栅和所述多条第二牺牲栅跨设在所述多条鳍上，且所述第二区域在所述第一区域的周围；Forming a plurality of first sacrificial gates located in the first region and a plurality of second sacrificial gates located in the second region, the first sacrificial gates and the second sacrificial gates extending in a second direction parallel to the substrate , the first direction and the second direction intersect; the plurality of first sacrificial gates and the plurality of second sacrificial gates are arranged across the plurality of fins, and the second region is located in the around the first area;
    形成层间介质层，所述层间介质层覆盖所述多条第一牺牲栅和所述多条第二牺牲栅；Forming an interlayer dielectric layer covering the plurality of first sacrificial gates and the plurality of second sacrificial gates;
    平坦化所述层间介质层，以暴露所述多条第一牺牲栅和所述多条第二牺牲栅远离所述衬底的表面；Planarizing the interlayer dielectric layer to expose the surfaces of the plurality of first sacrificial gates and the plurality of second sacrificial gates away from the substrate;
    形成隔离结构，所述隔离结构将所述鳍分割成位于所述多条第一牺牲栅下方的第一鳍和位于所述多条第二牺牲栅下方的第二鳍，所述隔离结构围绕多条所述第一鳍和所述多条第一牺牲栅。An isolation structure is formed. The isolation structure divides the fin into a first fin located under the plurality of first sacrificial gates and a second fin located under the plurality of second sacrificial gates. The isolation structure surrounds the plurality of first sacrificial gates and a second fin located under the plurality of second sacrificial gates. the first fins and the plurality of first sacrificial gates.
  2. 根据权利要求1所述的制备方法，其特征在于，所述形成隔离结构，包括：The preparation method according to claim 1, wherein forming the isolation structure includes:
    刻蚀第一预设区域内的第二牺牲栅和鳍，形成第一隔离槽；沿所述第二方向，所述第一预设区域位于所述多条第一牺牲栅的一侧，所述第一隔离槽沿所述第一方向延伸；Etch the second sacrificial gate and the fin in the first preset area to form a first isolation trench; along the second direction, the first preset area is located on one side of the plurality of first sacrificial gates, so The first isolation groove extends along the first direction;
    在所述第一隔离槽内形成第一隔离部；forming a first isolation part in the first isolation groove;
    刻蚀第二预设区域内的层间介质层和鳍，形成第二隔离槽；沿所述第一方向，所述第二预设区域位于所述多条第一牺牲栅的一侧，所述第二隔离槽沿所述第二方向延伸；Etch the interlayer dielectric layer and fins in the second preset area to form a second isolation trench; along the first direction, the second preset area is located on one side of the plurality of first sacrificial gates, so The second isolation groove extends along the second direction;
    在所述第二隔离槽内形成第二隔离部；forming a second isolation portion in the second isolation groove;
    其中，所述隔离结构包括所述第一隔离部和所述第二隔离部。Wherein, the isolation structure includes the first isolation part and the second isolation part.
  3. 根据权利要求2所述的制备方法，其特征在于，所述第一隔离部在所述第二方向上的尺寸小于或等于，相邻两个鳍的中心线之间的距离的二倍；和/或，The preparation method according to claim 2, wherein the size of the first isolation part in the second direction is less than or equal to twice the distance between the center lines of two adjacent fins; and /or,
    所述衬底上设有至少一个第一牺牲栅组，所述第一牺牲栅组包括多条所述第一牺牲栅；所述第二隔离部在所述第一方向上的尺寸小于或等于，与所述第二隔离部相邻的第一牺牲栅组中相邻两个第一牺牲栅的中心线之间的距离的二倍。At least one first sacrificial gate group is provided on the substrate, and the first sacrificial gate group includes a plurality of first sacrificial gates; the size of the second isolation portion in the first direction is less than or equal to , twice the distance between the center lines of two adjacent first sacrificial gates in the first sacrificial gate group adjacent to the second isolation portion.
  4. 根据权利要求2所述的制备方法，其特征在于，所述刻蚀第一预设区域内的第二牺牲栅和鳍，形成第一隔离槽，包括：The preparation method according to claim 2, characterized in that etching the second sacrificial gate and the fin in the first preset area to form the first isolation trench includes:
    在所述层间介质层上形成第一掩膜层，所述第一掩膜层包括第一开口，所述第一开口沿所述第一方向延伸，且暴露多条所述第二牺牲栅靠近所述多条第一牺牲栅的端部；A first mask layer is formed on the interlayer dielectric layer. The first mask layer includes a first opening. The first opening extends along the first direction and exposes a plurality of second sacrificial gates. Ends close to the plurality of first sacrificial gates;
    经由所述第一开口，刻蚀多条所述第二牺牲栅所暴露的端部，以及所述端部下方的鳍，形成第一隔离槽。Through the first opening, the exposed ends of the plurality of second sacrificial gates and the fins below the ends are etched to form first isolation trenches.
  5. 根据权利要求4所述的制备方法，其特征在于，在所述形成多条第一牺牲栅和多条第二牺牲栅之前，所述制备方法还包括： The preparation method according to claim 4, characterized in that, before forming the plurality of first sacrificial gates and the plurality of second sacrificial gates, the preparation method further includes:
    在所述衬底上形成绝缘层，所述鳍的部分嵌入所述绝缘层中，其余部分凸出于所述绝缘层的上表面；An insulating layer is formed on the substrate, part of the fin is embedded in the insulating layer, and the remaining part protrudes from the upper surface of the insulating layer;
    所述经由所述第一开口，刻蚀所述多条第二牺牲栅所暴露的端部，以及所述端部下方的鳍，形成第一隔离槽，包括：etching the exposed ends of the plurality of second sacrificial gates and the fins below the ends through the first opening to form a first isolation trench, including:
    刻蚀所述第一开口所暴露的多条所述第二牺牲栅的端部，暴露出所述端部下方的鳍；Etching the ends of the plurality of second sacrificial gates exposed by the first opening to expose the fins below the ends;
    刻蚀所述鳍，形成位于所述绝缘层中的第一凹陷，和位于所述绝缘层上的第二凹陷；Etching the fin to form a first recess located in the insulating layer and a second recess located on the insulating layer;
    其中，所述第一隔离槽包括所述第一凹陷和所述第二凹陷。Wherein, the first isolation groove includes the first recess and the second recess.
  6. 根据权利要求2所述的制备方法，其特征在于，所述刻蚀第二预设区域内的层间介质层和鳍，形成第二隔离槽，包括：The preparation method according to claim 2, characterized in that etching the interlayer dielectric layer and fins in the second preset area to form a second isolation trench includes:
    在所述层间介质层上形成第二掩膜层，所述第二掩膜层包括第二开口，所述第二开口沿所述第二方向延伸，且暴露第一目标牺牲栅和第二目标牺牲栅之间的层间介质层；所述第一目标牺牲栅和所述第二目标牺牲栅为，沿所述第一方向，所述多条第一牺牲栅和所述多条第二牺牲栅中距离最近的第一牺牲栅和第二牺牲栅；A second mask layer is formed on the interlayer dielectric layer, the second mask layer includes a second opening, the second opening extends along the second direction, and exposes the first target sacrificial gate and the second an interlayer dielectric layer between target sacrificial gates; the first target sacrificial gate and the second target sacrificial gate are, along the first direction, the plurality of first sacrificial gates and the plurality of second sacrificial gates. The closest first sacrificial gate and the second sacrificial gate among the sacrificial gates;
    经由所述第二开口，刻蚀所暴露的层间介质层，以及所述层间介质层下方的鳍，形成第二隔离槽。Through the second opening, the exposed interlayer dielectric layer and the fins below the interlayer dielectric layer are etched to form a second isolation trench.
  7. 根据权利要求6所述的制备方法，其特征在于，在所述形成层间介质层之前，所述制备方法还包括：The preparation method according to claim 6, characterized in that, before forming the interlayer dielectric layer, the preparation method further includes:
    形成介质层，所述介质层覆盖所述多条第一牺牲栅和所述多条第二牺牲栅在所述第一方向上相对的两个侧面；Forming a dielectric layer, the dielectric layer covering two opposite sides of the plurality of first sacrificial gates and the plurality of second sacrificial gates in the first direction;
    在所述鳍上形成源极和漏极；沿所述第一方向，所述源极和所述漏极分别位于所述第一牺牲栅的两侧，以及所述第二牺牲栅的两侧；A source electrode and a drain electrode are formed on the fin; along the first direction, the source electrode and the drain electrode are respectively located on both sides of the first sacrificial gate and on both sides of the second sacrificial gate. ;
    形成刻蚀停止层，所述刻蚀停止层覆盖所述介质层，以及所述源极和所述漏极。An etching stop layer is formed, covering the dielectric layer, the source electrode and the drain electrode.
  8. 根据权利要求7所述的制备方法，其特征在于，所述经由所述第二开口，刻蚀所暴露的层间介质层，以及所述层间介质层下方的鳍，形成第二隔离槽，包括：The preparation method according to claim 7, wherein the exposed interlayer dielectric layer and the fins under the interlayer dielectric layer are etched through the second opening to form a second isolation trench, include:
    刻蚀所述第二开口所暴露的层间介质层，暴露出所述层间介质层下方的刻蚀停止层；Etching the interlayer dielectric layer exposed by the second opening to expose the etching stop layer below the interlayer dielectric layer;
    刻蚀所暴露的刻蚀停止层，暴露出所述刻蚀停止层下方的源极或漏极；Etching the exposed etching stop layer to expose the source or drain electrode below the etching stop layer;
    刻蚀所暴露的源极或漏极，以及所述源极或所述漏极下方的鳍，形成所述第二隔离槽。The exposed source electrode or drain electrode and the fin under the source electrode or drain electrode are etched to form the second isolation trench.
  9. 根据权利要求7所述的制备方法，其特征在于，所述第二开口还暴露所述第一目标牺牲栅靠近所述第二目标牺牲栅的部分表面，以及所述第二目标牺牲栅靠近所述第一目标牺牲栅的部分表面；The preparation method according to claim 7, wherein the second opening also exposes a portion of the surface of the first target sacrificial gate close to the second target sacrificial gate, and the second target sacrificial gate is close to the second target sacrificial gate. a portion of the surface of the first target sacrificial gate;
    在所述经由所述第二开口，刻蚀所暴露的层间介质层，以及所述层间介质层下方的鳍，形成第二隔离槽的过程中，还刻蚀所述第一目标牺牲栅和所述第二目标牺牲栅。During the process of etching the exposed interlayer dielectric layer and the fins under the interlayer dielectric layer through the second opening to form a second isolation trench, the first target sacrificial gate is also etched. and the second target sacrificial gate.
  10. 根据权利要求9所述的制备方法，其特征在于，覆盖所述第一目标牺牲栅靠近所述第二目标牺牲栅的侧面的介质层为第一目标介质层，覆盖所述第一目标介质层的刻蚀停止层为第一目标刻蚀停止层，覆盖所述第二目标牺牲栅靠近所述第一目标牺牲 栅的侧面的介质层为第二目标介质层，覆盖所述第二目标介质层的刻蚀停止层为第二目标刻蚀停止层；The preparation method according to claim 9, wherein the dielectric layer covering the side of the first target sacrificial gate close to the second target sacrificial gate is a first target dielectric layer, and the dielectric layer covering the first target sacrificial gate The etch stop layer is the first target etch stop layer, covering the second target sacrificial gate and close to the first target sacrificial gate. The dielectric layer on the side of the gate is the second target dielectric layer, and the etching stop layer covering the second target dielectric layer is the second target etching stop layer;
    所述第二开口还暴露所述第一目标介质层、所述第一目标刻蚀停止层、所述第二目标介质层和所述第二目标刻蚀停止层远离所述衬底的端面；The second opening also exposes the end surface of the first target dielectric layer, the first target etch stop layer, the second target dielectric layer and the second target etch stop layer away from the substrate;
    所述刻蚀第二预设区域内的层间介质层和鳍，形成第二隔离槽，包括：The etching of the interlayer dielectric layer and fins in the second preset area to form a second isolation trench includes:
    经由所述第二开口，同步刻蚀所述第一目标牺牲栅、所述第一目标介质层、所述第一目标刻蚀停止层、所述第二目标牺牲栅、所述第二目标介质层、所述第二目标刻蚀停止层，以及所述第一目标牺牲栅和所述第二目标牺牲栅之间的层间介质层，形成第三凹陷；沿垂直于所述衬底的方向，所述第三凹陷的底面与位于所述第一目标牺牲栅和所述第二目标牺牲栅之间的源极或漏极的上表面之间具有间距；Through the second opening, the first target sacrificial gate, the first target dielectric layer, the first target etch stop layer, the second target sacrificial gate, and the second target dielectric are simultaneously etched. layer, the second target etch stop layer, and the interlayer dielectric layer between the first target sacrificial gate and the second target sacrificial gate to form a third depression; in a direction perpendicular to the substrate , there is a distance between the bottom surface of the third recess and the upper surface of the source or drain located between the first target sacrificial gate and the second target sacrificial gate;
    刻蚀剩余的第一目标介质层、第一目标刻蚀停止层、第二目标介质层和第二目标刻蚀停止层；Etching the remaining first target dielectric layer, first target etching stop layer, second target dielectric layer and second target etching stop layer;
    刻蚀所述第一目标牺牲栅和所述第二目标牺牲栅之间剩余的层间介质层，暴露出所述层间介质层下方的刻蚀停止层；Etching the remaining interlayer dielectric layer between the first target sacrificial gate and the second target sacrificial gate to expose the etching stop layer under the interlayer dielectric layer;
    刻蚀剩余的第一目标牺牲栅和第二目标牺牲栅、暴露出的刻蚀停止层、所述刻蚀停止层下方的源极或漏极，以及所述源极或所述漏极下方的鳍，形成第二隔离槽。Etch the remaining first target sacrificial gate and the second target sacrificial gate, the exposed etch stop layer, the source electrode or the drain electrode below the etch stop layer, and the source electrode or the drain electrode below. fins to form a second isolation groove.
  11. 根据权利要求1～10中任一项所述的制备方法，其特征在于，在形成隔离结构之前，沿所述第二方向，所述多条第一牺牲栅与所述多条第二牺牲栅之间存在间隙；The preparation method according to any one of claims 1 to 10, characterized in that, before forming the isolation structure, along the second direction, the plurality of first sacrificial gates and the plurality of second sacrificial gates are There is a gap between;
    所述间隙小于或等于相邻两条鳍的中心线之间的距离。The gap is less than or equal to the distance between the center lines of two adjacent fins.
  12. 根据权利要求1～10中任一项所述的制备方法，其特征在于，所述制备方法还包括：The preparation method according to any one of claims 1 to 10, characterized in that the preparation method further includes:
    将所述第一牺牲栅替换成第一栅，将所述第二牺牲栅替换成第二栅。The first sacrificial gate is replaced with a first gate, and the second sacrificial gate is replaced with a second gate.
  13. 一种半导体器件，其特征在于，包括：A semiconductor device, characterized by including:
    衬底；substrate;
    多条第一鳍和多条第二鳍，设于所述衬底上，且沿平行于所述衬底的第一方向延伸；A plurality of first fins and a plurality of second fins are provided on the substrate and extend along a first direction parallel to the substrate;
    多条第一栅和多条第二栅，沿平行于所述衬底的第二方向延伸，所述第一方向与所述第二方向相交叉；所述多条第一栅跨设在所述多条第一鳍上，所述多条第二栅跨设在所述多条第二鳍上；A plurality of first gates and a plurality of second gates extend along a second direction parallel to the substrate, and the first direction intersects the second direction; the plurality of first gates are provided across the On the plurality of first fins, the plurality of second grids are provided across the plurality of second fins;
    层间介质层，所述层间介质层覆盖所述多条第一栅之间的区域和所述多条第二栅之间的区域，暴露出所述多条第一栅和所述多条第二栅远离所述衬底的表面；An interlayer dielectric layer covering the area between the first gates and the second gates, exposing the first gates and the second gates. a second gate away from the surface of the substrate;
    隔离结构，间隔所述多条第一鳍和所述多条第二鳍，以及间隔所述多条第一栅和所述多条第二栅，且围绕所述多条第一鳍和所述多条第一栅；Isolation structure, spaced between the plurality of first fins and the plurality of second fins, spaced between the plurality of first gates and the plurality of second gates, and surrounding the plurality of first fins and the plurality of second gates multiple first gates;
    其中，所述多条第一鳍和所述多条第二鳍材料相同且同层设置，所述多条第一栅和所述多条第二栅材料相同且同层设置。Wherein, the plurality of first fins and the plurality of second fins are made of the same material and are arranged in the same layer, and the plurality of first gates and the plurality of second gates are made of the same material and are arranged in the same layer.
  14. 根据权利要求13所述的半导体器件，其特征在于，所述隔离结构包括：The semiconductor device according to claim 13, wherein the isolation structure includes:
    第一隔离部，沿所述第一方向延伸，且沿所述第二方向，所述第一隔离部位于所述多条第一栅的一侧；A first isolation portion extends along the first direction, and along the second direction, the first isolation portion is located on one side of the plurality of first gates;
    第二隔离部，沿所述第二方向延伸，且沿所述第一方向，所述第二隔离部位于所 述多条第一栅的一侧。The second isolation part extends along the second direction, and is located along the first direction. One side of the plurality of first gates.
  15. 根据权利要求14所述的半导体器件，其特征在于，所述第一隔离部包括沿所述第一方向间隔排列的多个隔离子部，所述隔离子部位于所述第二栅的延长线上，且所述隔离子部在所述第一方向上的宽度与所述第二栅在所述第一方向上的宽度相等。The semiconductor device according to claim 14, wherein the first isolation portion includes a plurality of isolation sub-portions spaced apart along the first direction, and the isolation sub-portions are located on an extension line of the second gate. on, and the width of the isolator portion in the first direction is equal to the width of the second gate in the first direction.
  16. 根据权利要求15所述的半导体器件，其特征在于，还包括：The semiconductor device according to claim 15, further comprising:
    绝缘层，所述多条第一鳍和所述多条第二鳍的部分嵌入所述绝缘层中，其余部分凸出于所述绝缘层的上表面；An insulating layer, parts of the plurality of first fins and the plurality of second fins are embedded in the insulating layer, and the remaining parts protrude from the upper surface of the insulating layer;
    所述隔离子部包括嵌入所述绝缘层中的第一部分和位于所述绝缘层上的第二部分；所述第一部分在所述第二方向上的尺寸与所述第二鳍在所述第二方向上的尺寸相等。The isolation sub-portion includes a first part embedded in the insulating layer and a second part located on the insulating layer; the size of the first part in the second direction is consistent with the size of the second fin in the second direction. The dimensions in both directions are equal.
  17. 根据权利要求14所述的半导体器件，其特征在于，沿所述第一方向，所述多条第一栅和所述多条第二栅中距离最近的第一栅和第二栅，分别为第一目标栅和所述第二目标栅；The semiconductor device according to claim 14, wherein along the first direction, the closest first gate and second gate among the plurality of first gates and the plurality of second gates are respectively a first target grid and the second target grid;
    所述半导体器件还包括：The semiconductor device also includes:
    覆盖所述第一目标栅靠近所述第二目标牺牲栅的侧面的第一目标介质层；a first target dielectric layer covering the side of the first target gate close to the second target sacrificial gate;
    覆盖所述第一目标介质层的第一目标刻蚀停止层；a first target etch stop layer covering the first target dielectric layer;
    覆盖所述第二目标栅靠近所述第一目标牺牲栅的侧面的第二目标介质层；a second target dielectric layer covering the side of the second target gate close to the first target sacrificial gate;
    覆盖所述第二目标介质层的第二目标刻蚀停止层；a second target etch stop layer covering the second target dielectric layer;
    其中，沿所述第一方向，所述第二隔离部位于所述第一目标刻蚀停止层和所述第二目标刻蚀停止层之间。Wherein, along the first direction, the second isolation portion is located between the first target etching stop layer and the second target etching stop layer.
  18. 根据权利要求14所述的半导体器件，其特征在于，还包括：The semiconductor device according to claim 14, further comprising:
    第一介质层和第二介质层，分别覆盖所述第二隔离部在所述第一方向上相对的两个侧面；The first dielectric layer and the second dielectric layer respectively cover two opposite sides of the second isolation part in the first direction;
    第一刻蚀停止层和第二刻蚀停止层，所述第一刻蚀停止层覆盖所述第一介质层，所述第二刻蚀停止层覆盖所述第二介质层。A first etching stop layer and a second etching stop layer, the first etching stop layer covers the first dielectric layer, and the second etching stop layer covers the second dielectric layer.
  19. 根据权利要求14所述的半导体器件，其特征在于，所述隔离结构包括两个所述第一隔离部和两个所述第二隔离部，沿所述第二方向，两个所述第一隔离部分别位于所述多条第一栅的相对两侧；沿所述第一方向，两个所述第二隔离部分别位于所述多条第一栅的相对两侧；两个所述第一隔离部和两个所述第二隔离部相连成框形。The semiconductor device according to claim 14, wherein the isolation structure includes two first isolation parts and two second isolation parts, and along the second direction, the two first isolation parts The isolation portions are respectively located on opposite sides of the plurality of first gates; along the first direction, two second isolation portions are respectively located on opposite sides of the plurality of first gates; the two second isolation portions are respectively located on opposite sides of the plurality of first gates; One isolation part and two second isolation parts are connected to form a frame shape.
  20. 根据权利要求13～19中任一项所述的半导体器件，其特征在于，还包括：The semiconductor device according to any one of claims 13 to 19, further comprising:
    第三介质层，覆盖所述多条第一栅和所述多条第二栅在所述第一方向上的相对的两个侧面；A third dielectric layer covers two opposite sides of the plurality of first gates and the plurality of second gates in the first direction;
    源极和漏极，位于所述多条第一鳍和所述多条第二鳍上；沿所述第一方向，所述源极和所述漏极分别位于所述第一栅的两侧和所述第二栅的两侧；The source electrode and the drain electrode are located on the plurality of first fins and the plurality of second fins; along the first direction, the source electrode and the drain electrode are located on both sides of the first gate respectively. and both sides of the second gate;
    第三刻蚀停止层，覆盖所述第三介质层、所述源极和所述漏极。A third etching stop layer covers the third dielectric layer, the source electrode and the drain electrode.
  21. 根据权利要求13～19中任一项所述的半导体器件，其特征在于，所述第一隔离部在所述第二方向上的尺寸小于或等于，相邻两个第一鳍的中心线之间的距离的二倍；和/或，The semiconductor device according to any one of claims 13 to 19, wherein the size of the first isolation portion in the second direction is less than or equal to the distance between the center lines of two adjacent first fins. twice the distance between; and/or,
    所述衬底上设有至少一个第一栅组，所述第一栅组包括多条所述第一栅；所述第二隔离部在所述第一方向上的尺寸小于或等于，与所述第二隔离部相邻的第一栅组中 相邻两个第一栅的中心线之间的距离的二倍。At least one first gate group is provided on the substrate, and the first gate group includes a plurality of first gates; the size of the second isolation portion in the first direction is less than or equal to the size of the first gate group. In the first gate group adjacent to the second isolation part Twice the distance between the center lines of two adjacent first grids.
  22. 根据权利要求13～19中任一项所述的半导体器件，其特征在于，所述多条第一鳍和所述多条第二鳍的宽度相等；和/或，The semiconductor device according to any one of claims 13 to 19, wherein the widths of the plurality of first fins and the plurality of second fins are equal; and/or,
    所述多条第一鳍和所述多条第二鳍中任意相邻两条鳍之间的间距相等；和/或，The spacing between any two adjacent fins among the plurality of first fins and the plurality of second fins is equal; and/or,
    所述多条第二栅的宽度相等；和/或，The widths of the plurality of second gates are equal; and/or,
    任意相邻两条所述第二栅之间的间距相等。The spacing between any two adjacent second gates is equal.
  23. 一种电子设备，其特征在于，包括印刷电路板和权利要求13～22中任一项所述的半导体器件；所述半导体器件和所述印刷电路板电连接。 An electronic device, characterized in that it includes a printed circuit board and the semiconductor device according to any one of claims 13 to 22; the semiconductor device and the printed circuit board are electrically connected.
PCT/CN2023/081450 2022-03-22 2023-03-14 Semiconductor device and preparation method therefor, and electronic device WO2023179411A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210284461.0A CN116825722A (en) 2022-03-22 2022-03-22 Semiconductor device, manufacturing method thereof and electronic equipment
CN202210284461.0 2022-03-22

Publications (1)

Publication Number Publication Date
WO2023179411A1 true WO2023179411A1 (en) 2023-09-28

Family

ID=88099822

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/081450 WO2023179411A1 (en) 2022-03-22 2023-03-14 Semiconductor device and preparation method therefor, and electronic device

Country Status (2)

Country Link
CN (1) CN116825722A (en)
WO (1) WO2023179411A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105633158A (en) * 2015-03-31 2016-06-01 中国科学院微电子研究所 Semiconductor device manufacturing method
US20200020794A1 (en) * 2018-07-12 2020-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing the same
US20200075428A1 (en) * 2018-08-30 2020-03-05 International Business Machines Corporation Fabricating tapered semiconductor devices
CN113270497A (en) * 2020-01-29 2021-08-17 台湾积体电路制造股份有限公司 Semiconductor device and method for manufacturing the same
CN113496894A (en) * 2020-04-01 2021-10-12 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105633158A (en) * 2015-03-31 2016-06-01 中国科学院微电子研究所 Semiconductor device manufacturing method
US20200020794A1 (en) * 2018-07-12 2020-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing the same
US20200075428A1 (en) * 2018-08-30 2020-03-05 International Business Machines Corporation Fabricating tapered semiconductor devices
CN113270497A (en) * 2020-01-29 2021-08-17 台湾积体电路制造股份有限公司 Semiconductor device and method for manufacturing the same
CN113496894A (en) * 2020-04-01 2021-10-12 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor structure

Also Published As

Publication number Publication date
CN116825722A (en) 2023-09-29

Similar Documents

Publication Publication Date Title
US9153489B2 (en) Microelectronic devices having conductive through via electrodes insulated by gap regions
US10916468B2 (en) Semiconductor device with buried local interconnects
TW201926473A (en) Continuous gate and fin spacer for advanced integrated circuit structure fabrication
US7723203B2 (en) Method of forming an alignment key having a capping layer and method of fabricating a semiconductor device using the same
KR102188883B1 (en) Semiconductor device and fabricating method thereof
TW202236671A (en) Integrated chip
CN110896046A (en) Shallow trench isolation structure, semiconductor device and preparation method thereof
KR20130134139A (en) Semiconductor device and method for using the same
KR20120048791A (en) Method of manufacturing a vertical type semiconductor device
TW202224199A (en) Semiconductor device with decoupling unit and method for fabricating the same
WO2023179411A1 (en) Semiconductor device and preparation method therefor, and electronic device
US20040245596A1 (en) Semiconductor device having trench isolation
US8778757B2 (en) Methods of manufacturing a DRAM device
KR20060098045A (en) Highly integrated semiconductor device and method of fabricating the same
EP4287256A1 (en) Semiconductor structure and manufacturing method therefor
KR20230122797A (en) Manufacturing method of semiconductor device
WO2023123143A1 (en) Integrated circuit and preparation method therefor, and electronic device
TWI846333B (en) Semiconductor devices
US20240276718A1 (en) Semiconductor device and method of manufacturing semiconductor device
KR20120086624A (en) Semiconductor device and method for forming the same
US11963346B2 (en) Semiconductor structure and preparation method thereof
TWI771138B (en) Method for manufacturing semiconductor structure with capacitor landing pad
US20230402365A1 (en) Capacitor and airgap structure
WO2024045870A1 (en) Semiconductor component and manufacturing method therefor, chip and electronic device
CN114141751A (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23773659

Country of ref document: EP

Kind code of ref document: A1