CN113484788A - Reference voltage source test system, reference voltage source circuit and chip - Google Patents
Reference voltage source test system, reference voltage source circuit and chip Download PDFInfo
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- CN113484788A CN113484788A CN202110796042.0A CN202110796042A CN113484788A CN 113484788 A CN113484788 A CN 113484788A CN 202110796042 A CN202110796042 A CN 202110796042A CN 113484788 A CN113484788 A CN 113484788A
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/40—Testing power supplies
Abstract
The application discloses reference voltage source's test system, reference voltage source's circuit and chip, the system includes: a controller and a chopper buffer; the chopping buffer comprises a driving buffer circuit and a chopping switch; the positive input end of the driving buffer circuit is connected with a reference voltage source, and the controller is used for sending a first control signal to control the action of the chopping switch, so that the driving buffer circuit outputs reference voltage superposed with positive offset voltage after buffering the reference voltage source; the chopper switch is also used for sending a second control signal to control the action of the chopper switch, so that the driving buffer circuit outputs the reference voltage superposed with the negative offset voltage after buffering the reference voltage source; and the controller is also used for obtaining the test voltage of the reference voltage source according to the reference voltage of the superposed positive offset voltage output by the output end of the driving buffer circuit and the reference voltage of the superposed negative offset voltage output by the output end of the driving buffer circuit. Because no complex peripheral circuit is arranged, the test time of the test machine is saved, the test efficiency of the mass production of chips is improved, and the test cost is reduced.
Description
Technical Field
The application relates to the technical field of circuit testing, in particular to a test system of a reference voltage source, a circuit of the reference voltage source and a chip.
Background
The function of the reference voltage source is to provide a reference voltage for the circuit system, and the accuracy of the reference voltage determines the accuracy of the circuit system. For example, the accuracy of the output voltage of a Low Dropout Regulator (LDO), the significance of an Analog-to-digital Converter (ADC), and the like.
The reference voltage source generally has no driving capability and cannot be directly output to the PAD from the inside, so a driving buffer circuit needs to be added to output the reference voltage provided by the reference voltage source to the PAD, but the offset voltage introduced by the driving buffer circuit to the test path is generally several mV. Therefore, in the process of testing a chip corresponding to the circuit system, even if the precision of the internal reference voltage source is high, errors are introduced into the test path, and the precise value cannot be detected.
In the prior art, a method for accurately testing the voltage of the reference voltage source is to connect two test paths, see fig. 1, which is a schematic diagram of the voltage of a test reference voltage source provided in the prior art.
To enable testing of the voltage Vref of the reference voltage source, an ideal voltage source, for example denoted Vref _ ext (not shown in the figure), is added to TP1, where Vos denotes the offset voltage on the test path. The voltage follower 100 in fig. 1 serves as a driving buffer circuit.
The first step tests the offset voltage on the test path: turning on the channel from the pad TP1 to the pad TP2, that is, both the switch SW1 and the switch SW2 are closed, and measuring the voltage value Vtst1 on TP2, the offset voltage Vos on the test path is Vtst1-Vref _ ext.
The second step tests the internal reference voltage Vref: the channel from the reference voltage source Vref to the pad TP2 is turned on, i.e., the switch SW1 is opened, the switch SW2 and the switch SW3 are both closed, and the voltage value Vtst2 at TP2 is measured, Vref is Vtst 2-Vos.
Although the voltage of the reference voltage source can be accurately tested by the above test mode, two test PADs are needed, the test path is complex, a high-precision ideal voltage source needs to be externally connected as a reference, and both an internal circuit and peripheral equipment needed by the test and the test steps are complex. Particularly in the final mass production test link, if the reference voltage source needs to be modified, the above operation needs to be performed on each chip, and the test cost is relatively high.
Disclosure of Invention
In order to solve the technical problems, the application provides a test system of a reference voltage source, a circuit of the reference voltage source and a chip, which can accurately detect the reference voltage source, reduce the complexity of peripheral equipment and reduce the cost.
The embodiment of the application provides a test system of a reference voltage source, which comprises: a controller and a chopper buffer;
the chopping buffer comprises a driving buffer circuit and a chopping switch;
the positive input end of the driving buffer circuit is connected with the reference voltage source,
the controller is used for sending a first control signal to control the chopper switch to act, so that the driving buffer circuit buffers the reference voltage source and then outputs a reference voltage superposed with a positive offset voltage; the chopper switch is also used for sending a second control signal to control the action of the chopper switch, so that the driving buffer circuit outputs a reference voltage superposed with a negative offset voltage after buffering the reference voltage source;
the controller is further configured to obtain a test voltage of the reference voltage source according to the reference voltage superimposed with the positive offset voltage and the reference voltage superimposed with the negative offset voltage, which are output by the output end of the driving buffer circuit.
Preferably, the negative input end of the driving buffer circuit is connected with the output end of the driving buffer circuit; the chopping switches comprise a first set of switches and a second set of switches;
the controller is specifically configured to send a first control signal to control the first group of switches and the second group of switches, where the first group of switches is turned on under the action of the first control signal, and the second group of switches is turned off under the action of an inverted signal of the first control signal, so that the driving buffer circuit buffers the reference voltage source and outputs a reference voltage superimposed with a positive offset voltage; the driving buffer circuit is used for buffering the reference voltage source and then outputting the reference voltage superposed with the negative offset voltage.
Preferably, the first control signal is at a high level, the second control signal is at a low level, and the first control signal and the second control signal have the same duration.
Preferably, the first control signal is at a low level, the second control signal is at a high level, and the first control signal and the second control signal have the same duration.
Preferably, the controller is specifically configured to take an average value obtained by adding the reference voltage of the superimposed positive offset voltage output by the output terminal of the driving buffer circuit and the reference voltage of the output superimposed negative offset voltage as the test voltage of the reference voltage source;
the controller is further configured to use an average value obtained by subtracting the reference voltage of the superimposed positive offset voltage output by the output end of the driving buffer circuit and the reference voltage of the output superimposed negative offset voltage as an offset voltage on the test path.
The embodiment of the present application further provides a circuit of a reference voltage source, including: a reference voltage source, a controller and a chopping buffer;
the chopping buffer comprises a driving buffer circuit and a chopping switch;
the positive input end of the driving buffer circuit is connected with the reference voltage source;
the controller is used for sending a first control signal to control the chopper switch to act, so that the driving buffer circuit buffers the reference voltage source and then outputs a reference voltage superposed with a positive offset voltage; the chopper switch is also used for sending a second control signal to control the action of the chopper switch, so that the driving buffer circuit outputs a reference voltage superposed with a negative offset voltage after buffering the reference voltage source;
the controller is further configured to obtain a test voltage of the reference voltage source according to the reference voltage superimposed with the positive offset voltage and the reference voltage superimposed with the negative offset voltage, which are output by the output end of the driving buffer circuit.
Preferably, the negative input end of the driving buffer circuit is connected with the output end of the driving buffer circuit; the chopping switches comprise a first set of switches and a second set of switches;
the controller is specifically configured to send a first control signal to control the first group of switches and the second group of switches, where the first group of switches is turned on under the action of the first control signal, and the second group of switches is turned off under the action of an inverted signal of the first control signal, so that the driving buffer circuit buffers the reference voltage source and outputs a reference voltage superimposed with a positive offset voltage; the driving buffer circuit is used for buffering the reference voltage source and then outputting the reference voltage superposed with the negative offset voltage.
Preferably, the first control signal is at a high level and the second control signal is at a low level, or the first control signal is at a low level and the second control signal is at a high level;
the first control signal and the second control signal are the same in duration.
Preferably, the controller is specifically configured to take an average value obtained by adding the reference voltage of the superimposed positive offset voltage output by the output terminal of the driving buffer circuit and the reference voltage of the output superimposed negative offset voltage as the test voltage of the reference voltage source;
the controller is further configured to use an average value obtained by subtracting the reference voltage of the superimposed positive offset voltage output by the output end of the driving buffer circuit and the reference voltage of the output superimposed negative offset voltage as an offset voltage on the test path.
The embodiment of the present application further provides a chip, including the above-described circuit; the reference voltage source in the circuit is used for providing reference voltage for other circuits in the chip.
Compared with the prior art, the method has the advantages that:
the chopping buffer in the test system of the reference voltage source provided by the embodiment of the application comprises a driving buffer circuit and a chopping switch; the positive input end of the driving buffer circuit is connected with a reference voltage source, and the negative input end of the driving buffer circuit is connected with the output end of the driving buffer circuit; the controller sends a first control signal to control the action of the chopping switch, so that the driving buffer circuit outputs reference voltage superposed with positive offset voltage after buffering the reference voltage source; sending a second control signal to control the action of a chopping switch, so that a driving buffer circuit buffers a reference voltage source and then outputs a reference voltage superposed with a negative offset voltage; the test voltage is obtained from the reference voltage of the superimposed positive offset voltage output by the output end of the driving buffer circuit and the reference voltage of the superimposed negative offset voltage output by the output end of the driving buffer circuit, for example, the average value obtained by adding the reference voltage of the superimposed positive offset voltage output by the output end of the driving buffer circuit and the reference voltage of the superimposed negative offset voltage output by the output end of the driving buffer circuit is used as the test voltage of the reference voltage source. The technical scheme provided by the embodiment of the application can ensure that the output of the driving buffer circuit is turned over by sending different control signals to the chopper switch twice in the front and back, thereby utilizing the test results twice to calculate to obtain the reference voltage of a precise reference voltage source, the technical scheme does not need to additionally increase a test pad, compared with the prior art, one test pad is omitted, an ideal voltage source is not required to be arranged, too many peripheral circuits are not required, because the technical scheme does not have a complex peripheral circuit and does not need to switch two test paths by controlling the action of the switch, the test time of a test machine is saved, because the test time of the test machine is an important factor of the calculation cost when a chip is produced and tested, because the technical scheme provided by the embodiment of the application can directly switch a first control signal and a second control signal, therefore, the test time can be saved, the test efficiency during the production of the chip can be improved, and the test cost can be reduced.
Drawings
FIG. 1 is a diagram illustrating a voltage of a test reference voltage source provided in the prior art;
FIG. 2 is a schematic diagram of a system for testing a reference voltage source according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a test system for a reference voltage source according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a chopper buffer according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a driving buffer circuit according to an embodiment of the present disclosure;
fig. 6 is a circuit diagram of a reference voltage source according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
The terms "first," "second," and the like in the following description are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the present application, unless expressly stated or limited otherwise, the term "coupled" is to be construed broadly, e.g., "coupled" may be a fixed connection, a removable connection, or an integral part; may be directly connected or indirectly connected through an intermediate. Furthermore, the term "coupled" may be a manner of making electrical connections that communicate signals. "coupled" may be a direct electrical connection or an indirect electrical connection through intervening media.
The embodiment of the application relates to a test system of a reference voltage source, which can accurately test the reference voltage of the reference voltage source, does not need too many peripheral circuits, does not need to set an ideal voltage source, and has a simple test mode.
In order to make those skilled in the art better understand the technical solution provided by the embodiments of the present application, an application scenario of the reference voltage source is described below.
The reference voltage source is a voltage source which can provide a reference voltage, for example, in many chips or circuits, the reference voltage is needed, and thus, the reference voltage source can provide the reference voltage for the chips or circuits. For example, an ADC chip, in the embodiment of the present application, the application scenario of the ADC chip is not particularly limited, and the ADC chip may be used in any scenario that requires analog-to-digital conversion. In addition, it can also be used in other scenarios, such as requiring a reference voltage source in the audio circuit.
Referring to fig. 2, the figure is a schematic diagram of a test system of a reference voltage source according to an embodiment of the present application.
The test system of the reference voltage source provided by the embodiment comprises: a controller 200 and a chopper buffer 300;
the chopper buffer 300 includes a drive buffer circuit 301 and a chopper switch 302;
in a specific implementation manner, the driving buffer circuit 301 may be implemented by a voltage follower, i.e. with a gain of 1:1, or may be implemented by an amplifier with other gains. In this embodiment, a voltage follower is taken as an example for description. The positive input end of the driving buffer circuit 301 is connected with a reference voltage source Vref, and the negative input end of the driving buffer circuit 301 is connected with the output end of the driving buffer circuit 301; namely, the output end is directly connected with the input end to realize voltage following, and the gain is 1: 1.
The controller 200 is configured to send a first control signal to control the chopper switch 302 to operate, so that the driving buffer circuit 301 buffers the reference voltage source Vref and then outputs a reference voltage superimposed with the positive offset voltage; and is further configured to send a second control signal to control the chopper switch 302 to operate, so that the driving buffer circuit 301 buffers the reference voltage source Vref and outputs the reference voltage superimposed with the negative offset voltage. The first control signal and the second control signal output by the controller 200 are opposite signals, and the purpose is to make the output signal path of the driving buffer circuit 301 to be inverted, that is, similar to the chopping technique, so that one of the voltages output by the driving buffer circuit 301 under the action of the first control signal and the second control signal includes a positive offset voltage and the other includes a negative offset voltage, and the two results are added and then divided by 2 to obtain an accurate reference voltage of the reference voltage source.
The controller 200 is further configured to use an average value obtained by subtracting the reference voltage of the superimposed positive offset voltage output by the output terminal of the driving buffer circuit and the reference voltage of the output superimposed negative offset voltage as the offset voltage on the test path.
The controller 200 is further configured to take an average value obtained by adding the positive buffered signal output from the output terminal of the driving buffer circuit 301 and the negative buffered signal output therefrom as a test voltage of the reference voltage source Vref.
In order to more clearly describe the operation principle of the test system provided by the embodiment of the present application, the following description is made with reference to a circuit schematic diagram corresponding to fig. 2.
Referring to fig. 3, the figure is a schematic diagram of a test system of a reference voltage source according to an embodiment of the present application.
As can be seen from a comparison between fig. 3 and fig. 1, the chopper buffer 300 in fig. 3 is different from the drive buffer circuit 100 in fig. 1.
It should be understood that switch SW1 in FIG. 3 is closed only when the reference voltage source Vref needs to be tested, otherwise SW1 is open, i.e., SW1 is open when Vref provides a reference voltage for the chip or other circuitry.
The control signal in fig. 3 is denoted by Chop _ sel, that is, the technical solution provided by the embodiment of the present application adds a 1-bit digital control bit signal, which is used to control the switches in the chopper buffer 300 to operate. In practical application, the digital control bit signal is a square wave signal which can be a period, namely, a 50% duty ratio, a half period high level and a half period low level; wherein, half period is used as a first control signal, and the other half period is used as a second control signal, namely, the level states of the two control signals are opposite, thereby realizing the opposite of the switch states. The duration of the first control signal is the same as the duration of the second control signal.
As will be described in detail with reference to fig. 2 and 3, the controller 200 sends a first control signal to control the chopper switch 302 to operate, so that the driving buffer circuit 301 performs forward buffering on the reference voltage source Vref and outputs the reference voltage Vt1 superimposed with the positive offset voltage Vos; and is also used for sending a second control signal to control the action of the chopper switch 302, so that the drive buffer circuit 301 outputs the reference voltage Vt2 superposed with the negative offset voltage-Vos after buffering the reference voltage source Vref.
Here, the first control signal is at a high level, and the second control signal is at a low level. Alternatively, the first control signal may be at a low level, the second control signal may be at a high level, and the first control signal and the second control signal may be continued for the same time. Vt1 and Vt2 tested by the test pad TP2 are sent to the controller 200, and the controller 200 sums Vt1 and Vt2 and divides the sum by 2, so that the reference voltage Vref of the reference voltage source without offset voltage can be accurately obtained.
In the circuit shown in fig. 3, when chop _ sel is 0, the drive buffer circuit 301 outputs the reference voltage Vt1 superimposed with the positive offset voltage Vos after forward buffering the reference voltage source Vref; when chop _ sel is equal to 1, the drive buffer circuit 301 buffers the reference voltage source Vref and outputs the reference voltage Vt2 superimposed with the negative offset voltage Vos. Therefore, in a clock period of chop _ sel being 0 and 1, the signal path is switched once, the offset voltage of the chopper buffer itself appears at the output end in a positive and negative magnitude, the voltage of the test pad TP2 obtained twice is added and divided by 2 to obtain the internal real reference voltage, and similarly, the offset voltage Vos of the chopper buffer itself can be obtained by subtracting and dividing the result obtained twice by 2.
The accurate obtaining of the offset voltage Vos is particularly important for the operation (trimming) of high-precision reference power supply trimming, because the trimming is specific to each chip, the offset voltage Vos can be very conveniently obtained by using the technical scheme provided by the embodiment, so that the offset voltage of a test path is subtracted during trimming, and the trimmed reference voltage is ensured to be a really desired result.
According to the technical scheme, the controller sends different control signals to the chopping switch twice in the front and at the back, the output of the driving buffer circuit can be turned over, so that the reference voltage of an accurate reference voltage source can be obtained by utilizing the two test results, no extra test pad is required to be added in the technical scheme, and as can be seen by comparing the figure 3 and the figure 1, one less test pad is needed, an ideal voltage source is not required to be arranged, too many peripheral circuits are not required, for example, the figure 1 comprises a plurality of switches, and the figure 1 needs to control the switching of the plurality of switches. This technical scheme need not additionally increase the test pad, compare prior art and lacked a test pad, and need not set up ideal voltage source, also need not too many peripheral hardware circuit, because this technical scheme does not have complicated peripheral hardware circuit, the action that does not need control switch switches two test access, therefore, save the test time of test board, because the chip is when the production test, the test duration of test board is the important factor of accounting cost, because the technical scheme that this application embodiment provided directly switch first control signal second control signal can, consequently, can save test time, the efficiency of software testing when can improving chip volume production can be reduced to this scheme, and the test cost is reduced.
A specific implementation of a chopper buffer is described below with reference to the accompanying drawings.
Referring to fig. 4, a schematic diagram of a chopper buffer according to an embodiment of the present application is shown.
The chopper switch in the embodiment of the present application includes three switch circuits, which are a first chopper switch circuit 302a, a second chopper switch circuit 302b, and a third chopper switch circuit 302 c. Each chopping switch circuit includes a first set of switches and a second set of switches. As shown in fig. 4, the first set of switches are switches corresponding to sel1, the second set of switches are switches corresponding to sel2, where sel2 is an inverted signal of the first control signal sel1, i.e., sel1 and sel2 are complementary, sel2 is low when sel1 is high, and sel2 is high when sel1 is low.
It should be noted that, in this embodiment of the application, the first control signal and the second control signal are two control signals with different levels output by the controller, that is, in one control period, the first half period is the first control signal, and the second half period is the second control signal, but may be output from the same pin of the controller. Whereas sel1 and sel2 in fig. 4 represent only two complementary control signals and are not equivalent to the first control signal and the second control signal. For example, the first control signal and the second control signal are both output to sel1, and sel2 is a signal obtained by inverting the signal of sel 1. That is, the first control signal output by the controller in the first half period is applied to sel1, and the second control signal output in the second half period is also applied to sel 1. And sel2 is always the opposite of sel 1.
The controller (not shown in the figure) may output the first control signal and the second control signal.
In the first half period, the controller is specifically configured to send a first control signal to control the first group of switches and the second group of switches, the first group of switches is turned on under the action of the first control signal, and the second group of switches is turned off under the action of the inverted signal of the first control signal, so that the driving buffer circuit buffers the reference voltage source and outputs the reference voltage superimposed with the positive offset voltage. For example, in the first half period, the first control signal is high, i.e., outputs a high level to sel1, and sel2 is low. For example, for the first chopper switch circuit 302a, the switch corresponding to sel1 high is closed, the switch corresponding to sel2 low is open, VINP is connected to the gate of switch transistor M1, and VINN is connected to the gate of switch transistor M2. The action is similar for the switches in the second chopping switch circuit 302b and the third chopping switch circuit 302 c.
In the second half period, the controller is further configured to send a second control signal to control the first group of switches and the second group of switches, the first group of switches is turned off under the action of the second control signal, and the second group of switches is turned on under the action of the inverted signal of the second control signal, so that the driving buffer circuit buffers the reference voltage source and outputs the reference voltage superposed with the negative offset voltage.
For example, in the second half period, the second control signal is low, that is, a low level is output to sel1, and sel2 is high. For example, for the first chopper switch circuit 302a, the switch corresponding to sel1 low is open, the switch corresponding to sel2 high is closed, VINP is connected to the gate of switch transistor M2, and VINN is connected to the gate of switch transistor M1. The action is similar for the switches in the second chopping switch circuit 302b and the third chopping switch circuit 302 c.
As can be seen from fig. 3, the positive input terminal of the chopper buffer 300 is connected to the reference voltage source Vref, the negative input terminal of the chopper buffer 300 is connected to the output terminal of the chopper buffer 300, VINP in fig. 4 is the positive input terminal of the chopper buffer, and VINN is the negative input terminal of the chopper buffer.
As can be seen from the analysis of fig. 4, under the control of the first control signal and the second control signal of the controller, the connection of the signals of the positive input terminal and the negative input terminal of the chopper buffer 300 inside the drive buffer circuit is switched, the first half cycle is the gate of the reference voltage source connection M1, and the second half cycle is the gate of the reference voltage source connection M2.
The following illustrates a testing method of the technical solution provided in the embodiments of the present application. For example, when the reference voltage of the reference voltage source is 1.1V, the control signal chop _ sel outputted by the controller is the first control signal 0 and the second control signal 1, respectively, the voltages measured on the test pad TP2 are 1.2V and 1V, respectively, the offset voltage on the test path obtained by subtracting 2 from the voltages of the two tests is 100mV, and the accurate reference voltage obtained by adding 2 from the voltages of the two tests is 1.1V.
The technical scheme provided by the embodiment of the application has a simple hardware structure, only three groups of switch circuits are added on the basis of the driving buffer circuit, the controller outputs two control signals in one period to obtain voltages corresponding to the two control signals, the reference voltage of the reference voltage source can be obtained by simply operating the voltages tested twice, the offset voltage of the driving buffer circuit can also be obtained, and the driving buffer circuit is convenient to adjust after the offset voltage is obtained, because the technical scheme does not have a complex peripheral circuit and does not need to control the action of a switch tube to switch two testing paths, the testing time of a testing machine is saved, because the testing time length of the testing machine is an important factor of the accounting cost during the production testing of a chip, because the technical scheme provided by the embodiment of the application can directly switch the first control signal and the second control signal, therefore, the test time can be saved, the test efficiency during the production of the chip can be improved, and the test cost can be reduced.
Referring to fig. 5, the figure is a schematic diagram of a driving buffer circuit according to an embodiment of the present disclosure.
As can be seen from comparing fig. 5 and fig. 4, fig. 4 has more chopping switches than fig. 5, and in the embodiment of the present application, the chopping switch includes three switch circuits, namely, a first chopping switch circuit 302a, a second chopping switch circuit 302b, and a third chopping switch circuit 302 c. The connection relationship of the other switching tubes is the same, that is, the switching tubes M1-M10 are included, and in the embodiment of the present application, the specific type of the switching tube is not limited, and for example, the switching tube may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), which is abbreviated as a MOS tube, where M1, M2, M5, M6, M9, and M10 are all NMOS tubes, and M3, M4, M7, and M8 are all PMOS tubes. The first chopper switch circuit 302a uses PMOS and NMOS as switching transistors, the second chopper circuit 302b uses PMOS as switching transistors, and the third chopper circuit 302c uses NMOS as switching transistors.
Based on the test system of the reference voltage source provided by the above embodiments, the embodiments of the present application also provide a circuit of the reference voltage source, and it should be understood that, because the reference voltage source itself has no driving capability, the reference voltage source may be used by being tied with the chopper buffer in actual application.
Referring to fig. 6, the diagram is a circuit diagram of a reference voltage source according to an embodiment of the present application.
The reference voltage source circuit provided by the embodiment is used for providing a reference voltage source for a chip or other circuits.
The circuit of the reference voltage source provided by the embodiment comprises: a reference voltage source Vref, a controller 200, and a chopper buffer 300.
The chopper buffer 300 includes a drive buffer circuit and a chopper switch;
the positive input end of the driving buffer circuit is connected with a reference voltage source, and the negative input end of the driving buffer circuit is connected with the output end of the driving buffer circuit.
The controller 200 is used for sending a first control signal to control the action of the chopping switch, so that the driving buffer circuit buffers the reference voltage source and then outputs the reference voltage superposed with the positive offset voltage; and the driving buffer circuit is also used for sending a second control signal to control the action of the chopping switch, so that the driving buffer circuit outputs the reference voltage superposed with the negative offset voltage after buffering the reference voltage source.
The controller 200 is further configured to use an average value obtained by adding the reference voltage of the superimposed positive offset voltage output by the output terminal of the driving buffer circuit and the reference voltage of the output superimposed negative offset voltage as a test voltage of the reference voltage source.
The reference voltage source's that this application embodiment provided circuit, the controller sends different control signal for two times around for the chopper switch in the chopper buffer, alright appear the upset in order to make drive buffer circuit's output, thereby can utilize two test results to calculate the reference voltage who obtains accurate reference voltage source, this technical scheme need not increase extra test pad, compare fig. 3 and fig. 1 and can see out, test pad has lacked one, and need not set up ideal voltage source, also need not too many peripheral hardware circuit, for example, include a plurality of switches in fig. 1, the switching of a plurality of switches need to be controlled in fig. 1. The technical scheme provided by the embodiment of the application has the advantages of simple hardware circuit, simple test process and low cost.
The chopping switches comprise a first set of switches and a second set of switches;
the controller is specifically used for sending a first control signal to control the first group of switches and the second group of switches, the first group of switches are conducted under the action of the first control signal, and the second group of switches are turned off under the action of an inverted signal of the first control signal, so that the driving buffer circuit buffers the reference voltage source and then outputs the reference voltage superposed with the positive offset voltage; and the driving buffer circuit is used for sending a second control signal to control the first group of switches and the second group of switches, the first group of switches are turned off under the action of the second control signal, and the second group of switches are turned on under the action of an inverted signal of the second control signal, so that the driving buffer circuit buffers the reference voltage source and then outputs the reference voltage superposed with the negative offset voltage.
The first control signal is at a high level and the second control signal is at a low level, or the first control signal is at a low level and the second control signal is at a high level; the first control signal and the second control signal are of the same duration, each accounting for 50% of the switching period.
And the controller is also used for taking the average value obtained by subtracting the reference voltage of the superposed positive offset voltage output by the output end of the driving buffer circuit and the reference voltage of the superposed negative offset voltage as the offset voltage on the test path.
Based on the circuit of a reference voltage source provided in the foregoing embodiment, the embodiment of the present application further provides a chip, which does not limit the specific type and application scenario of the chip, and may be, for example, a chip in the field of artificial intelligence, such as a sound processing chip for performing speech recognition.
The chip provided by the embodiment of the application comprises a circuit of the reference voltage source provided by the above embodiment; the test mode of the reference voltage source can refer to the above description of the test system, and is not described herein again. The reference voltage source is used to provide reference voltages for other circuits in the chip.
Because the chip that this application embodiment provided includes reference voltage source's circuit, consequently, can provide more accurate reference voltage, and then guarantee the accuracy of chip work.
It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application in any way. Although the present application has been described with reference to the preferred embodiments, it is not intended to limit the present application. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (10)
1. A system for testing a reference voltage source, comprising: a controller and a chopper buffer;
the chopping buffer comprises a driving buffer circuit and a chopping switch;
the positive input end of the driving buffer circuit is connected with the reference voltage source,
the controller is used for sending a first control signal to control the chopper switch to act, so that the driving buffer circuit buffers the reference voltage source and then outputs a reference voltage superposed with a positive offset voltage; the chopper switch is also used for sending a second control signal to control the action of the chopper switch, so that the driving buffer circuit outputs a reference voltage superposed with a negative offset voltage after buffering the reference voltage source;
the controller is further configured to obtain a test voltage of the reference voltage source according to the reference voltage superimposed with the positive offset voltage and the reference voltage superimposed with the negative offset voltage, which are output by the output end of the driving buffer circuit.
2. The test system of claim 1, wherein the negative input of the drive buffer circuit is connected to the output of the drive buffer circuit; the chopping switches comprise a first set of switches and a second set of switches;
the controller is specifically configured to send a first control signal to control the first group of switches and the second group of switches, where the first group of switches is turned on under the action of the first control signal, and the second group of switches is turned off under the action of an inverted signal of the first control signal, so that the driving buffer circuit buffers the reference voltage source and outputs a reference voltage superimposed with a positive offset voltage; the driving buffer circuit is used for buffering the reference voltage source and then outputting the reference voltage superposed with the negative offset voltage.
3. The test system of claim 2, wherein the first control signal is high and the second control signal is low, and wherein the first control signal and the second control signal are of the same duration.
4. The test system of claim 2, wherein the first control signal is low and the second control signal is high, and wherein the first control signal and the second control signal are of the same duration.
5. The test system according to any one of claims 1 to 4, wherein the controller is specifically configured to add a reference voltage of the superimposed positive offset voltage output from the output terminal of the driving buffer circuit and a reference voltage of the superimposed negative offset voltage output from the output terminal of the driving buffer circuit to obtain an average value as the test voltage of the reference voltage source;
the controller is further configured to use an average value obtained by subtracting the reference voltage of the superimposed positive offset voltage output by the output end of the driving buffer circuit and the reference voltage of the output superimposed negative offset voltage as an offset voltage on the test path.
6. A circuit for a reference voltage source, comprising: a reference voltage source, a controller and a chopping buffer;
the chopping buffer comprises a driving buffer circuit and a chopping switch;
the positive input end of the driving buffer circuit is connected with the reference voltage source;
the controller is used for sending a first control signal to control the chopper switch to act, so that the driving buffer circuit buffers the reference voltage source and then outputs a reference voltage superposed with a positive offset voltage; the chopper switch is also used for sending a second control signal to control the action of the chopper switch, so that the driving buffer circuit outputs a reference voltage superposed with a negative offset voltage after buffering the reference voltage source;
the controller is further configured to obtain a test voltage of the reference voltage source according to the reference voltage superimposed with the positive offset voltage and the reference voltage superimposed with the negative offset voltage, which are output by the output end of the driving buffer circuit.
7. The circuit of claim 6, wherein the negative input terminal of the driving buffer circuit is connected to the output terminal of the driving buffer circuit; the chopping switches comprise a first set of switches and a second set of switches;
the controller is specifically configured to send a first control signal to control the first group of switches and the second group of switches, where the first group of switches is turned on under the action of the first control signal, and the second group of switches is turned off under the action of an inverted signal of the first control signal, so that the driving buffer circuit buffers the reference voltage source and outputs a reference voltage superimposed with a positive offset voltage; the driving buffer circuit is used for buffering the reference voltage source and then outputting the reference voltage superposed with the negative offset voltage.
8. The circuit of claim 7, wherein the first control signal is high and the second control signal is low, or wherein the first control signal is low and the second control signal is high;
the first control signal and the second control signal are the same in duration.
9. The circuit according to any of claims 6 to 8, wherein the controller is specifically configured to take an average value obtained by adding the reference voltage of the superimposed positive offset voltage output from the output terminal of the driving buffer circuit and the reference voltage of the superimposed negative offset voltage output from the output terminal of the driving buffer circuit as the test voltage of the reference voltage source;
the controller is further configured to use an average value obtained by subtracting the reference voltage of the superimposed positive offset voltage output by the output end of the driving buffer circuit and the reference voltage of the output superimposed negative offset voltage as an offset voltage on the test path.
10. A chip comprising the circuit of any one of claims 6-9;
the reference voltage source in the circuit is used for providing reference voltage for other circuits in the chip.
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Inventor after: Tang Rongrong Inventor after: Luo Sai Inventor after: Wu Yanwei Inventor after: Wang Zhiguo Inventor after: Shao Zhiyong Inventor after: Liu Wei Inventor before: Tang Rongrong Inventor before: Luo Sai Inventor before: Wu Yanwei |