WO2023045969A1 - Comparator circuit and control method thereof, voltage comparison device and analog-to-digital converter - Google Patents

Abstract

A comparator circuit, which is used for comparing a first voltage with a second voltage. The comparator circuit comprises an energy storage circuit (100), an operational amplifier circuit (200), and a first switch element (S1). A first input terminal of the operational amplifier circuit (200) is used for receiving a reference voltage, and a second input terminal of the operational amplifier circuit (200) is connected to an output terminal of the operational amplifier circuit (200) via the first switch element (S1). A first terminal of the energy storage circuit (100) is used for receiving in time sharing the first voltage or the second voltage, and a second terminal of the energy storage circuit (100) is connected to a second input terminal of the operational amplifier circuit (200).

Description

Comparator circuit and its control method, voltage comparison device and analog-to-digital converter

Cross References to Related Applications

This application claims the priority of the Chinese patent application with the application number 2021111232290 and the title of the invention "comparator circuit and its control method, voltage comparison device and analog-to-digital converter" submitted to the China Patent Office on September 24, 2021. The entire contents are incorporated by reference in this application.

technical field

The present application relates to the technical field of integrated circuits, in particular to a comparator circuit and its control method, a voltage comparison device and an analog-to-digital converter.

Background technique

Comparator circuits are widely used in analog circuits, for example, in analog-to-digital converters, comparator circuits play a vital role. Among them, whether the current or voltage at the two input terminals can be accurately compared is a key technical index of the comparator circuit. However, due to insufficient design of the internal circuit of the comparator circuit, if the difference between the two compared signals is less than or equal to a certain threshold, the comparator circuit cannot accurately output the comparison result. That is, the sensitivity of the existing comparator circuit cannot meet the usage requirements.

The statements herein merely provide background information related to the present application and do not necessarily constitute exemplary techniques.

Contents of the invention

According to various embodiments of the present application, there are provided a comparator circuit and a control method thereof, a voltage comparison device and an analog-to-digital converter.

A comparator circuit for comparing a first voltage with a second voltage, the comparator voltage comprising an energy storage circuit, an operational amplifier circuit and a first switching element; wherein,

The first input terminal of the operational amplifier circuit is used to receive a reference voltage, the second input terminal of the operational amplifier circuit is connected to the output terminal of the operational amplifier circuit through the first switch element, and the energy storage circuit The first terminal is used to receive the first voltage or the second voltage in time division, and the second terminal of the energy storage circuit is connected to the second input terminal of the operational amplifier circuit.

A voltage comparison device, comprising:

Comparator circuit as above;

A controller, connected to the comparator circuit, for outputting a control signal including a first level and a second level.

An analog-to-digital converter, comprising the above-mentioned voltage comparison device, the voltage comparison device is used to generate a corresponding digital signal according to an analog signal to be converted and a preset threshold signal.

A control method for a comparator circuit, used for the above-mentioned comparator circuit, the control method comprising:

It includes first control for setting the first switching element in an on state and second control for setting the first switching element in an off state.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present application will be apparent from the description, drawings and claims.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments or exemplary technologies of the present application, the following will briefly introduce the accompanying drawings that need to be used in the descriptions of the embodiments or exemplary technologies. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present application. Those skilled in the art can also obtain the drawings of other embodiments according to these drawings without creative work.

Fig. 1 is one of the circuit diagrams when the comparator circuit of an embodiment receives the first voltage Va;

Fig. 2 is one of the circuit diagrams when the comparator circuit of an embodiment receives the second voltage Vb;

Fig. 3 is the second circuit diagram of the comparator circuit of an embodiment;

Fig. 4 is the third circuit diagram of the comparator circuit of an embodiment;

Fig. 5 is the circuit diagram 4 of the comparator circuit of an embodiment;

Fig. 6 is the fifth circuit diagram of the comparator circuit of an embodiment;

Fig. 7 is the sixth circuit diagram of the comparator circuit of an embodiment;

FIG. 8 is an equivalent circuit diagram of a comparator circuit in an embodiment in a first working mode;

FIG. 9 is an equivalent circuit diagram of a comparator circuit in an embodiment in a second working mode;

FIG. 10 is a schematic simulation diagram of a comparator circuit of an embodiment;

FIG. 11 is one of the structural schematic diagrams of a voltage comparison device of an embodiment;

FIG. 12 is a second structural schematic diagram of a voltage comparison device of an embodiment.

Component label description:

Comparator circuit: 10; energy storage circuit: 100; operational amplifier circuit: 200; first-stage operational amplifier: 210; second-stage operational amplifier: 220; Miller compensation structure: 230; signal selection circuit: 300; waveform modulation circuit : 400; NOR gate: 410; reference voltage generating circuit: 500; controller: 20; sampling circuit: 30.

Detailed ways

In order to facilitate understanding of the embodiments of the present application, the following will describe the embodiments of the present application more comprehensively with reference to related drawings. A preferred embodiment of the embodiments of the application is given in the accompanying drawings. However, the embodiments of the present application can be implemented in many different forms, and are not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the embodiments of the present application more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are only for the purpose of describing specific embodiments, and are not intended to limit the application.

It can be understood that the terms "first", "second" and the like used in this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present application, the first resistor R1 could be referred to as the second resistor R2, and similarly, the second resistor R2 could be referred to as the first resistor R1. Both the first resistor R1 and the second resistor R2 are resistors, but they are not the same resistor.

It can be understood that the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the connected circuits, modules, units, etc. have the transmission of electric signals or data between each other.

When used herein, the singular forms "a", "an" and "the/the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising/comprising" or "having" etc. specify the presence of stated features, integers, steps, operations, components, parts or combinations thereof, but do not exclude the presence or addition of one or more The possibility of other features, integers, steps, operations, components, parts or combinations thereof. Meanwhile, the term "and/or" used in this specification includes any and all combinations of the related listed items.

Fig. 1 is one of the circuit diagrams when the comparator circuit 10 of an embodiment receives the first voltage Va, Fig. 2 is one of the circuit diagrams when the comparator circuit 10 of an embodiment receives the second voltage Vb, wherein, when the comparator circuit When 10 receives the first voltage Va, it can be understood that the comparator circuit 10 is in the first working mode; when the comparator circuit 10 receives the second voltage Vb, it can be understood that the comparator circuit 10 is in the second working mode. Referring to FIG. 1 and FIG. 2 together, in this embodiment, the comparator voltage includes an energy storage circuit 100 , an operational amplifier circuit 200 and a first switching element S1 .

The first input terminal of the operational amplifier circuit 200 is used to receive the reference voltage Vref, and the second input terminal of the operational amplifier circuit 200 is connected to the output terminal of the operational amplifier circuit 200 through the first switch element S1, so The first end of the energy storage circuit 100 is used to receive the first voltage Va or the second voltage Vb in time division, and the second end of the energy storage circuit 100 is connected to the second input end of the operational amplifier circuit 200 . Wherein, the first input terminal of the operational amplifier circuit 200 may be a non-inverting input terminal, and the second input terminal of the operational amplifier circuit 200 may be an inverting input terminal.

In this embodiment, the circuit characteristics of the operational amplifier circuit itself can be stored through the energy storage circuit. When the on-off state of the first switch element changes, the circuit characteristics of the operational amplifier circuit itself remain unchanged. The stored charge removes the influence of the offset on the comparison result, thereby improving the sensitivity of the comparator circuit.

In one of the embodiments, the comparator circuit 10 operates in the first working mode when the first switching element S1 is set in the on state and the first switching element S1 is set in the off state When running in the second mode of operation to obtain the comparison results. That is, the comparator circuit 10 is configured with two different operating modes, and the comparator circuit 10 can be in different operating modes by switching the first switching element S1, and after completing a transition from the first operating mode to the second After the switching of the working mode, the comparison result of the first voltage Va and the second voltage Vb is output.

Specifically, continuing to refer to FIG. 1 , the first switching element S1 is controlled to be turned on first, so that the comparator circuit 10 first works in the first working mode. When the first switching element S1 is turned on, the energy storage circuit 100 configured to store charges according to the received first voltage Va and the voltage received at the second terminal. That is, the total charge stored in the energy storage circuit 100 is jointly determined by the first voltage Va and the voltage of the second input terminal of the operational amplifier circuit 200 .

The first switch element S1 is turned off under control after a preset time period, wherein the preset time period is the time required to fully charge the energy storage circuit 100 with the above-mentioned total amount of charge. It can be understood that the conduction of the first switch element S1 The communication duration may also be greater than the above preset duration, which is not limited in this embodiment. Wherein, the conduction duration may be, for example, 0.5 μs, 1 μs, or the like. When the first switching element S1 is turned off, the energy storage circuit 100 is configured to discharge to the second terminal according to the received second voltage Vb and the stored charge, so as to adjust the operational amplifier circuit 200 The voltage at the second input terminal makes the output terminal of the operational amplifier circuit 200 output a voltage corresponding to the comparison result of the comparator circuit 10 .

In the related art, due to the non-ideality of the operational amplifier circuit 200 itself, as well as unavoidable factors in the layout design process and production process, the symmetrical devices in the operational amplifier circuit 200 cannot be completely symmetrical and accurate. Therefore, A system offset and a random offset will be introduced into the operational amplifier circuit 200 . The offset will directly affect the accuracy of the comparator circuit 10, that is, if the difference between the first voltage Va and the second voltage Vb is less than or equal to the offset, the comparator circuit 10 cannot obtain an accurate comparison result. Therefore, in this embodiment, by charging the energy storage circuit 100 first, it can be understood that the circuit characteristics of the operational amplifier circuit 200 itself are first stored, and when switching from the first working mode to the second working mode, the operating The circuit characteristic of the discharge circuit 200 remains unchanged all the time, so the influence of the offset on the comparison result can be removed based on the stored charge, thereby improving the sensitivity of the comparator circuit 10 .

It can be understood that this embodiment does not specifically limit the output voltage Vout when the comparator circuit 10 is in the first working mode, but uses the output voltage Vout in the second working mode to evaluate the difference between the first voltage Va and the second voltage Vb. size relationship. Exemplarily, when the first voltage Va is greater than the second voltage Vb, the comparator circuit 10 outputs a high voltage in the second working mode, for example, 1.8V; when the first voltage Va is less than or equal to the second voltage Vb, the comparator The converter circuit 10 outputs a low voltage, such as 0V, in the second working mode.

Continuing to refer to FIG. 1 and FIG. 2 , in one embodiment, the energy storage circuit 100 includes a first energy storage element and a second energy storage element. The first end of the first energy storage element is used to receive the first voltage Va or the second voltage Vb time-divisionally, and the second end of the first energy storage element is connected to a ground end. The second energy storage element is respectively connected to the first end of the first energy storage element and the second input end of the operational amplifier circuit 200 . Wherein, the first energy storage element may be, for example, an element with a charge storage function such as a capacitor or an inductor, and the second energy storage element may also be, for example, an element with a charge storage function such as a capacitor or an inductor. Moreover, the types of the first energy storage element and the second energy storage element may be the same or different, which is not limited in this embodiment.

Specifically, taking the first energy storage element and the second energy storage element both as capacitors as an example, the working principle of the comparator circuit 10 is specifically analyzed. The first terminal of the second capacitor C2 is used to receive the first voltage Va or the second voltage Vb time-divisionally, and the second terminal of the second capacitor C2 is connected to a ground terminal. The third capacitor C3 is respectively connected to the first terminal of the second capacitor C2 and the second input terminal of the operational amplifier circuit 200 .

Ideally, the operational amplifier circuit 200 has no offset. Referring to FIG. 1 , when the externally input control signal CK controls the first switch element S1 to close, the operational amplifier circuit 200 forms a closed-loop structure. Due to the imaginary short characteristic of the operational amplifier circuit 200, V _{im_1} =V _ip =V _ref , where V _{im_1} refers to the voltage value of the inverting input terminal of the operational amplifier circuit when CK=1, V _ip refers to the voltage value of the non-inverting input terminal of the operational amplifier circuit, and V _ref refers to the reference voltage input externally. Since the first voltage Va is a stable voltage signal, and the capacitor can isolate the DC signal, the voltage of the second input end of the operational amplifier circuit 200 has nothing to do with the first voltage Va. At this time, the amount of charge on the second capacitor C2 is V _a *C ₂ , and the amount of charge on the third capacitor C3 is (V _a -V _{im_1} )*C ₃ =(V _a -V _ip )*C ₃ =( V _a -V _ref )*C ₃ . Referring to FIG. 2 , when the first switch element S1 is turned off, the operational amplifier circuit 200 forms an open-loop structure. At this time, the amount of charge on the second capacitor C2 is V _b *C ₂ , and the amount of charge on the third capacitor C3 is (V _b -V _{im_0} )*C ₃ , wherein, V _{im_0} means that when CK=0, the operation The voltage value of the inverting input terminal of the amplifier circuit.

It can be understood that due to the law of conservation of charge, in the two operating modes of FIG. 1 and FIG. 2 , the total amount of charges on the second capacitor C2 and the third capacitor C3 should be equal. That is, V _a *C ₂ +(V _a -V _ref )*C ₃ =V _b *C ₂ +(V _b -V _{im_0} )*C ₃ . It can be obtained from the above formula,

The voltage at the first input terminal of the operational amplifier circuit 200 remains unchanged at V _ref . therefore,

That is, in the second working mode shown in FIG. 2, V _b -V _a is positively correlated with V _{im_0} -V _ip . Moreover, in the comparison process, the absolute magnitudes of the first voltage Va and the second voltage Vb are not involved. Therefore, the first voltage Va and the second voltage Vb can be very small, such as 10mV, and the first voltage Va and the second voltage Vb can also be large, such as AVDD-10mV, where AVDD is the power supply voltage of the comparator circuit 10 . That is, this embodiment realizes rail-to-rail (rail-to-rail) of the input signal.

In the case that the operational amplifier circuit 200 has an offset, it is assumed that the offset is the offset voltage Voff. When the first switch element S1 is closed, the charge on the third capacitor C3 is (V _a -V _{im_1} )*C ₃ =(V _a -V _ip -Voff)*C ₃ =(V _a -V _ref -Voff )*C ₃ . When the first switching element S1 is turned on, as calculated above,

Due to the existence of the offset voltage Voff, the operational amplifier circuit 200 compares ( _{Vim_0} -Voff) with _Vip , that is,

It can be seen that, in the second working mode shown in FIG. 2 , the offset voltage Voff is canceled out. Therefore, the comparator circuit 10 of this embodiment can completely overcome the influence of the offset of the operational amplifier circuit 200 on the comparison result, thereby providing a comparator circuit 10 with high sensitivity.

In one of the embodiments, the first switch element S1 is configured to be turned on or off under the control of a control signal, and the control signal is configured with two different level states, namely the first level and the second level . Exemplarily, the first level may be a high level, and the second level may be a low level. Wherein, when the control signal is at the first level, the first switch element S1 is turned on, so that the energy storage circuit 100 stores charges according to the first voltage Va and the voltage received by the second terminal. When the control signal is at the second level, the first switch element S1 is turned on, so that the energy storage circuit 100 discharges to the second terminal according to the second voltage Vb and the stored charges. It can be understood that, in other embodiments, the control signal may also be a current signal or the like.

FIG. 3 is a second circuit diagram of the comparator circuit 10 of an embodiment. Referring to FIG. 3 , in this embodiment, the comparator circuit 10 further includes a signal selection circuit 300 . The first input end of the signal selection circuit 300 is used to receive the first voltage Va, the second input end of the signal selection circuit 300 is used to receive the second voltage Vb, and the control of the signal selection circuit 300 The terminal is used to receive the control signal. Optionally, the control signal may be a clock signal CK. The signal selection circuit 300 is configured to select and output the first voltage Va when the control signal is at a first level, and select to output the second voltage Vb when the control signal is at a second level. In the embodiment shown in FIG. 3 , the signal selection circuit 300 is a multiplexer mux. In other embodiments, the signal selection circuit 300 may be a device with a path selection function such as an SPDT switch, which is not limited here. In this embodiment, through the relatively simple connection relationship of the signal selection circuit 300, the time-sharing output of different voltages is realized, which avoids the need for the energy storage circuit 100 to frequently switch the connected voltage ports to receive the first voltage Va or the second voltage Va in a time-sharing manner. In the case of two voltages Vb, the test efficiency of the comparator circuit 10 is improved.

FIG. 4 is a third circuit diagram of the comparator circuit 10 of an embodiment. Referring to FIG. 4 , in this embodiment, the comparator circuit 10 further includes a waveform modulation circuit 400 . The waveform modulating circuit 400 is connected to the output end of the operational amplifier circuit 200 , and is used for outputting a signal waveform corresponding to the comparison result according to the received voltage output from the operational amplifier circuit 200 and the control signal. It can be understood that, by setting the waveform modulation circuit 400, the voltage at the output terminal of the operational amplifier circuit 200 can be visualized, so as to facilitate further analysis based on the comparison result, for example, by obtaining the rising edge time and falling edge time of the signal waveform, etc. Realize more complex analysis functions.

Continuing to refer to FIG. 4 , in one embodiment, the control signal is a clock signal CK, and the waveform modulation circuit 400 includes a NOR gate 410 . One input end of the NOR gate 410 is connected to the output end of the operational amplifier circuit 200, the other input end of the NOR gate 410 is used for receiving the clock signal CK, and the NOR gate 410 is used for The signal waveform is generated according to the voltage output by the operational amplifier circuit 200 and the clock signal CK. In this embodiment, when the clock signal CK is at a high level, no matter whether the output terminal voltage of the operational amplifier circuit 200 is at a high level or at a low level, the signal waveform corresponds to a low level at this moment. When the clock signal CK is at When the level is low, the signal waveform corresponds to the inversion signal of the output terminal voltage of the operational amplifier circuit 200 at this moment. In other embodiments, the waveform modulation circuit 400 may also be other logic gates, such as NAND gates, but the type of the logic gates should correspond to the switching logic of the first switching device.

Fig. 5 is the fourth circuit diagram of the comparator circuit 10 of an embodiment, with reference to Fig. 5, in the present embodiment, the comparator circuit 10 also includes a reference voltage generating circuit 500, the first reference voltage generating circuit 500 and the operational amplifier circuit 200 connected to an input terminal and used to generate the reference voltage Vref. Continuing to refer to FIG. 5 , the reference voltage generating circuit 500 may include a second resistor R2 and a third resistor R3, and provide a reference voltage Vref through resistor division. For example, the ratio of the second resistor R2 to the third resistor R3 may be is 4:3, then the reference voltage Vref is

It can be understood that the above-mentioned resistance ratios are only for illustrative purposes, and are not intended to limit the protection scope of this embodiment.

FIG. 6 is the fifth circuit diagram of the comparator circuit 10 of an embodiment. Referring to FIG. 6, in this embodiment, the reference voltage generating circuit 500 further includes a fourth switching element S4, and the fourth switching element S4 is connected in series between the ground terminal and the on the path between the supply voltage terminals AVDD. Exemplarily, the fourth switch element S4 may be a MOS transistor, and the fourth switch element S4 may be respectively connected to the second resistor R2 and the power supply voltage terminal AVDD as shown in FIG. 6 . The fourth switch element S4 is turned on or off under the control of the power signal. Specifically, the fourth switch element S4 of this embodiment is controlled by the inversion signal pwron_b of the power signal. When the power signal pwron is at a high level, the inversion The phase signal pwron_b is low, and controls the conduction of the path between the ground terminal and the power voltage terminal AVDD, so that the reference voltage generating circuit 500 outputs the reference voltage Vref. In this embodiment, by controlling whether the reference voltage generating circuit 500 outputs the reference voltage Vref through the fourth switch element S4, the power consumption of the comparator circuit 10 can be effectively reduced when the comparator circuit 10 is not working.

Continuing to refer to FIG. 6 , in one of the embodiments, the comparator circuit 10 further includes a third switch element S3, and the third switch element S3 is connected to the first input end of the reference voltage generation circuit 500 and the operational amplifier circuit 200 , the third switch element S3 is configured to be turned on when the control signal is at a first level, and turned on and off when the control signal is at a second level. Further, the comparator circuit 10 further includes a fourth capacitor C4, the fourth capacitor C4 is used to store charges when the third switch element S3 is turned on, and to hold the operational amplifier through the stored charges when the third switch element S3 is turned off. The voltage level at the first input of circuit 200 does not change. Based on the above circuit structure, the power consumption of the comparator circuit 10 can be reduced without affecting the accuracy of the comparison result.

Fig. 7 is the sixth circuit diagram of the comparator circuit 10 of an embodiment, with reference to Fig. 7, in this embodiment, the operational amplifier circuit 200 includes a two-stage operational amplifier and a dense circuit connected between the two operational amplifiers Le compensation structure 230 .

Specifically, the first-stage operational amplifier 210 includes a MOS transistor p1, a MOS transistor n1, a MOS transistor p2, a MOS transistor n2, and a MOS transistor n3. Wherein, the gate of MOS transistor p1 is connected to the gate of MOS transistor p2, the source of MOS transistor p1 is connected to the source of MOS transistor p2, the drain of MOS transistor p1 is respectively connected to the drain of MOS transistor n1, and the drain of MOS transistor p1 The gate of the MOS transistor p2 is connected to the drain of the MOS transistor n2, the gate of the MOS transistor n1 is used as the first input terminal of the operational amplifier circuit 200, and the gate of the MOS transistor n2 is used as the first input terminal of the operational amplifier circuit 200 Two input terminals, the source of MOS transistor n1 is connected to the source of MOS transistor n2, the gate of MOS transistor n2 is used to receive the bias voltage Nbias, the source of MOS transistor n2 is connected to the ground terminal, and the drain of MOS transistor n2 Connect with the source of MOS transistor n1. The second-stage operational amplifier 220 includes MOS transistor p3 and MOS transistor n4, the gate of MOS transistor p3 is connected to the drain of MOS transistor p2, the source of MOS transistor p3 is connected to the power supply voltage terminal AVDD, and the drain of MOS transistor p3 is connected to The drain of the MOS transistor n4 is connected, the source of the MOS transistor n4 is used to receive the bias voltage Nbias, the source of the MOS transistor n4 is connected to the ground terminal, and the node between the drain of the MOS transistor p3 and the drain of the MOS transistor n4 As the output terminal of the operational amplifier circuit 200. In this embodiment, through the structure of the two-stage operational amplifier, the output swing can be effectively increased on the basis of ensuring the gain, so as to realize the rail-to-rail of the output.

It can be understood that, in the related art, the comparable range of the comparator circuit is limited by the threshold voltage Vth of the MOS transistor. If an NMOS input is used, the minimum value of the input signal (Vip or Vim) at one of the input terminals is at least V _{ds_N3} +V _{gs_N1/N2} , the value is generally around 0.5V-0.8V, thus losing part of the comparable range. If PMOS input is used, the maximum value of the input signal (Vip or Vim) at one of the inputs cannot exceed AVDD-V _{ds_P3} -V _{gs_P1/P2} , similarly, the value is generally AVDD-0.8V to AVDD-0.5V, thus also Part of the comparable range will be lost. If a comparator circuit with combined input of NMOS and PMOS is used, since there are two sets of input pair transistors, two sets of bias voltages Nbias and Pbias need to be applied at the same time, which greatly increases the complexity of the circuit and introduces additional power consumption. Compared with the comparator circuit using a combination of NMOS and PMOS inputs, in this embodiment, only one set of input pair transistors is needed, and correspondingly, only one set of bias voltages (that is, Nbias in FIG. 7 ) is needed, namely The required comparison function can be realized. It will be appreciated that the amount of bias voltage is positively related to the power consumption of the comparator circuit. Therefore, this embodiment uses the relatively simple circuit structure and relatively small power consumption of the two-stage operational amplifier with NMOS input, based on the large-swing output characteristics of the two-stage operational amplifier itself, combined with the energy storage compensation function of the aforementioned energy storage circuit 100. The above supported large input range together realizes a rail-to-rail comparator circuit 10 at both input and output terminals.

Continuing to refer to FIG. 7, a Miller compensation structure 230 is connected between the drain of the MOS transistor p3 and the drain of the MOS transistor p3, and the Miller compensation structure 230 includes a first resistor R1, a first capacitor C1 and a first capacitor C1 connected in series. Two switching elements S2. In this embodiment, the Miller compensation structure 230 can produce the Miller Effect (Miller Effect), which refers to the increase in the equivalent capacitance that occurs when a capacitor is connected from the input to the output of an amplifier with a large negative gain. effect. It can be understood that the capacitor has the function of suppressing the signal fluctuation in the circuit, thereby improving the stability of the circuit. Therefore, by setting the Miller compensation structure 230 , the above-mentioned effect of increasing the equivalent capacitance can be produced, thereby effectively improving the stability of the operational amplifier circuit 200 . Moreover, by controlling the second switching element S2 to be turned on when the control signal is at the first level, and turned on and off when the control signal is at the second level, the operational amplifier circuit 200 can be operated in a closed-loop structure , it has better stability, and in the open-loop structure, it has better response speed, and realizes the rapid output of the comparison result of the comparator circuit 10 .

Specifically, FIG. 8 is an equivalent circuit diagram of the comparator circuit 10 of an embodiment in the first operating mode, and FIG. 9 is an equivalent circuit diagram of the comparator circuit 10 of an embodiment in the second operating mode. What needs to be explained Yes, in order to show the equivalent circuit structure of the actual operation more clearly, in Figure 8 and Figure 9, the switch that is turned on and closed is shown as a wire, and the switch that is not connected to the operational amplifier circuit under the control of the switching element is omitted 200 part of the circuit structure. With reference voltage Vref as

For example, referring to FIG. 8 , in the first working mode, the first switching element S1 is closed, the second switching element S2 is closed, the third switching element S3 is closed, and the fourth switching element S4 is conductive, and the operational amplifier circuit 200 forms a closed-loop structure. , ideally, the operational amplifier circuit 200 has no offset. The signal selection circuit 300 outputs the first voltage Va. Due to the virtual short characteristic of the operational amplifier circuit 200,

Wherein, V _{im_1} refers to the voltage value of vim when CK=1. Since the first voltage Va is a stable voltage signal, and the capacitor can isolate the DC signal, the voltage of the second input end of the operational amplifier circuit 200 has nothing to do with the first voltage Va. At this time, the amount of charge on the second capacitor C2 is V _a *C ₂ , and the amount of charge on the third capacitor C3 is

Referring to FIG. 9, in the second working mode, the first switching element S1 is turned off, the second switching element S2 is turned off, the third switching element S3 is turned off, and the fourth switching element S4 is turned on, and the operational amplifier circuit 200 constitutes an open loop structure, the signal selection circuit 300 outputs the second voltage Vb. At this time, the amount of charge on the second capacitor C2 is V _b *C ₂ , and the amount of charge on the third capacitor C3 is (V _b -V _{im_0} )*C ₃ , wherein, V _{im_0} means that when CK=0 The voltage value of vim.

It can be understood that due to the law of conservation of charge, in the two operating modes, the total amount of charge on the second capacitor C2 and the third capacitor C3 should be equal. Right now,

It can be obtained from the above formula,

And the voltage of the first input end of the operational amplifier circuit 200 remains as

constant. therefore,

That is, in the second working mode, V _b -V _a is positively correlated with V _{im_0} -V _p . Moreover, in the comparison process, the absolute magnitudes of the first voltage Va and the second voltage Vb are not involved, and the specific value of the reference voltage Vref will not affect the comparison result.

In the case that the operational amplifier circuit 200 has an offset, it is assumed that the offset is the offset voltage Voff. When the first switch element S1 is closed, the charge on the third capacitor C3 is (V _a -V _{im_1} )*C ₃ =(V _a -V _ip -Voff)*C ₃ =(V _a -V _ref -Voff )*C ₃ . When the first switching element S1 is turned on, as calculated above,

Due to the existence of the offset voltage Voff, the operational amplifier circuit 200 compares (V _{im_0} −Voff) with V _{ip_0} , that is,

It can be seen that, in the second working mode, the offset voltage Voff is canceled out. Therefore, the comparator circuit 10 of this embodiment can completely overcome the influence of the offset of the operational amplifier circuit 200 on the comparison result, thereby providing a comparator circuit 10 with high sensitivity.

FIG. 10 is a schematic diagram of a simulation of the comparator circuit 10 of an embodiment. Referring to FIG. 10, when the first voltage Va is less than the second voltage Vb, the signal waveform output by the waveform modulation circuit 400 is a pulse signal; when the first voltage Va is greater than the second voltage Vb When the second voltage is Vb, the signal waveform output by the waveform modulation circuit 400 is a square wave signal, thereby realizing the comparison of the input signals and outputting a signal waveform corresponding to the comparison result. It should be noted that the input signal should satisfy

AVDD, that is,

In order to avoid the breakdown of the MOS tube in the operational amplifier circuit 200 .

FIG. 11 is one of the structural schematic diagrams of a voltage comparison device of an embodiment. With reference to FIG. 11 , the voltage comparison device includes the above-mentioned comparator circuit 10 and a controller 20, and the controller 20 is connected to the comparator circuit 10 for output control signals including the first level and the second level, the controller 20 sets the first switch element in the conduction state through the control signal of the first level, and sets the first switch element to the conduction state through the control signal of the second level. The element is set to the OFF state. It can be understood that, the structure of the comparator circuit 10 in this embodiment may refer to the foregoing embodiments, and details are not repeated here. Based on the aforementioned comparator circuit 10, this embodiment provides a voltage comparison device with high sensitivity.

FIG. 12 is the second structural diagram of a voltage comparison device in an embodiment. Referring to FIG. 12, in this embodiment, when the comparator circuit 10 includes a waveform modulation circuit 400, the voltage comparison device also includes a sampling circuit 30 The sampling circuit 30 is connected with the waveform modulation circuit 400, and is used for sampling the signal waveform output by the waveform modulation circuit 400, and outputting a digital signal carrying a voltage comparison result according to the sampling result. Wherein, the sampling circuit 30 performs sampling at an appropriate time point, and outputs 0 when multiple 0s are continuously sampled, or outputs 1 when multiple 1s are continuously sampled. It can be understood that this embodiment does not limit the specific structure of the sampling circuit 30 , as long as it can perform sampling at a preset interval with the received signal, it falls within the scope of protection of this embodiment.

An embodiment of the present application also provides an analog-to-digital converter, including the voltage comparison device as described above, and the voltage comparison device is configured to generate a corresponding digital signal according to an analog signal to be converted and a preset threshold signal. Based on the aforementioned voltage comparison device, this embodiment can provide an analog-to-digital converter with high conversion precision. Wherein, the analog-to-digital converter can be, but not limited to, SAR ADC (Successive Approximation ADC) and ∑–△ ADC.

In one of the embodiments, a method for controlling a comparator circuit is provided. In this embodiment, the method for controlling a comparator circuit is used to control the comparator circuit in any of the foregoing embodiments. The control method includes: It includes first control for setting the first switching element in an on state and second control for setting the first switching element in an off state. In this embodiment, by first storing the circuit characteristics of the operational amplifier circuit itself, the influence of the offset on the comparison result can be removed based on the stored charge, thereby providing a control method with high comparison sensitivity.

Specifically, taking the comparator circuit shown in FIG. 1 and FIG. 2 as an example, the processor outputs a control signal of a first level, and the control signal of the first level is used to set the first switching element S1 to the conduction The on state, specifically to control the energy storage circuit 100 to store charges according to the received first voltage Va and the voltage received at the second terminal, and to control the connection between the second input terminal of the operational amplifier circuit 200 and the operational amplifier circuit 200 The output terminal is turned on, wherein the first input terminal of the operational amplifier circuit 200 is used to receive the reference voltage Vref, and the second terminal of the energy storage circuit 100 is connected to the second input terminal of the operational amplifier circuit 200 .

The processor outputs a control signal of a second level, and the control signal of the second level is used to set the first switching element S1 in an off state, specifically to control the energy storage circuit 100 according to the received second The voltage Vb and the stored charge are discharged to the second terminal, and the second input terminal of the operational amplifier circuit 200 is controlled to be disconnected from the output terminal of the operational amplifier circuit 200 to adjust the second input terminal of the operational amplifier circuit 200 terminal voltage, so that the output terminal of the operational amplifier circuit 200 outputs a voltage corresponding to the comparison result of the comparator circuit 10 .

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the scope of the patent for the invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the embodiments of the present application, and these all belong to the protection scope of the embodiments of the present application. Therefore, the scope of protection of the embodiment patent of this application should be based on the appended claims.

Claims (20)

1. A comparator circuit for comparing a first voltage with a second voltage, the comparator voltage comprising an energy storage circuit, an operational amplifier circuit and a first switching element; wherein,

   The first input terminal of the operational amplifier circuit is used to receive a reference voltage, the second input terminal of the operational amplifier circuit is connected to the output terminal of the operational amplifier circuit through the first switch element, and the energy storage circuit The first terminal is used to receive the first voltage or the second voltage in time division, and the second terminal of the energy storage circuit is connected to the second input terminal of the operational amplifier circuit.
2. The comparator circuit according to claim 1, said comparator circuit operates in a first operation mode when said first switching element is set to an on state and has said first switching element set to an off state. In the state, it operates in the second working mode to obtain the comparison result.
3. The comparator circuit according to claim 2, the first operation mode is that when the first switching element is turned on, the energy storage circuit is configured to receive the first voltage and the second terminal The received voltage stores the charge;

   The second working mode is that when the first switching element is turned off, the energy storage circuit is configured to discharge to the second terminal according to the received second voltage and the stored charge, so as to adjust the operation The voltage of the second input terminal of the amplifier circuit is used to make the output terminal of the operational amplifier circuit output a voltage corresponding to the comparison result of the comparator circuit.
4. The comparator circuit according to claim 1, said tank circuit comprising:

   a first energy storage element, the first end of the first energy storage element is used to receive the first voltage or the second voltage in time division, and the second end of the first energy storage element is connected to a ground terminal;

   The second energy storage element is respectively connected to the first end of the first energy storage element and the second input end of the operational amplifier circuit.
5. The comparator circuit according to claim 4, the first energy storage element and the second energy storage element are capacitors.
6. According to the comparator circuit according to any one of claims 1 to 5, the first switching element is configured to be turned on or off under the control of a control signal, and when the control signal is at a first level, the first A switch element is turned on, so that the energy storage circuit stores charges according to the first voltage and the voltage received by the second terminal; when the control signal is at a second level, the first switch element is turned on, making the energy storage circuit discharge to the second terminal according to the second voltage and the stored charge.
7. The comparator circuit of claim 6, further comprising:

   Signal selection circuit, the first input terminal of the signal selection circuit is used to receive the first voltage, the second input terminal of the signal selection circuit is used to receive the second voltage, the control terminal of the signal selection circuit For receiving the control signal, the signal selection circuit is used for selecting and outputting the first voltage when the control signal is at a first level, and selecting and outputting the first voltage when the control signal is at a second level second voltage.
8. The comparator circuit according to claim 7, said control signal is a clock signal.
9. The comparator circuit of claim 6, further comprising:

   A waveform modulation circuit, connected to the output terminal of the operational amplifier circuit, for outputting a signal waveform corresponding to the comparison result according to the received voltage output by the operational amplifier circuit and the control signal.
10. The comparator circuit according to claim 9, the control signal is a clock signal, and the waveform modulation circuit comprises:

    A NOR gate, one input end of the NOR gate is connected with the output end of the operational amplifier circuit, the other input end of the NOR gate is used for receiving the clock signal, and the NOR gate is used for receiving the clock signal according to The voltage output by the operational amplifier circuit and the clock signal generate the signal waveform.
11. According to the comparator circuit according to claim 9, when the first voltage is lower than the second voltage, the signal output by the waveform modulation circuit is a pulse signal;

    When the first voltage is greater than the second voltage, the signal output by the waveform modulation circuit is a square wave signal.
12. The comparator circuit according to claim 6, said operational amplifier circuit comprises two stages of operational amplifiers and a Miller compensation structure connected between said two stages of said operational amplifiers, said Miller compensation structure comprising a series-connected first A resistor, a first capacitor, and a second switch element, the second switch element is used to turn on when the control signal is at a first level, and turn on and off when the control signal is at a second level.
13. The comparator circuit of claim 6, further comprising:

    a reference voltage generating circuit, configured to generate the reference voltage;

    The third switching element is respectively connected to the first input end of the reference voltage generation circuit and the operational amplifier circuit, and the third switching element is used to conduct when the control signal is at the first level, and to be turned on when the control signal is at the first level. When the control signal is at the second level, it is turned on and off.
14. The comparator circuit according to claim 13, wherein the reference voltage generation circuit includes a second resistor, a third resistor, and a fourth switching element connected in series between the ground terminal and the power supply voltage terminal, and the fourth switching element uses It is turned on or off under the control of the power signal.
15. The comparator circuit according to claim 14, the ratio of the second resistor to the third resistor is 4:3.
16. The comparator circuit according to claim 13, the reference voltage further includes a fourth switching element connected in series on a path between the ground terminal and the power supply voltage terminal.
17. A voltage comparison device, comprising:

    A comparator circuit as claimed in any one of claims 1 to 16;

    A controller, connected to the comparator circuit, for outputting a control signal including a first level and a second level.
18. According to the voltage comparison device according to claim 17, when the comparator circuit includes a waveform modulation circuit, the voltage comparison device further includes:

    A sampling circuit, connected to the waveform modulation circuit, is used for sampling the signal waveform output by the waveform modulation circuit, and outputting a digital signal carrying a voltage comparison result according to the sampling result.
19. An analog-to-digital converter, comprising the voltage comparison device according to claim 17 or 18, the voltage comparison device is used to generate a corresponding digital signal according to the analog signal to be converted and a preset threshold signal.
20. A control method for a comparator circuit, used for controlling the comparator circuit according to any one of claims 1 to 16, the control method comprising:

    It includes first control for setting the first switching element in an on state and second control for setting the first switching element in an off state.

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