CN113471088A - Optimized POP repackaging method adopting MUF process - Google Patents
Optimized POP repackaging method adopting MUF process Download PDFInfo
- Publication number
- CN113471088A CN113471088A CN202110732194.4A CN202110732194A CN113471088A CN 113471088 A CN113471088 A CN 113471088A CN 202110732194 A CN202110732194 A CN 202110732194A CN 113471088 A CN113471088 A CN 113471088A
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- China
- Prior art keywords
- substrate
- steel mesh
- muf
- insulating glue
- method adopting
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Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 229910000831 Steel Inorganic materials 0.000 claims abstract description 38
- 239000010959 steel Substances 0.000 claims abstract description 38
- 239000003292 glue Substances 0.000 claims abstract description 31
- 238000007639 printing Methods 0.000 claims abstract description 23
- 229910000679 solder Inorganic materials 0.000 claims abstract description 14
- 238000005516 engineering process Methods 0.000 claims abstract description 13
- 239000004033 plastic Substances 0.000 claims abstract description 8
- 238000005476 soldering Methods 0.000 claims abstract description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000009517 secondary packaging Methods 0.000 description 4
- 238000001746 injection moulding Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000011514 reflex Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83024—Applying flux to the bonding area
Abstract
The invention discloses an optimized POP (point of presence package) repackaging method adopting MUF (multi-media object) process, which comprises the following steps of printing solder paste on a substrate pad position by using a first steel mesh in an SMT (surface mounting technology) process; printing insulating glue on the substrate by using a second steel mesh; performing FCDA, mounting the BGA chip on a substrate, performing reflow soldering, and then baking and curing the insulating glue; and (5) carrying out MUF plastic package. The invention can effectively solve the problems of high process cost, incomplete filling and reliability risk in the prior art.
Description
Technical Field
The invention belongs to the technical field of integrated circuit packaging, and particularly relates to an optimized POP re-packaging method adopting an MUF process.
Background
BGA: ball Grid Array packaging is a surface mount packaging technology applied to integrated circuits.
And (4) POP packaging: and sticking a packaged package chip to a new carrier substrate again, and carrying out secondary packaging.
When the solder balls of the BGA chip needing secondary packaging are uniformly distributed, the BGA chip can be completely filled by adopting an MUF (Molded underfill) process, and no hole or layering problem exists between the chip and the substrate. Referring to fig. 1, another situation is the uneven distribution of the solder balls of the BGA chip, especially the solder balls are distributed only in the edge circles, and the middle area is a blank area. In this case, if the conventional MUF process is used, underfill tends to occur, a void may be formed between the chip and the substrate, and reliability may be at risk. If the CUF process is adopted, the filling problem can be solved, but the cost of CUF (Capillary underfill) is higher than that of MUF by a large amount.
Disclosure of Invention
Aiming at the technical problems, the invention provides an optimized POP repackaging method adopting an MUF process, which is used for solving the problems of high process cost, incomplete filling and reliability risk in the prior art.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
the invention provides an optimized POP repackaging method adopting an MUF process, which comprises the following steps:
printing solder paste on a substrate bonding pad by using a first steel mesh in an SMT (surface mount technology) process;
printing insulating glue on the substrate by using a second steel mesh;
performing FCDA, mounting the BGA chip on a substrate, performing reflow soldering, and then baking and curing the insulating glue;
and (5) carrying out MUF plastic package.
The invention further improves the following steps: in the step of printing the insulating glue on the substrate by using the second steel mesh, the second steel mesh is provided with a hole pattern, and the printed insulating glue is consistent with the hole pattern of the steel mesh.
The invention further improves the following steps: in the step of printing the insulating glue on the substrate by using the second steel mesh, the opening pattern is an array pattern.
The invention further improves the following steps: in the step of printing the insulating glue on the substrate by using the second steel mesh, the opening pattern is an array type rice-shaped pattern.
The invention further improves the following steps: in the step of printing the insulating glue on the substrate by using the second steel mesh, the opening patterns are array patterns, and each pattern is a similar-rice-shaped pattern formed by eight collective through holes.
The invention further improves the following steps: in the step of printing the insulating glue on the substrate by using the second steel mesh, the height of the second steel mesh is less than or equal to the height of a tin ball standing on the BGA chip.
The invention further improves the following steps: the substrate is provided with a plurality of bonding pads which are positioned on the substrate and close to the edge; the insulating glue is printed in the middle area without the bonding pad on the substrate.
The invention further improves the following steps: in the step of printing the insulating glue on the substrate by using the second steel mesh, a groove is formed in the second steel mesh, and the groove of the second steel mesh covers the bonding pad of the substrate and the printed solder paste when the insulating glue is printed.
The invention further improves the following steps: the thickness of the second steel net is 80-100 μm.
The invention further improves the following steps: and carrying out FCDA (Flexible printed Circuit Board), mounting the BGA chip on the substrate, carrying out insulating glue baking and curing after reflow soldering, and using the Mesh cover to prevent the substrate from warping when mounting the BGA chip on the substrate.
The invention has the beneficial effects that: the invention reduces the cost of the heavy packaging, solves the problem of the cavity between the chip and the substrate and improves the reliability of the heavy packaging body. The invention can reduce the cost of secondary packaging, simultaneously solve the problem of cavities between the MUF process BGA chip and the substrate, and improve the reliability of the secondary packaging body. The invention can solve the problem that cavities are easy to appear between the re-packaged BGA chip and the carrier substrate when an MUF process is used, and the reliability of repackage products is further enhanced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a front view of a BGA chip;
FIG. 2 is a view of the steel mesh after printing of solder paste;
FIG. 3 is a steel mesh view after printing an insulating paste;
FIG. 4 is a diagram of post-FCDA effects;
FIG. 5 is a transmission scan of SAT after MUF;
FIG. 6 is a reflection scan of SAT after MUF.
Detailed Description
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings. It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The following detailed description is exemplary in nature and is intended to provide further details of the invention. Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention.
An optimized POP repackaging method adopting an MUF process comprises the following steps:
step 1, printing solder paste on a substrate bonding pad position by using a first steel mesh in an SMT (surface mount technology) process, wherein the solder paste is used for the subsequent welding of a BGA chip and a substrate, and the effect is shown in FIG. 2;
step 2, printing insulating glue on the substrate by taking the second steel mesh, wherein the printed glue is consistent with the hole patterns of the steel meshes, and the effect is shown in figure 3;
step 3, carrying out flip chip attach (FCDA), attaching the BGA chip to the substrate, baking and curing glue after reflex, wherein the effect is shown in fig. 4;
and 4, using the plastic package material to carry out MUF plastic package, wherein the injection pressure is 1.6T, the effect is shown in figures 5 and 6, and the problem of cavities is solved. And (5) carrying out normal operation of each subsequent procedure after plastic packaging. Description of the principle: after the insulation glue array with the shape of a Chinese character 'mi' and the height of about 80um is arranged in the blank area, epoxy resin plastic packaging materials can fill the whole area below the chip containing the shape of the Chinese character 'mi' along the gullies of the array during molding under the action of injection molding pressure. The array acts as a guide for the flow of the mold compound. Without the mi-array, it is difficult to completely fill the empty areas only under the injection molding pressure, especially in the middle area, which causes the void problem.
In step 2, the thickness of the second steel mesh is selected according to the stand height of the BGA chip solder balls.
Wherein, in step 2, the thickness of the steel mesh can be 80-100 um.
In step 2, when the second steel mesh prints the insulating glue on the substrate, the positions of the open holes and the solder paste are kept away by the grooves, so that the printed solder paste effect is prevented from being influenced during printing.
In step 2, the opening pattern is an array pattern.
Wherein, in the step 2, the opening patterns are array type rice-shaped patterns.
In the step 2, the opening patterns are array patterns, and each pattern is a similar-meter-shaped pattern formed by eight collective through holes.
In step 3, when the BGA chip is mounted on the substrate, a Mesh cover (Mesh cover) is used to improve the warpage of the substrate.
Wherein, in the step 4, the plastic package material is 20um filler size.
It will be appreciated by those skilled in the art that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed above are therefore to be considered in all respects as illustrative and not restrictive. All changes which come within the scope of or equivalence to the invention are intended to be embraced therein.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (10)
1. An optimized POP repackaging method adopting an MUF process is characterized by comprising the following steps:
printing solder paste on a substrate bonding pad by using a first steel mesh in an SMT (surface mount technology) process;
printing insulating glue on the substrate by using a second steel mesh;
performing FCDA, mounting the BGA chip on a substrate, performing reflow soldering, and then baking and curing the insulating glue;
and (5) carrying out MUF plastic package.
2. The optimized POP repackaging method adopting MUF technology as claimed in claim 1, wherein: in the step of printing the insulating glue on the substrate by using the second steel mesh, the second steel mesh is provided with a hole pattern, and the printed insulating glue is consistent with the hole pattern of the steel mesh.
3. The optimized POP repackaging method adopting MUF technology as claimed in claim 2, wherein: in the step of printing the insulating glue on the substrate by using the second steel mesh, the opening pattern is an array pattern.
4. The optimized POP repackaging method adopting MUF technology as claimed in claim 2, wherein: in the step of printing the insulating glue on the substrate by using the second steel mesh, the opening pattern is an array type rice-shaped pattern.
5. The optimized POP repackaging method adopting MUF technology as claimed in claim 2, wherein: in the step of printing the insulating glue on the substrate by using the second steel mesh, the opening patterns are array patterns, and each pattern is a similar-rice-shaped pattern formed by eight collective through holes.
6. The optimized POP repackaging method adopting MUF technology as claimed in claim 1, wherein: in the step of printing the insulating glue on the substrate by using the second steel mesh, the height of the second steel mesh is less than or equal to the height of a tin ball standing on the BGA chip.
7. The optimized POP repackaging method adopting MUF technology as claimed in claim 1, wherein: the substrate is provided with a plurality of bonding pads which are positioned on the substrate and close to the edge; the insulating glue is printed in the middle area without the bonding pad on the substrate.
8. The optimized POP repackaging method adopting MUF technology as claimed in claim 1, wherein: in the step of printing the insulating glue on the substrate by using the second steel mesh, a groove is formed in the second steel mesh, and the groove of the second steel mesh covers the bonding pad of the substrate and the printed solder paste when the insulating glue is printed.
9. The optimized POP repackaging method adopting MUF technology as claimed in claim 1, wherein: the thickness of the second steel net is 80-100 μm.
10. The optimized POP repackaging method adopting MUF technology as claimed in claim 1, wherein: and carrying out FCDA (Flexible printed Circuit Board), mounting the BGA chip on the substrate, carrying out insulating glue baking and curing after reflow soldering, and using the Mesh cover to prevent the substrate from warping when mounting the BGA chip on the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110732194.4A CN113471088A (en) | 2021-06-29 | 2021-06-29 | Optimized POP repackaging method adopting MUF process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110732194.4A CN113471088A (en) | 2021-06-29 | 2021-06-29 | Optimized POP repackaging method adopting MUF process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113471088A true CN113471088A (en) | 2021-10-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110732194.4A Pending CN113471088A (en) | 2021-06-29 | 2021-06-29 | Optimized POP repackaging method adopting MUF process |
Country Status (1)
| Country | Link |
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| CN (1) | CN113471088A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013247343A (en) * | 2012-05-29 | 2013-12-09 | Fdk Corp | Thick copper wiring board |
| CN109548313A (en) * | 2018-11-30 | 2019-03-29 | 深圳市德仓科技有限公司 | A kind of FPC component paster technique |
| CN109979836A (en) * | 2019-04-09 | 2019-07-05 | 深圳市圆方科技新材料有限公司 | A kind of flip-chip UV photocuring packaging method |
| CN111545856A (en) * | 2020-05-15 | 2020-08-18 | 宁波奥克斯电气股份有限公司 | Method for preventing wave soldering from being connected and welded, printing screen and electric control board |
-
2021
- 2021-06-29 CN CN202110732194.4A patent/CN113471088A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013247343A (en) * | 2012-05-29 | 2013-12-09 | Fdk Corp | Thick copper wiring board |
| CN109548313A (en) * | 2018-11-30 | 2019-03-29 | 深圳市德仓科技有限公司 | A kind of FPC component paster technique |
| CN109979836A (en) * | 2019-04-09 | 2019-07-05 | 深圳市圆方科技新材料有限公司 | A kind of flip-chip UV photocuring packaging method |
| CN111545856A (en) * | 2020-05-15 | 2020-08-18 | 宁波奥克斯电气股份有限公司 | Method for preventing wave soldering from being connected and welded, printing screen and electric control board |
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