CN113451394B - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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CN113451394B
CN113451394B CN202110737105.5A CN202110737105A CN113451394B CN 113451394 B CN113451394 B CN 113451394B CN 202110737105 A CN202110737105 A CN 202110737105A CN 113451394 B CN113451394 B CN 113451394B
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epitaxial wafer
dielectric layer
groove
layer
semiconductor device
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CN113451394A (en
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童小东
邢利敏
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Shenzhen Times Suxin Technology Co Ltd
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Shenzhen Times Suxin Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention provides a semiconductor device and a method for manufacturing the semiconductor device, wherein the device comprises the following components: the first epitaxial wafer is provided with two grooves and comprises a two-dimensional electron gas structure layer; the first dielectric layer is deposited in the two grooves, and the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer; a first metal layer is deposited on the first dielectric layers in the two grooves to form a source electrode and a drain electrode; the grid electrode is formed by depositing a second metal layer at a designated position on the upper surface of the first epitaxial wafer. According to the semiconductor device, the first dielectric layers with low dielectric constants are filled below the metal layers corresponding to the drain electrode and the source electrode respectively, the depth of the first dielectric layers is lower than that of the two-dimensional electron gas structural layer, and parasitic capacitance effect generated by mutual coupling among the grid electrode, the source electrode and the drain electrode can be reduced by the structural form, so that the working frequency of the device can be improved, and the manufacturing cost of the device can be controlled while the yield and the reliability of the device are ensured due to the fact that the grid length does not need to be changed.

Description

Semiconductor device and method for manufacturing semiconductor device
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the semiconductor device.
Background
HEMT (High Electron Mobility Transistor ) is widely applied to design and manufacture of circuits such as power amplifier and low noise amplifier, and is an important device of modern microwave design integrated circuit; as the communication technology enters 5G (5 th GenerationMobile Communication Technology, abbreviated as 5G), 6G (6 th Generation Mobile Communication Technology, abbreviated as 6G), even in the terahertz communication era, the carrier frequency increases, which requires the working frequency of HEMTs to increase; in the related art, in order to increase the operating frequency of the HEMT, a method of reducing the gate length of the HEMT, that is, reducing the width of the gate is generally adopted, but the reduction of the gate length increases the cost of the HEMT significantly, and the yield and reliability of the HEMT are also affected.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method of the semiconductor device, which are used for improving the working frequency of HEMTs.
The present invention provides a semiconductor device including: the semiconductor device comprises a first epitaxial wafer with a first groove and a second groove, a first dielectric layer with a low dielectric constant, a grid electrode arranged on the upper surface of the first epitaxial wafer, a source electrode arranged in the first groove and a drain electrode arranged in the second groove; the source electrode and the drain electrode are arranged on two sides of the grid electrode; the first epitaxial wafer comprises a two-dimensional electron gas structure layer; the first dielectric layer is deposited in the first groove and the second groove, and the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structural layer; a first metal layer is deposited on the first dielectric layer in the first groove and the second groove to form a source electrode and a drain electrode; the grid electrode is formed by depositing a second metal layer at a designated position on the upper surface of the first epitaxial wafer.
Further, the upper surfaces of the first metal layers in the first groove and the second groove are higher than the upper surface of the first epitaxial wafer.
Further, the side surfaces of the first metal layer in the first groove and the second groove are communicated with the two-dimensional electron gas structural layer.
Further, an isolation region is arranged in the edge preset region of the first epitaxial wafer.
Further, the material of the first dielectric layer includes silicon nitride or silicon dioxide.
The invention provides a method for manufacturing a semiconductor device, which comprises the following steps: obtaining a second epitaxial wafer; the second epitaxial wafer is provided with a first groove and a second groove, and a second dielectric layer is deposited on a first area except the first groove and the second groove on the upper surface of the second epitaxial wafer; the second epitaxial wafer comprises a two-dimensional electron gas structure layer; depositing a first dielectric layer with low dielectric constant on the second epitaxial wafer; wherein, in the first groove and the second groove, the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer; and processing the second epitaxial wafer with the first dielectric layer to obtain the semiconductor device.
Further, the second epitaxial wafer is obtained by: forming an isolation region in a preset region at the edge of the initial epitaxial wafer obtained in advance to obtain an epitaxial wafer with the isolation region; the initial epitaxial wafer comprises a two-dimensional electron gas structure layer; the lower surface of the isolation region is lower than the lower surface of the two-dimensional electron gas structure layer; depositing a second dielectric layer in a first area on the upper surface of the epitaxial wafer with the isolation area; and etching the regions except the first region on the epitaxial wafer with the isolation region by taking the second dielectric layer as a mask to obtain a second epitaxial wafer.
Further, the step of processing the second epitaxial wafer with the first dielectric layer to obtain the semiconductor device includes: forming a first metal layer on the epitaxial wafer with the first dielectric layer; removing the first metal layer, the first dielectric layer and the second dielectric layer which are covered on the first area; and depositing a second metal layer at the appointed position of the first region to obtain the semiconductor device.
Further, the step of removing the first metal layer, the first dielectric layer and the second dielectric layer covered on the first region includes: stripping the first metal layer covered on the first area; and removing the first dielectric layer and the second dielectric layer which are covered on the first area by adopting a wet etching mode.
Further, the material of the second dielectric layer includes silicon nitride or silicon dioxide.
The invention provides a semiconductor device and a method for manufacturing the semiconductor device, wherein the semiconductor device comprises: the semiconductor device comprises a first epitaxial wafer with a first groove and a second groove, a first dielectric layer, a grid electrode arranged on the upper surface of the first epitaxial wafer, a source electrode arranged in the first groove and a drain electrode arranged in the second groove; the source electrode and the drain electrode are arranged on two sides of the grid electrode; the first epitaxial wafer comprises a two-dimensional electron gas structure layer; the first dielectric layer is deposited in the first groove and the second groove, and the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structural layer; a first metal layer is deposited on the first dielectric layer in the first groove and the second groove to form a source electrode and a drain electrode; the grid electrode is formed by depositing a second metal layer at a designated position on the upper surface of the first epitaxial wafer. According to the semiconductor device, the first dielectric layers with low dielectric constants are filled below the metal layers corresponding to the drain electrode and the source electrode respectively, the depth of the first dielectric layers is lower than that of the two-dimensional electron gas structural layer, and parasitic capacitance effect generated by mutual coupling among the grid electrode, the source electrode and the drain electrode can be reduced by the structural form, so that the working frequency of the device can be improved, and the manufacturing cost of the device can be controlled while the yield and the reliability of the device are ensured due to the fact that the grid length does not need to be changed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an initial epitaxial wafer according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an epitaxial wafer with an isolation region according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an epitaxial wafer according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another epitaxial wafer according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another epitaxial wafer according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of another epitaxial wafer according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of another epitaxial wafer according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention.
Icon: 10-a first epitaxial wafer; 11-a first dielectric layer; 12-a two-dimensional electron gas structural layer; 13-a first metal layer; 14-a second metal layer; 15-isolation regions; 16-a second dielectric layer.
Detailed Description
The technical solutions of the present invention will be clearly and completely described in connection with the embodiments, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
At present, HEMT devices are widely applied to design and manufacture of power amplifiers and low noise amplifier circuits, are important devices of modern microwave design integrated circuits, and as communication technology enters into the 5g,6g and even terahertz communication age, carrier frequency is increased, so that the working frequency of HEMTs is required to be increased. In the related art, in order to increase the operating frequency of the HEMT, the most commonly adopted method is to reduce the gate length, but the reduction of the gate length can cause significant increase of the cost of the HEMT, meanwhile, the yield and the reliability can also be drastically reduced, in addition, the material system of the HEMT can also be greatly changed, so that the incompatibility problem with the existing technology occurs. Based on the above, the embodiment of the invention provides a semiconductor device and a manufacturing method of the semiconductor device, and the technology can be applied to the application needing to improve the working frequency of the semiconductor.
For the sake of understanding the present embodiment, first, a description will be given of a semiconductor device disclosed in an embodiment of the present invention, referring to a schematic structural diagram of a semiconductor device shown in fig. 1, where fig. 1 (b) is a cross-sectional view of fig. 1 (a), and the semiconductor device includes: the semiconductor device comprises a first epitaxial wafer 10 with a first groove and a second groove, a first dielectric layer 11 with a low dielectric constant, a grid electrode arranged on the upper surface of the first epitaxial wafer 10, a source electrode arranged in the first groove and a drain electrode arranged in the second groove; the source electrode and the drain electrode are arranged on two sides of the grid electrode; the first epitaxial wafer 10 includes a two-dimensional electron gas structural layer 12 therein.
The first epitaxial wafer 10 may be understood as a silicon wafer with an epitaxial layer formed on a substrate, where the first epitaxial wafer 10 includes a two-dimensional electron gas structural layer 12, and the two-dimensional electron gas structural layer 12 is a structural layer with a certain depth and is generally close to the upper surface of the first epitaxial wafer 10, where the two-dimensional electron gas may be understood as a system with a low electron density, in which the movement of an electron group in one direction is limited to a small range and free movement in the other two directions is limited by using physical methods such as quantum confinement; the first groove and the second groove can be obtained by adopting an etching process; the first dielectric layer 11 is usually a low-k dielectric such as silicon nitride or silicon dioxide; the semiconductor device generally includes a gate electrode generally disposed in an intermediate region of the upper surface of the first epitaxial wafer 10, a source electrode and a drain electrode disposed at positions corresponding to the first recess and the second recess, respectively, as in fig. 1, the gate electrode may be disposed in an intermediate region of the source electrode and the drain electrode.
The first dielectric layer 11 is deposited in the first groove and the second groove, and the upper surface of the first dielectric layer 11 is lower than the lower surface of the two-dimensional electron gas structure layer 12; a first metal layer 13 is deposited on the first dielectric layer 11 in the first groove and the second groove to form a source electrode and a drain electrode; the gate electrode is formed by deposition of a second metal layer 14 at a designated location on the upper surface of the first epitaxial wafer 10.
In the semiconductor device, the first dielectric layer 11 is deposited in the first groove and the second groove respectively, the thickness of the first dielectric layer 11 in the two grooves can be the same, the upper surface of the first dielectric layer 11 in the two grooves must be lower than the lower surface of the two-dimensional electron gas structural layer 12, the first metal layer 13 is deposited on the first dielectric layer 11 in the two grooves respectively, the thickness of the first metal layer 13 deposited in the two grooves can be the same, and the depth of the first dielectric layer 11 in the two grooves is lower than the depth of the two-dimensional electron gas structural layer 12, so that the first metal layer 13 deposited in the two grooves can be connected with the two-dimensional electron gas structural layer 12, the conduction path between a drain electrode and a source electrode is prevented from being cut off, the second metal layer 14 is deposited at a designated position on the upper surface of the first epitaxial wafer 10, for example, in fig. 1, the second metal layer 14 is deposited at a part of the area between the two grooves of the first epitaxial wafer 10, and the grid electrode of the semiconductor device is formed.
The semiconductor device includes: the semiconductor device comprises a first epitaxial wafer with a first groove and a second groove, a first dielectric layer with a low dielectric constant, a grid electrode arranged on the upper surface of the first epitaxial wafer, a source electrode arranged in the first groove and a drain electrode arranged in the second groove; the source electrode and the drain electrode are arranged on two sides of the grid electrode; the first epitaxial wafer comprises a two-dimensional electron gas structure layer; the first dielectric layer is deposited in the first groove and the second groove, and the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structural layer; a first metal layer is deposited on the first dielectric layer in the first groove and the second groove to form a source electrode and a drain electrode; the grid electrode is formed by depositing a second metal layer at a designated position on the upper surface of the first epitaxial wafer. According to the semiconductor device, the first dielectric layers with low dielectric constants are filled below the metal layers corresponding to the drain electrode and the source electrode respectively, the depth of the first dielectric layers is lower than that of the two-dimensional electron gas structural layer, and parasitic capacitance effect generated by mutual coupling among the grid electrode, the source electrode and the drain electrode can be reduced by the structural form, so that the working frequency of the device can be improved, and the manufacturing cost of the device can be controlled while the yield and the reliability of the device are ensured due to the fact that the grid length does not need to be changed.
Further, the upper surfaces of the first metal layers in the first groove and the second groove are higher than the upper surface of the first epitaxial wafer. In practical implementation, the first metal layers in the first groove and the second groove are usually formed by anisotropic deposition, the upper surfaces of the first metal layers deposited in the two grooves usually exceed the upper surface of the first epitaxial wafer, and the thickness of the first metal layers is generally 20nm-500nm, so that the corresponding areas of the source electrode and the drain electrode can be protruded, and the subsequent process operation flow is more convenient.
Further, the side surfaces of the first metal layer in the first groove and the second groove are communicated with the two-dimensional electron gas structural layer. After depositing the first metal layer in the first groove and the second groove of the first epitaxial wafer, it is required to ensure that each side surface of the first metal layer is communicated with the two-dimensional electron gas structure layer in the two grooves so as to form ohmic contact of the source electrode and the drain electrode.
Further, the preset edge area of the first epitaxial wafer is provided with an isolation area 15. The forming process of the isolation region 15 may be a conventional method, for example, an ion implantation method is used to form the isolation region 15, or a mesa etching method is used to form the isolation region 15; the depth of the isolation region 15 generally needs to be greater than the depth of the two-dimensional electron gas structural layer, i.e., the lower surface of the isolation region 15 needs to be lower than the lower surface of the two-dimensional electron gas structural layer; the isolation region 15 may be used to reduce leakage of the semiconductor device; the edge preset region is generally a designated region of the edge of the first epitaxial wafer.
Further, the material of the first dielectric layer includes silicon nitride or silicon dioxide. In practical implementation, the first dielectric layers in the first groove and the second groove are usually formed by anisotropic deposition, the thickness of the first dielectric layer is generally 20nm-500nm, the first dielectric layer is usually a low dielectric constant dielectric, for example, silicon nitride, silicon dioxide, etc., and of course, other low dielectric constant dielectrics can be selected according to practical requirements.
The embodiment of the invention also provides a manufacturing method of the semiconductor device, as shown in fig. 2, comprising the following steps:
step S202, obtaining a second epitaxial wafer; the second epitaxial wafer is provided with a first groove and a second groove, and a second dielectric layer is deposited on a first area except the first groove and the second groove on the upper surface of the second epitaxial wafer; the second epitaxial wafer comprises a two-dimensional electron gas structure layer.
The material of the second dielectric layer may be the same as or different from that of the first dielectric layer, and when the semiconductor device is to be fabricated in actual implementation, it is generally necessary to obtain a second epitaxial wafer first, where the second epitaxial wafer includes a two-dimensional electron gas structure layer, the two-dimensional electron gas structure layer is usually a structure layer having a certain depth and being close to the upper surface of the second epitaxial wafer, and a second dielectric layer is deposited on an area of the upper surface of the second epitaxial wafer except for the first groove and the second groove, where the thickness of the second dielectric layer is generally 20nm-500nm, and specifically, a suitable bonding thickness can be selected according to actual requirements.
Step S204, depositing a first dielectric layer with low dielectric constant on the second epitaxial wafer; the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structural layer in the first groove and the second groove.
After the second epitaxial wafer is obtained, the first dielectric layer may be deposited on the second epitaxial wafer, where the first dielectric layer is usually a low dielectric constant dielectric, for example, may be silicon nitride or silicon dioxide; specifically, the first dielectric layer is deposited on the upper surface of the second epitaxial wafer, including the upper surfaces of the first groove and the second groove, wherein after the first dielectric layer is deposited in the two grooves, the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structural layer; the thickness of the first dielectric layer is generally 20nm-50nm, and particularly, a proper thickness can be selected according to actual requirements.
And S206, processing the second epitaxial wafer with the first dielectric layer to obtain the semiconductor device.
After the second epitaxial wafer with the first dielectric layer deposited thereon is obtained, the second epitaxial wafer is processed, for example, a metal layer is deposited, the first dielectric layer, the second dielectric layer and the like are etched by a wet method, so as to obtain the semiconductor device, the semiconductor device generally comprises a gate electrode, a source electrode and a drain electrode, the positions of the first groove and the second groove are generally set as the source electrode and the drain electrode of the semiconductor device, and the gate electrode of the semiconductor device is formed in a part of the region between the first groove and the second groove.
The manufacturing method of the semiconductor device comprises the steps of firstly obtaining a second epitaxial wafer; the second epitaxial wafer is provided with a first groove and a second groove, and a second dielectric layer is deposited on a first area except the first groove and the second groove on the upper surface of the second epitaxial wafer; the second epitaxial wafer comprises a two-dimensional electron gas structure layer. Depositing a first dielectric layer with low dielectric constant on the second epitaxial wafer; the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structural layer in the first groove and the second groove. And processing the second epitaxial wafer with the first dielectric layer to obtain the semiconductor device. In the mode, the first grooves and the second grooves of the second epitaxial wafer are respectively filled with the first dielectric layer with low dielectric constant, and the depth of the first dielectric layer is lower than that of the two-dimensional electron gas structure layer, so that parasitic capacitance effect generated by mutual coupling between the poles of the semiconductor device can be reduced, and the working frequency of the semiconductor device can be further improved. The structure does not need to change the gate length, so that the manufacturing cost of the semiconductor device can be controlled, and the yield and the reliability of the semiconductor device can be ensured.
The embodiment of the invention also provides another method for manufacturing a semiconductor device, which is realized on the basis of the method of the embodiment, and the method mainly describes a determination mode of the second epitaxial wafer and a specific process of processing the second epitaxial wafer with the first dielectric layer to obtain the semiconductor device, as shown in fig. 3, and comprises the following steps:
step S302, obtaining a second epitaxial wafer; the second epitaxial wafer is provided with a first groove and a second groove, and a second dielectric layer is deposited on a first area except the first groove and the second groove on the upper surface of the second epitaxial wafer; the second epitaxial wafer comprises a two-dimensional electron gas structure layer.
The second epitaxial wafer is obtained by the following steps:
forming an isolation region in a preset region of the edge of a pre-obtained initial epitaxial wafer to obtain an epitaxial wafer with the isolation region; the initial epitaxial wafer comprises a two-dimensional electron gas structure layer; the lower surface of the isolation region is lower than the lower surface of the two-dimensional electron gas structure layer.
Referring to fig. 4, wherein fig. 4 (b) is a schematic structural diagram of an initial epitaxial wafer, and as can be seen from fig. 4 (a), the initial epitaxial wafer is usually an original epitaxial wafer which is not subjected to etching, deposition, etc., and includes a two-dimensional electron gas structural layer, which is usually a structural layer with a certain depth and is close to the upper surface of the initial epitaxial wafer; referring to a schematic structural diagram of an epitaxial wafer with an isolation region shown in fig. 5, where fig. 5 (b) is a cross-sectional view of fig. 5 (a), the isolation region may be formed by using an ion implantation method in a preset region at an edge of an obtained initial epitaxial wafer, or may be formed by using a mesa etching method to obtain an epitaxial wafer with an isolation region; the depth of the isolation region formed is typically required to be greater than the depth of the two-dimensional electron gas structural layer, i.e., the lower surface of the isolation region is lower than the lower surface of the two-dimensional electron gas structural layer.
And step two, depositing a second dielectric layer on the first area of the upper surface of the epitaxial wafer with the isolation area.
The first region is usually a region except for a source electrode and a drain electrode, which need to be etched on the epitaxial wafer with the isolation region; referring to a schematic structural diagram of an epitaxial wafer shown in fig. 6, where fig. 6 (b) is a cross-sectional view of fig. 6 (a), in actual implementation, after the epitaxial wafer with the isolation region is obtained, a second dielectric layer 16 may be deposited on the first region on the upper surface of the epitaxial wafer with the isolation region, where the thickness of the second dielectric layer is generally 20nm-500nm, and the material of the second dielectric layer may include silicon nitride, silicon dioxide, or other dielectrics may be selected according to actual requirements.
And thirdly, etching the regions except the first region on the epitaxial wafer with the isolation region by taking the second dielectric layer as a mask to obtain a second epitaxial wafer.
Selecting and etching the epitaxial wafer with the isolation region by using the second dielectric layer as a mask, specifically, etching the region, except the first region, of the epitaxial wafer with the isolation region to an etching depth of 20-500 nm; the first recess and the second recess may be etched, referring to a schematic structural diagram of another epitaxial wafer shown in fig. 7, where fig. 7 (b) is a cross-sectional view of fig. 7 (a), in which a source electrode and a drain electrode of a semiconductor device may be disposed in the first recess and the second recess, and the second epitaxial wafer may be obtained after etching treatment.
Step S304, depositing a first dielectric layer on the second epitaxial wafer; the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structural layer in the first groove and the second groove.
Referring to fig. 8, wherein fig. 8 (b) is a cross-sectional view of fig. 8 (a), the first dielectric layer is deposited on the upper surface of the second epitaxial wafer, including the upper surfaces of the first recess and the second recess, wherein after the first dielectric layer is deposited in the two recesses, the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structural layer; the thickness of the first dielectric layer is generally 20nm-50nm, and particularly, a proper thickness can be selected according to actual requirements.
In step S306, a first metal layer is formed on the epitaxial wafer with the first dielectric layer.
A first metal layer is anisotropically deposited on the epitaxial wafer with the first dielectric layer, specifically, referring to the schematic structural diagram of another epitaxial wafer shown in fig. 9, where fig. 9 (b) is a cross-sectional view of fig. 9 (a), and the first metal layer needs to be deposited in both a first area and an etched area, where the upper surface of the deposited first metal layer in the etched area needs to be higher than the upper surface of the epitaxial wafer, and each side is to be communicated with a two-dimensional electron gas structural layer, and the thickness of the deposited first metal layer is typically 20nm-500nm for forming source and drain ohmic contacts.
Step S308, removing the first metal layer, the first dielectric layer and the second dielectric layer which are covered on the first area.
Specifically, this step S308 may be implemented by the following steps six and seven:
and step six, stripping the first metal layer covered on the first area.
After the first metal layer is formed on the epitaxial wafer with the first dielectric layer, the first metal layer correspondingly covered on the first area needs to be stripped, and the metal stripping process in the prior art can be referred to for specific details, which are not described herein again.
And seventhly, removing the first dielectric layer and the second dielectric layer which are covered on the first area in a wet etching mode.
The wet etching is understood to mean etching by placing the wafer in a liquid chemical etching solution, during which the etching solution will gradually etch away the material with which it is in contact by chemical reaction. In actual implementation, after the first metal layer covered on the first area is stripped, the first dielectric layer and the second dielectric layer correspondingly covered on the first area need to be removed continuously, and the process can be performed in a wet etching manner, and specifically, reference may be made to a wet etching process in the prior art, and details are not repeated here; referring to fig. 10, fig. 10 (b) is a cross-sectional view of fig. 10 (a), and it can be seen that the first metal layer, the first dielectric layer, and the second dielectric layer, which are covered on the first region, have been removed.
And step S310, depositing a second metal layer at the appointed position of the first area to obtain the semiconductor device.
The designated location is generally the middle area of the first area, for example, as shown in the schematic structural diagram of a semiconductor device in fig. 1, the second metal layer may be deposited on the upper surface of the first area and located in the middle position of the first groove and the second groove, so as to form the gate metal, and finally the semiconductor device is obtained.
Referring to the schematic structure of another semiconductor device shown in fig. 11, a conventional HEMT device is taken as an example for explanation, in the HEMT device, three parasitic capacitance effects, that is, cds, cgs and Cgd, mainly exist, and by adopting the semiconductor device manufacturing method in the application to improve the structure of the HEMT device, the three parasitic capacitance effects can be weakened, so that the working frequency of the device can be improved.
According to the manufacturing method of the semiconductor device, under the conditions that the gate length is not changed, the epitaxial wafer structure is not changed, and the process difficulty is not obviously increased, parasitic capacitance effects generated by mutual coupling among the gate, the source and the drain electrodes are reduced by a method of filling low dielectric constant (low K) medium under the source and the drain metals, so that the purpose of improving the working frequency of the device is achieved; the technology has strong compatibility with the existing HEMT technology, has strong applicability, and can solve the problem that the working frequency of HEMT devices is limited by parasitic capacitance effect.
The block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and computer program products according to various embodiments of the present invention. In this regard, each block in the block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams, and combinations of blocks in the block diagrams, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, in the description of embodiments of the present invention, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The relative numerical expressions and numerical values of the components set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
Any particular values in all examples shown and described herein are to be construed as merely illustrative and not a limitation, and thus other examples of exemplary embodiments may have different values.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments provided in the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (9)

1. A semiconductor device, comprising: the semiconductor device comprises a first epitaxial wafer with a first groove and a second groove, a first dielectric layer with a low dielectric constant, a grid electrode arranged on the upper surface of the first epitaxial wafer, a source electrode arranged in the first groove and a drain electrode arranged in the second groove; wherein the source electrode and the drain electrode are arranged at two sides of the grid electrode; the first epitaxial wafer comprises a two-dimensional electron gas structure layer;
the first dielectric layer is deposited in the first groove and the second groove, and the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer; a first metal layer is deposited on the first dielectric layer in the first groove and the second groove, and the source electrode and the drain electrode are formed; wherein the first dielectric layer is in direct contact with the first metal layer;
the grid electrode is formed by depositing a second metal layer at a designated position on the upper surface of the first epitaxial wafer.
2. The semiconductor device of claim 1, wherein an upper surface of the first metal layer in the first recess and the second recess is higher than an upper surface of the first epitaxial wafer.
3. The semiconductor device of claim 1, wherein sides of the first metal layer within the first recess and the second recess are each in communication with the two-dimensional electron gas structural layer.
4. The semiconductor device of claim 1, wherein the edge pre-set region of the first epitaxial wafer has an isolation region.
5. The semiconductor device of claim 1, wherein the material of the first dielectric layer comprises silicon nitride or silicon dioxide.
6. A method of fabricating a semiconductor device, the method comprising:
obtaining a second epitaxial wafer; the second epitaxial wafer is provided with a first groove and a second groove, and a second dielectric layer is deposited on a first area of the upper surface of the second epitaxial wafer except the first groove and the second groove; the second epitaxial wafer comprises a two-dimensional electron gas structure layer;
depositing a first dielectric layer with low dielectric constant on the second epitaxial wafer; wherein, in the first groove and the second groove, the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer;
processing the second epitaxial wafer with the first dielectric layer to obtain a semiconductor device;
the step of processing the second epitaxial wafer with the first dielectric layer to obtain the semiconductor device comprises the following steps:
forming a first metal layer on the epitaxial wafer with the first dielectric layer; the first dielectric layer in the first groove and the second groove is in direct contact with the first metal layer, so that a source electrode and a drain electrode are formed;
removing the first metal layer, the first dielectric layer and the second dielectric layer which are covered on the first area;
and depositing a second metal layer at the appointed position of the first region to form a grid electrode, thereby obtaining the semiconductor device.
7. The method of claim 6, wherein the second epitaxial wafer is obtained by:
forming an isolation region in a preset region at the edge of the initial epitaxial wafer obtained in advance to obtain an epitaxial wafer with the isolation region; wherein the initial epitaxial wafer comprises the two-dimensional electron gas structure layer; the lower surface of the isolation region is lower than the lower surface of the two-dimensional electron gas structure layer;
depositing a second dielectric layer on the first area of the upper surface of the epitaxial wafer with the isolation area;
and etching the regions, except the first region, of the epitaxial wafer with the isolation region by taking the second dielectric layer as a mask to obtain the second epitaxial wafer.
8. The method of claim 6, wherein the step of removing the first metal layer, the first dielectric layer, and the second dielectric layer overlying the first region comprises:
stripping the first metal layer covered on the first area;
and removing the first dielectric layer and the second dielectric layer which are covered on the first area in a wet etching mode.
9. The method of claim 6, wherein the material of the second dielectric layer comprises silicon nitride or silicon dioxide.
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