CN113451394A - Semiconductor device and semiconductor device manufacturing method - Google Patents
Semiconductor device and semiconductor device manufacturing method Download PDFInfo
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- CN113451394A CN113451394A CN202110737105.5A CN202110737105A CN113451394A CN 113451394 A CN113451394 A CN 113451394A CN 202110737105 A CN202110737105 A CN 202110737105A CN 113451394 A CN113451394 A CN 113451394A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 60
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 37
- 238000000151 deposition Methods 0.000 claims abstract description 29
- 238000002955 isolation Methods 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000004891 communication Methods 0.000 claims description 8
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- 238000010586 diagram Methods 0.000 description 21
- 230000008569 process Effects 0.000 description 11
- 238000013461 design Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, wherein the device comprises: the device comprises a first epitaxial wafer with two grooves and a first dielectric layer, wherein the first epitaxial wafer comprises a two-dimensional electron gas structure layer; the first dielectric layer is deposited in the two grooves, and the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electronic gas structure layer; depositing a first metal layer on the first dielectric layer in the two grooves to form a source electrode and a drain electrode; the grid electrode is formed by depositing a second metal layer at a designated position on the upper surface of the first epitaxial wafer. According to the semiconductor device, the first dielectric layer with a low dielectric constant is filled below the metal layers corresponding to the drain electrode and the source electrode respectively, the depth of the first dielectric layer is lower than that of the two-dimensional electronic gas structure layer, the parasitic capacitance effect generated by mutual coupling among the grid electrode, the source electrode and the drain electrode can be reduced through the structural form, the working frequency of the device can be further improved, and the yield and the reliability of the device can be guaranteed while the manufacturing cost of the device is controlled due to the fact that the length of the grid electrode does not need to be changed.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method of the semiconductor device.
Background
HEMTs (High Electron Mobility transistors) are widely used in the design and manufacture of circuits such as power amplifiers, low noise amplifiers and the like, and are important devices of modern microwave design integrated circuits; as the Communication Technology enters 5G (5G for short) and 6G (6G for short), even in the terahertz Communication era, the carrier frequency is increased, which requires the operating frequency of the HEMT to be increased; in the related art, in order to improve the operating frequency of the HEMT, a method is generally adopted to reduce the gate length of the HEMT, that is, to reduce the width of the gate, but the reduction of the gate length significantly increases the cost of the HEMT, and meanwhile, the yield and reliability are also affected.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method of the semiconductor device, so as to improve the working frequency of a HEMT.
The invention provides a semiconductor device, comprising: the device comprises a first epitaxial wafer with a first groove and a second groove, a first dielectric layer with a low dielectric constant, a grid electrode arranged on the upper surface of the first epitaxial wafer, a source electrode arranged in the first groove and a drain electrode arranged in the second groove; the source electrode and the drain electrode are arranged on two sides of the grid electrode; the first epitaxial wafer comprises a two-dimensional electron gas structure layer; the first dielectric layer is deposited in the first groove and the second groove, and the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer; depositing a first metal layer on the first dielectric layer in the first groove and the second groove to form a source electrode and a drain electrode; the grid electrode is formed by depositing a second metal layer at a designated position on the upper surface of the first epitaxial wafer.
Further, the upper surface of the first metal layer in the first groove and the second groove is higher than the upper surface of the first epitaxial wafer.
Furthermore, the side surfaces of the first metal layer in the first groove and the second groove are communicated with the two-dimensional electron gas structure layer.
Furthermore, the edge preset area of the first epitaxial wafer is provided with an isolation area.
Furthermore, the material of the first dielectric layer includes silicon nitride or silicon dioxide.
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: obtaining a second epitaxial wafer; the second epitaxial wafer is provided with a first groove and a second groove, and a second dielectric layer is deposited in a first area of the upper surface of the second epitaxial wafer except the first groove and the second groove; the second epitaxial wafer comprises a two-dimensional electron gas structure layer; depositing a first dielectric layer with a low dielectric constant on the second epitaxial wafer; in the first groove and the second groove, the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer; and processing the second epitaxial wafer with the first dielectric layer to obtain the semiconductor device.
Further, the second epitaxial wafer is obtained by: forming an isolation region in a preset region at the edge of the initial epitaxial wafer obtained in advance to obtain an epitaxial wafer with the isolation region; the initial epitaxial wafer comprises a two-dimensional electronic gas structure layer; the lower surface of the isolation region is lower than the lower surface of the two-dimensional electron gas structure layer; depositing a second dielectric layer on the first area of the upper surface of the epitaxial wafer with the isolation area; and etching the regions except the first region on the epitaxial wafer with the isolation region by taking the second dielectric layer as a mask to obtain a second epitaxial wafer.
Further, the step of processing the second epitaxial wafer with the first dielectric layer to obtain the semiconductor device comprises: forming a first metal layer on the epitaxial wafer with the first dielectric layer; removing the first metal layer, the first dielectric layer and the second dielectric layer which cover the first area; and depositing a second metal layer at the designated position of the first area to obtain the semiconductor device.
Further, the step of removing the first metal layer, the first dielectric layer and the second dielectric layer covering the first region includes: stripping the first metal layer covered on the first area; and removing the first dielectric layer and the second dielectric layer which cover the first region by adopting a wet etching mode.
Furthermore, the material of the second dielectric layer includes silicon nitride or silicon dioxide.
The invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: the device comprises a first epitaxial wafer with a first groove and a second groove, a first dielectric layer, a grid electrode arranged on the upper surface of the first epitaxial wafer, a source electrode arranged in the first groove, and a drain electrode arranged in the second groove; the source electrode and the drain electrode are arranged on two sides of the grid electrode; the first epitaxial wafer comprises a two-dimensional electron gas structure layer; the first dielectric layer is deposited in the first groove and the second groove, and the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer; depositing a first metal layer on the first dielectric layer in the first groove and the second groove to form a source electrode and a drain electrode; the grid electrode is formed by depositing a second metal layer at a designated position on the upper surface of the first epitaxial wafer. According to the semiconductor device, the first dielectric layer with a low dielectric constant is filled below the metal layers corresponding to the drain electrode and the source electrode respectively, the depth of the first dielectric layer is lower than that of the two-dimensional electronic gas structure layer, the parasitic capacitance effect generated by mutual coupling among the grid electrode, the source electrode and the drain electrode can be reduced through the structural form, the working frequency of the device can be further improved, and the yield and the reliability of the device can be guaranteed while the manufacturing cost of the device is controlled due to the fact that the length of the grid electrode does not need to be changed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a flow chart of another method for fabricating a semiconductor device according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an initial epitaxial wafer according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an epitaxial wafer with an isolation region according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an epitaxial wafer according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another epitaxial wafer according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another epitaxial wafer according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of another epitaxial wafer according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of another epitaxial wafer according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention.
Icon: 10-a first epitaxial wafer; 11-a first dielectric layer; 12-a two-dimensional electron gas structure layer; 13-a first metal layer; 14-a second metal layer; 15-isolation regions; 16-second dielectric layer.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
At present, HEMT devices are widely applied to design and manufacture of power amplifiers and low-noise amplifier circuits, are important devices of modern microwave design integrated circuits, and as communication technology enters 5G and 6G, even in the terahertz communication era, carrier frequency is increased, so that the working frequency of HEMT is required to be increased. In the related art, in order to improve the operating frequency of the HEMT, the gate length is most often reduced, but the reduction of the gate length causes the cost of the HEMT to be significantly increased, the yield and the reliability to be sharply reduced, and in addition, the material system of the HEMT is greatly changed, so that the HEMT is incompatible with the existing process. Based on this, the embodiments of the present invention provide a semiconductor device and a method for manufacturing the semiconductor device, which can be applied to applications requiring an increase in the operating frequency of the semiconductor device.
To facilitate understanding of the present embodiment, a semiconductor device disclosed in the present embodiment is first described, referring to a schematic structural diagram of a semiconductor device shown in fig. 1, wherein fig. 1(b) is a cross-sectional view of fig. 1(a), the semiconductor device includes: the structure comprises a first epitaxial wafer 10 with a first groove and a second groove, a first dielectric layer 11 with a low dielectric constant, a grid electrode arranged on the upper surface of the first epitaxial wafer 10, a source electrode arranged in the first groove, and a drain electrode arranged in the second groove; the source electrode and the drain electrode are arranged on two sides of the grid electrode; the first epitaxial wafer 10 includes a two-dimensional electron gas structure layer 12 therein.
The first epitaxial wafer 10 may be understood as a silicon wafer with an epitaxial layer formed on a substrate, where the first epitaxial wafer 10 includes a two-dimensional electron gas structure layer 12, and the two-dimensional electron gas structure layer 12 is usually a structure layer with a certain depth and close to the upper surface of the first epitaxial wafer 10, where the two-dimensional electron gas may be understood as a system with a low electron density, which uses physical methods such as quantum confinement to limit the movement of an electron group in one direction to a small range and can move freely in the other two directions; the first groove and the second groove can be obtained by adopting an etching process; the first dielectric layer 11 is usually a dielectric with a low dielectric constant, such as silicon nitride or silicon dioxide; the semiconductor device generally includes a gate electrode, a source electrode and a drain electrode, wherein the gate electrode is generally disposed in a middle region of an upper surface of the first epitaxial wafer 10, and the source electrode and the drain electrode are respectively disposed at positions corresponding to the first recess and the second recess, and as shown in fig. 1, the gate electrode may be disposed in a middle region of the source electrode and the drain electrode.
The first dielectric layer 11 is deposited in the first groove and the second groove, and the upper surface of the first dielectric layer 11 is lower than the lower surface of the two-dimensional electronic gas structure layer 12; depositing a first metal layer 13 on the first dielectric layer 11 in the first groove and the second groove to form a source electrode and a drain electrode; the gate is formed by depositing a second metal layer 14 at a designated location on the upper surface of the first epitaxial wafer 10.
In the semiconductor device, the first dielectric layers 11 are respectively deposited in the first groove and the second groove, the thickness of the first dielectric layers 11 in the two grooves can be the same, and the upper surface of the first dielectric layers 11 in the two grooves must be lower than the lower surface of the two-dimensional electronic gas structure layer 12, the first metal layers 13 are respectively deposited on the first dielectric layers 11 in the two grooves, the thickness of the first metal layers 13 deposited in the two grooves can be the same, because the depth of the first dielectric layers 11 in the two grooves is lower than the depth of the two-dimensional electronic gas structure layer 12, the first metal layers 13 deposited in the two grooves can be ensured to be connected with the two-dimensional electronic gas structure layer 12, the conductive path between the drain and the source is prevented from being cut off, the second metal layer 14 is deposited at the designated position of the upper surface of the first epitaxial wafer 10, for example, in fig. 1, the second metal layer 14 is deposited in a part of the area between the two grooves of the first epitaxial wafer 10, forming a gate of the semiconductor device.
The semiconductor device includes: the device comprises a first epitaxial wafer with a first groove and a second groove, a first dielectric layer with a low dielectric constant, a grid electrode arranged on the upper surface of the first epitaxial wafer, a source electrode arranged in the first groove and a drain electrode arranged in the second groove; the source electrode and the drain electrode are arranged on two sides of the grid electrode; the first epitaxial wafer comprises a two-dimensional electron gas structure layer; the first dielectric layer is deposited in the first groove and the second groove, and the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer; depositing a first metal layer on the first dielectric layer in the first groove and the second groove to form a source electrode and a drain electrode; the grid electrode is formed by depositing a second metal layer at a designated position on the upper surface of the first epitaxial wafer. According to the semiconductor device, the first dielectric layer with a low dielectric constant is filled below the metal layers corresponding to the drain electrode and the source electrode respectively, the depth of the first dielectric layer is lower than that of the two-dimensional electronic gas structure layer, the parasitic capacitance effect generated by mutual coupling among the grid electrode, the source electrode and the drain electrode can be reduced through the structural form, the working frequency of the device can be further improved, and the yield and the reliability of the device can be guaranteed while the manufacturing cost of the device is controlled due to the fact that the length of the grid electrode does not need to be changed.
Further, the upper surface of the first metal layer in the first groove and the second groove is higher than the upper surface of the first epitaxial wafer. In practical implementation, the first metal layer in the first recess and the second recess is usually formed by anisotropic deposition, the upper surface of the first metal layer deposited in the two recesses usually exceeds the upper surface of the first epitaxial wafer, and the thickness of the first metal layer is usually 20nm to 500nm, so that the regions corresponding to the source and the drain respectively can be protruded, which is more convenient for the subsequent process operation flow.
Furthermore, the side surfaces of the first metal layer in the first groove and the second groove are communicated with the two-dimensional electron gas structure layer. After depositing the first metal layer in the first groove and the second groove of the first epitaxial wafer, it is necessary to ensure that each side surface of the first metal layer in the two grooves is communicated with the two-dimensional electron gas structure layer to form ohmic contacts of the source electrode and the drain electrode.
Further, the edge of the first epitaxial wafer is provided with an isolation region 15. The isolation region 15 may be formed by a method in the prior art, for example, by ion implantation, or by mesa etching to form the isolation region 15; the depth of the isolation region 15 generally needs to be greater than the depth of the two-dimensional electron gas structure layer, that is, the lower surface of the isolation region 15 needs to be lower than the lower surface of the two-dimensional electron gas structure layer; the isolation region 15 may be used to reduce leakage of the semiconductor device; the edge presetting region is generally a designated region of the edge of the first epitaxial wafer.
Furthermore, the material of the first dielectric layer includes silicon nitride or silicon dioxide. In practical implementation, the first dielectric layer in the first recess and the second recess is usually formed by anisotropic deposition, the thickness of the first dielectric layer is usually 20nm to 500nm, the first dielectric layer is usually selected from a low-dielectric-constant dielectric, such as silicon nitride, silicon dioxide, etc., although other low-dielectric-constant dielectrics may also be selected according to practical requirements.
An embodiment of the present invention further provides a method for manufacturing a semiconductor device, as shown in fig. 2, the method includes the following steps:
step S202, acquiring a second epitaxial wafer; the second epitaxial wafer is provided with a first groove and a second groove, and a second dielectric layer is deposited in a first area of the upper surface of the second epitaxial wafer except the first groove and the second groove; the second epitaxial wafer comprises a two-dimensional electron gas structure layer.
The material of the second dielectric layer may be the same as or different from the material of the first dielectric layer, and in actual implementation, when the semiconductor device needs to be manufactured, the second epitaxial wafer generally needs to be obtained first, the second epitaxial wafer includes a two-dimensional electronic gas structure layer, the two-dimensional electronic gas structure layer is generally a structure layer which is close to the upper surface of the second epitaxial wafer and has a certain depth, the second dielectric layer is deposited on the upper surface of the second epitaxial wafer except for the first groove and the second groove, the thickness of the second dielectric layer is generally 20nm-500nm, and a proper combination thickness can be specifically selected according to actual requirements.
Step S204, depositing a first dielectric layer with a low dielectric constant on the second epitaxial wafer; and in the first groove and the second groove, the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer.
After the second epitaxial wafer is obtained, the first dielectric layer may be deposited on the second epitaxial wafer, where the first dielectric layer is usually a dielectric with a low dielectric constant, such as silicon nitride or silicon dioxide; specifically, the first dielectric layers are deposited on the upper surfaces of the second epitaxial wafer, including the upper surfaces of the first groove and the second groove, wherein after the first dielectric layers are deposited in the two grooves, the upper surface of each first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer; the thickness of the first dielectric layer is generally 20nm-50nm, and the appropriate thickness can be selected according to actual requirements.
And step S206, processing the second epitaxial wafer with the first dielectric layer to obtain the semiconductor device.
After obtaining the second epitaxial wafer deposited with the first dielectric layer, processing the second epitaxial wafer, for example, depositing a metal layer, wet etching the first dielectric layer, the second dielectric layer, and the like, to obtain the semiconductor device, where the semiconductor device generally includes a gate, a source, and a drain, the positions of the first recess and the second recess are generally set as the source and the drain of the semiconductor device, respectively, and the gate of the semiconductor device is formed in a part of the region between the first recess and the second recess.
The manufacturing method of the semiconductor device comprises the steps of firstly, obtaining a second epitaxial wafer; the second epitaxial wafer is provided with a first groove and a second groove, and a second dielectric layer is deposited in a first area of the upper surface of the second epitaxial wafer except the first groove and the second groove; the second epitaxial wafer comprises a two-dimensional electron gas structure layer. Depositing a first dielectric layer with a low dielectric constant on the second epitaxial wafer; and in the first groove and the second groove, the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer. And processing the second epitaxial wafer with the first dielectric layer to obtain the semiconductor device. In the mode, the first dielectric layer with low dielectric constant is respectively filled in the first groove and the second groove of the second epitaxial wafer, and the depth of the first dielectric layer is lower than that of the two-dimensional electronic gas structure layer, so that the parasitic capacitance effect generated by mutual coupling between the electrodes of the semiconductor device can be reduced, and the working frequency of the semiconductor device can be improved. The structure does not need to change the length of the gate, so that the yield and the reliability of the semiconductor device can be ensured while the manufacturing cost of the semiconductor device is controlled.
An embodiment of the present invention further provides another method for manufacturing a semiconductor device, which is implemented on the basis of the method in the foregoing embodiment, and the method mainly describes a determination manner of a second epitaxial wafer and a specific process of processing the second epitaxial wafer with the first dielectric layer to obtain the semiconductor device, as shown in fig. 3, the method includes the following steps:
step S302, a second epitaxial wafer is obtained; the second epitaxial wafer is provided with a first groove and a second groove, and a second dielectric layer is deposited in a first area of the upper surface of the second epitaxial wafer except the first groove and the second groove; the second epitaxial wafer comprises a two-dimensional electron gas structure layer.
The second epitaxial wafer is obtained by:
step one, forming an isolation region in a preset region at the edge of an initial epitaxial wafer obtained in advance to obtain an epitaxial wafer with the isolation region; the initial epitaxial wafer comprises a two-dimensional electronic gas structure layer; the lower surface of the isolation region is lower than the lower surface of the two-dimensional electron gas structure layer.
Referring to fig. 4, a schematic structural diagram of an initial epitaxial wafer is shown, in which fig. 4(b) is a cross-sectional view of fig. 4(a), and as can be seen from fig. 4, the initial epitaxial wafer is generally an original epitaxial wafer that has not been subjected to etching, deposition, or the like, and the initial epitaxial wafer includes a two-dimensional electron gas structure layer, which is generally a structural layer with a certain depth and is closer to the upper surface of the initial epitaxial wafer; referring to fig. 5, which is a schematic structural diagram of an epitaxial wafer with an isolation region, where fig. 5(b) is a cross-sectional view of fig. 5(a), the isolation region may be formed in an ion implantation manner or in a mesa etching manner in an edge preset region of an obtained initial epitaxial wafer, so as to obtain an epitaxial wafer with an isolation region; the depth of the formed isolation region is generally required to be greater than that of the two-dimensional electron gas structure layer, that is, the lower surface of the isolation region is lower than that of the two-dimensional electron gas structure layer.
And secondly, depositing a second dielectric layer on the first region of the upper surface of the epitaxial wafer with the isolation region.
The first area is usually the area except the area where the source and the drain are required to be etched on the epitaxial wafer with the isolation area; referring to fig. 6, which is a schematic structural diagram of an epitaxial wafer, in which fig. 6(b) is a cross-sectional view of fig. 6(a), in an actual implementation, after the epitaxial wafer with the isolation region is obtained, a second dielectric layer 16 may be deposited on the first region of the upper surface of the epitaxial wafer with the isolation region, where the thickness of the second dielectric layer is generally 20nm to 500nm, and the material of the second dielectric layer may include silicon nitride, silicon dioxide, and other dielectrics may be selected according to actual requirements.
And step three, taking the second dielectric layer as a mask, and carrying out etching treatment on the region except the first region on the epitaxial wafer with the isolation region to obtain a second epitaxial wafer.
Selecting and etching the epitaxial wafer with the isolation region by using the second dielectric layer as a mask, specifically, etching the region of the epitaxial wafer with the isolation region except the first region, wherein the etching depth is generally 20nm-500 nm; the first groove and the second groove may be etched, referring to another structure diagram of an epitaxial wafer shown in fig. 7, where fig. 7(b) is a cross-sectional view of fig. 7(a), a source and a drain of a semiconductor device may be disposed in the first groove and the second groove, and after the etching process, the second epitaxial wafer may be obtained.
Step S304, depositing a first dielectric layer on the second epitaxial wafer; and in the first groove and the second groove, the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer.
Referring to fig. 8, in another structure diagram of an epitaxial wafer, fig. 8(b) is a cross-sectional view of fig. 8(a), the first dielectric layer is deposited on the upper surface of the second epitaxial wafer, including the upper surfaces of the first and second grooves, wherein after the first dielectric layer is deposited in the two grooves, the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer; the thickness of the first dielectric layer is generally 20nm-50nm, and the appropriate thickness can be selected according to actual requirements.
Step S306, a first metal layer is formed on the epitaxial wafer with the first dielectric layer.
Anisotropically depositing a first metal layer on an epitaxial wafer with a first dielectric layer, specifically, referring to another structural schematic diagram of an epitaxial wafer shown in fig. 9, wherein fig. 9(b) is a cross-sectional view of fig. 9(a), the first metal layer needs to be deposited in both a first area and an etching area, wherein the upper surface of the deposited first metal layer in the etching area needs to exceed the upper surface of the epitaxial wafer, each side surface needs to be communicated with a two-dimensional electron gas structure layer, and the thickness of the deposited first metal layer is generally 20nm-500nm for forming source and drain ohmic contacts.
Step S308, the first metal layer, the first dielectric layer and the second dielectric layer covering the first region are removed.
Specifically, the step S308 can be implemented by the following steps six and seven:
and step six, stripping the first metal layer covered on the first area.
After the first metal layer is formed on the epitaxial wafer with the first dielectric layer, the first metal layer correspondingly covered on the first region needs to be stripped, which may specifically refer to a metal stripping process in the prior art and is not described herein again.
And seventhly, removing the first dielectric layer and the second dielectric layer covered on the first area in a wet etching mode.
The wet etching is understood to mean that the wafer is etched in a liquid chemical etching solution, and the etching solution gradually etches and dissolves the materials contacted with the wafer through chemical reaction during the etching process. In practical implementation, after the first metal layer covered on the first region is stripped, the first dielectric layer and the second dielectric layer correspondingly covered on the first region generally need to be continuously removed, and the process may be performed in a wet etching manner, which may specifically refer to a wet etching process in the prior art and is not described herein again; referring to fig. 10 showing another structure of an epitaxial wafer, wherein fig. 10(b) is a cross-sectional view of fig. 10(a), it can be seen that the first metal layer, the first dielectric layer and the second dielectric layer covering the first region have been removed.
And step S310, depositing a second metal layer at the designated position of the first area to obtain the semiconductor device.
The designated location is generally an intermediate region of the first region, for example, as shown in fig. 1, the second metal layer may be deposited on the upper surface of the first region at an intermediate position between the first recess and the second recess to form a gate metal, and the semiconductor device may be finally obtained.
Referring to fig. 11, another schematic structural diagram of a semiconductor device is shown, and fig. 11 illustrates a conventional HEMT device as an example, in the HEMT device, there are mainly three parasitic capacitance effects, namely Cds, Cgs, and Cgd.
According to the manufacturing method of the semiconductor device, under the conditions that the length of a grid is not changed, the structure of an epitaxial wafer is not changed, and the process difficulty is not obviously increased, the parasitic capacitance effect generated by mutual coupling among the grid, the source and the drain electrodes is reduced by filling a low dielectric constant (low-K) medium under the metal of the source and the drain electrodes, so that the aim of increasing the working frequency of the device is fulfilled; the process has strong compatibility with the existing HEMT process, has strong applicability, and can solve the problem that the working frequency of the HEMT device is restricted by the parasitic capacitance effect.
The block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and computer program products according to various embodiments of the present invention. In this regard, each block in the block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams, and combinations of blocks in the block diagrams, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, in the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Unless specifically stated otherwise, the relative numerical expressions and values of the components set forth in these embodiments do not limit the scope of the present invention.
In all examples shown and described herein, any particular value should be construed as merely exemplary, and not as a limitation, and thus other examples of example embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments provided by the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A semiconductor device, comprising: the device comprises a first epitaxial wafer with a first groove and a second groove, a first dielectric layer with a low dielectric constant, a grid electrode arranged on the upper surface of the first epitaxial wafer, a source electrode arranged in the first groove, and a drain electrode arranged in the second groove; wherein the source and the drain are arranged at two sides of the gate; the first epitaxial wafer comprises a two-dimensional electronic gas structure layer;
the first dielectric layer is deposited in the first groove and the second groove, and the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electron gas structure layer; depositing a first metal layer on the first dielectric layer in the first groove and the second groove to form the source electrode and the drain electrode;
the grid electrode is formed by depositing a second metal layer at a designated position on the upper surface of the first epitaxial wafer.
2. The semiconductor device of claim 1, wherein an upper surface of the first metal layer within the first recess and the second recess is higher than an upper surface of the first epitaxial wafer.
3. The semiconductor device of claim 1, wherein the sides of the first metal layer within the first recess and the second recess are both in communication with the two-dimensional electron gas structure layer.
4. The semiconductor device of claim 1, wherein the edge predetermined region of the first epitaxial wafer is provided with an isolation region.
5. The semiconductor device according to claim 1, wherein a material of the first dielectric layer comprises silicon nitride or silicon dioxide.
6. A method of fabricating a semiconductor device, the method comprising:
obtaining a second epitaxial wafer; the second epitaxial wafer is provided with a first groove and a second groove, and a second dielectric layer is deposited in a first area of the upper surface of the second epitaxial wafer except the first groove and the second groove; the second epitaxial wafer comprises a two-dimensional electronic gas structure layer;
depositing a first dielectric layer with a low dielectric constant on the second epitaxial wafer; in the first groove and the second groove, the upper surface of the first dielectric layer is lower than the lower surface of the two-dimensional electronic gas structure layer;
and processing the second epitaxial wafer with the first dielectric layer to obtain the semiconductor device.
7. The method of claim 6, wherein the second epitaxial wafer is obtained by:
forming an isolation region in a preset region at the edge of the initial epitaxial wafer obtained in advance to obtain an epitaxial wafer with the isolation region; the initial epitaxial wafer comprises a two-dimensional electron gas structure layer; the lower surface of the isolation region is lower than the lower surface of the two-dimensional electron gas structure layer;
depositing a second dielectric layer on the first region of the upper surface of the epitaxial wafer with the isolation region;
and etching the regions of the epitaxial wafer with the isolation region except the first region by taking the second dielectric layer as a mask to obtain the second epitaxial wafer.
8. The method of claim 6, wherein processing the second epitaxial wafer with the first dielectric layer to obtain the semiconductor device comprises:
forming a first metal layer on the epitaxial wafer with the first dielectric layer;
removing the first metal layer, the first dielectric layer and the second dielectric layer which are covered on the first area;
and depositing a second metal layer at the appointed position of the first area to obtain the semiconductor device.
9. The method of claim 8, wherein the step of removing the first metal layer, the first dielectric layer, and the second dielectric layer overlying the first region comprises:
stripping the first metal layer covering the first area;
and removing the first dielectric layer and the second dielectric layer which cover the first region by adopting a wet etching mode.
10. The method of claim 6, wherein the material of the second dielectric layer comprises silicon nitride or silicon dioxide.
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| US20100012977A1 (en) * | 2008-07-15 | 2010-01-21 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Semiconductor device |
| JP2012060082A (en) * | 2010-09-13 | 2012-03-22 | Tokyo Institute Of Technology | Field-effect transistor |
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| CN102769033A (en) * | 2011-05-05 | 2012-11-07 | 中国科学院微电子研究所 | HEMT with high breakdown voltage and method of manufacturing the same |
| CN110047910A (en) * | 2019-03-27 | 2019-07-23 | 东南大学 | A kind of heterojunction semiconductor device of high voltage ability |
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| US20100012977A1 (en) * | 2008-07-15 | 2010-01-21 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Semiconductor device |
| JP2012060082A (en) * | 2010-09-13 | 2012-03-22 | Tokyo Institute Of Technology | Field-effect transistor |
| US20120168877A1 (en) * | 2010-12-30 | 2012-07-05 | Niloy Mukherjee | Method to reduce contact resistance of n-channel transistors by using a iii-v semiconductor interlayer in source and drain |
| CN102769033A (en) * | 2011-05-05 | 2012-11-07 | 中国科学院微电子研究所 | HEMT with high breakdown voltage and method of manufacturing the same |
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