JP2012060082A - Field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve high carrier concentration of a source of a field-effect transistor while suppressing a load in respect of processes.SOLUTION: A gate insulating film 30 is formed in a gate region on a first surface of a channel layer 20 of a group 3-5 compound semiconductor. A source contact layer 34 and a drain contact layer 38 are respectively formed in a drain region and a source region that are disposed on the first surface of the channel layer 20 so as to sandwich the gate region. A backside insulating film 50 is formed on a second surface of the channel layer 20 located at the side opposite to the first surface. A lower source electrode 52 is formed in a region facing the source contact layer 34, on the side of the backside insulating film 50 opposite to the side on which the channel layer 20 is provided.

Description

  The present invention relates to a compound semiconductor field effect transistor.

  According to the 2009 roadmap of ITRS (International Technology Roadmap for Semiconductors), in order to satisfy the characteristics required for future transistors, III-V group compound semiconductors are used as high mobility channel materials in N-channel. The need for germanium (Ge) has been pointed out in the P channel.

  It has been predicted by simulations by a plurality of research institutions that an increase in carrier concentration in the source region is necessary for increasing the current of a field effect transistor structure using a compound semiconductor. In order to improve the source carrier concentration, in addition to high-concentration doping by ion implantation, which is common in silicon devices, molecular beam epitaxy and metalorganic vapor phase epitaxy, which are considered to be more suitable for III-V devices A regrowth process using silicon, a metal source using metal as a source, etc. have been proposed, and its device operation has been reported.

  On the other hand, these methods require high-temperature processing, and there are still problems in introduction into the integration process, cost increase by introducing crystal growth, carrier injection ability deterioration due to formation of Schottky barrier at the metal / semiconductor interface, etc. There is a problem.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and one of exemplary purposes of an embodiment thereof is to realize a high carrier concentration of a source in a field effect transistor while suppressing a load on a process. .

  One embodiment of the present invention relates to a field effect transistor. This field effect transistor includes a channel layer of a 3-5 (III-V) group compound semiconductor, a gate insulating film formed in a gate region on the first surface of the channel layer, and a gate region on the first surface of the channel layer. A drain contact layer and a source contact layer formed in each of the drain region and the source region located so as to sandwich the gate electrode, a back surface insulating film formed on the second surface side opposite to the first surface of the channel layer, and a back surface insulation A source lower surface electrode formed in a region facing the source contact layer is provided on the surface of the film opposite to the channel layer.

According to this aspect, by applying an appropriate potential to the source lower surface electrode, a source region having a high carrier concentration (high concentration source region) can be formed, and the carrier concentration can be improved. This structure has a lower load on the process compared to various currently proposed technologies, offers cost advantages over the ion implantation and regrowth methods, and uses a metal source structure. In comparison, since the Schottky barrier is not passed, an effect of increasing the carrier injection capability can be obtained.
In addition, the overlap length of the high-concentration source region and the gate electrode can be arbitrarily changed by the design of the source bottom electrode. This makes it possible to reduce the access resistance in the on state due to overlap formation and improve the drive current associated therewith, against the trade-off related to off-leakage current due to charging delay and barrier reduction due to the increase in gate parasitic capacitance that occurs at the same time. However, it is possible to easily form an optimum structure for each application of the device.

  Note that any combination of the above-described components, or a conversion of the expression of the present invention between methods, apparatuses, and the like is also effective as an aspect of the present invention.

  According to an aspect of the present invention, it is possible to realize a high carrier concentration of a source in a field effect transistor while suppressing a process load. Further, the characteristics can be improved by controlling the overlap length between the gate electrode and the high concentration source region.

It is sectional drawing which shows the structure of the semiconductor device (N channel field effect transistor) which concerns on embodiment. 2A to 2F are views showing a method for manufacturing the semiconductor device of FIG. 3A to 3F are views showing a method for manufacturing the semiconductor device of FIG. 4A is a schematic diagram of the band structure of the source region of the semiconductor device of FIG. 1, and FIG. 4B is a schematic diagram of the band structure of the source region of a general FET in which the source bottom electrode is not provided. FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  FIG. 1 is a cross-sectional view showing the structure of a semiconductor device (N-channel field effect transistor) 100 according to an embodiment. The semiconductor device 100 includes a substrate 2 and an FET 10 bonded thereon.

  The substrate 2 is, for example, a silicon substrate. An FET 10 is bonded on the substrate 2 through a bonding layer 4. The bonding layer 4 is, for example, a BCB (benzocyclobutene) adhesive, and the FET 10 formed through a process described later is fixed on the substrate 2.

  The FET 10 includes a channel layer 20, a gate insulating film 30, a gate electrode 32, a source contact layer 34, a source electrode 36, a drain contact layer 38, a drain electrode 40, a back surface insulating film 50, and a source lower surface electrode 52.

  The channel layer 20 includes an upper confinement layer 22, a channel layer 24, and a lower confinement layer 26 that are stacked. For the channel layer 24, a high electron mobility material, specifically, a III-V compound semiconductor such as indium gallium arsenide (InGaAs) or indium arsenide (InAs) is used. For the upper confinement layer 22 and the lower confinement layer 26, indium phosphide (InP), indium aluminum arsenide (InAlAs), or the like is used. The upper confinement layer 22 functions as an etch stop layer in wet etching for forming a channel intrinsic portion recess structure. Further, the upper confinement layer 22 and the channel layer 24 have a role of suppressing the carrier distribution in the channel and scattering due to roughness and trap charges at the insulating film / semiconductor interface and improving the carrier traveling speed in the channel.

  A gate insulating film 30 is formed in the gate region on the upper surface (first surface) of the channel layer 20. A gate electrode 32 is formed on the gate insulating film 30. In addition, a back surface insulating film 50 is formed on the lower surface (second surface) side of the channel layer 20. The gate insulating film 30 and the back surface insulating film 50 may be high-K gate insulating films.

  On the upper surface of the channel layer 20, a source electrode 36 and a drain electrode 40 are respectively formed in the source region S and the drain region D that are arranged so as to sandwich the gate region G. A source contact layer 34 and a drain contact layer 38 are formed between the source electrode 36 and the channel layer 20 and between the drain electrode 40 and the channel layer 20, respectively. The source contact layer 34 and the drain contact layer 38 are made of a highly doped material, such as indium gallium arsenide (n + -InGaAs).

The source lower surface electrode 52 is formed in a region facing the lower surface of the back insulating film 50, that is, the source electrode 36 on the surface side opposite to the channel layer 20. The source lower surface electrode 52 can be formed at any position according to the alignment accuracy with respect to the gate electrode 32, and the length L in the channel direction, that is, the overlap length L _OLP with the base of the gate electrode 32 is also arbitrary. Can be designed. As the source lower surface electrode 52, an appropriate metal material such as gold or chromium can be used.

The above is the configuration of the semiconductor device 100. Next, the manufacturing method will be described.
2 (a) to 2 (f) and FIGS. 3 (a) to 3 (f) are diagrams illustrating a method of manufacturing the semiconductor device 100 of FIG.
FIG. 2A shows a cross section of the substrate structure. The contact layers 34 and 38, the channel layer 20, and the cap layer 60 are formed in this order from the deep region to the shallow region of the InP wafer (support substrate) 3. The formation of each layer may be performed using a known technique and is not particularly limited. It should be noted that in FIGS. 2A to 2C, the top and bottom of FIG.

  Subsequently, as shown in FIG. 2B, the cap layer 60 is removed by etching or polishing. Thereby, the channel layer 20 appears on the surface. Subsequently, as shown in FIG. 2C, a back surface insulating film 50 is formed on the upper surface of the channel layer 20.

  Subsequently, as shown in FIG. 2D, the source lower surface electrode 52 is formed on the back surface insulating film 50. The structure shown in FIG. 2D is bonded to the substrate 2 through the bonding layer 4 with the source lower surface electrode 52 side as the bonding surface, and the structure shown in FIG. 2E is obtained. Subsequently, the wafer 3 is thinned to expose the contact layers 34 and 38 as shown in FIG.

Turning to FIG. In order to isolate adjacent FETs (element isolation), the outer peripheral portions of the contact layers 34 and 38 and the channel layer 20 are etched. Subsequently, as shown in FIG. 3B, the contact layers 34 and 38 in the gate region are etched to the depth of the channel layer 20 (channel out). Subsequently, as shown in FIG. 3C, a gate insulating film 30 is deposited so as to cover the entire FET. Subsequently, as shown in FIG. 3D, a gate electrode 32 is formed on the upper surface of the gate insulating film 30 in the gate region by vapor deposition. Subsequently, as shown in FIG. 3E, contact holes 62 and 64 are formed in the source region and the drain region of the gate insulating film 30. Subsequently, as shown in FIG. 3F, the source electrode 36 and the drain electrode 40 are formed on the contact holes 62 and 64 by vapor deposition.
The method for manufacturing the semiconductor device 100 has been described above.

Next, advantages of the semiconductor device 100 of FIG. 1 will be described. 4A is a schematic diagram of the band structure of the source region of the semiconductor device 100 of FIG. 1, and FIG. 4B is a schematic diagram of the band structure of the source region of the FET in which the source lower surface electrode 52 is not provided. Show. EF _(BS) represents the Fermi level of the source lower surface electrode 52, and EF _(S) represents the Fermi level of the source region.

  Reference is first made to FIG. In the conventional device structure, carrier (electron) injection from the source contact layer 34 to the channel layer 24 is inhibited by the upper confinement layer 22 which is a wide gap layer.

Next, the semiconductor device 100 of FIG. 1 will be described with reference to FIG. And applying the appropriate voltages to the source the lower electrode 52, between the source electrode 36 and the source lower electrode 52 when a bias by the voltage V _BS, the contact is reduced in the source region, the bottom of the channel layer 24 of the source contact layer 34 A high carrier concentration is induced, and a high concentration electron storage layer can be formed.

  As described above, according to the semiconductor device 100 of FIG. 1, the carrier concentration in the source region is increased, whereby the current driving capability of the FET alone can be improved, and the cut-off frequency can be increased accordingly.

In general n-type FETs including a CMOS logic circuit, the source is generally grounded. Thus between the source electrode 36 and the source lower electrode 52 is always to be biased by the bias voltage V _BS, there is an advantage that is not affected by the capacitive delay due to charging and discharging of the charge.

Further, since the bonding using the BCB bonding layer 4 is not limited to the support substrate, it can be transferred by bonding onto the Si substrate, and can be applied as a heterogeneous material integration process.
Further, when forming the source lower surface electrode 52, the alignment with respect to the source region, the gate region, and the drain region is important. As this alignment, the SEM observation of the electrode beyond the device layer is possible. It can be said that it corresponds to the alignment technique using an electron beam or the like.

  In summary, according to the semiconductor device 100 according to the embodiment, the carrier concentration can be improved by applying an appropriate potential to the source lower surface electrode 52. This structure has a lower load on the process compared to various currently proposed technologies, offers cost advantages over the ion implantation and regrowth methods, and uses a metal source structure. In comparison, since the Schottky barrier is not passed, an effect of increasing the carrier injection capability can be obtained.

  Further, by optimizing the position and length L of the source lower surface electrode 52 with respect to the gate electrode 32, it is possible to realize good controllability with respect to the trade-off between high driving capability and parasitic capacitance / standby power. Specifically, if the length L in the channel direction is increased to increase the amount of overlap with the gate electrode 32 (gate region), the off-leakage current increases due to charging delay and barrier reduction due to an increase in gate parasitic capacitance. In exchange for this, it is possible to reduce the access resistance in the on-state of the transistor and to improve the drive current associated therewith. On the other hand, when the overlap amount is reduced, the effect of reducing the access resistance is reduced, but in exchange, the effect of reducing the gate parasitic capacitance and reducing the off-leakage current can be obtained. That is, it becomes possible to easily form an optimum structure for each application of the device.

  Furthermore, the back surface processing bonding technique is attractive as an integration technique on a silicon substrate, and leads to logic circuit applications of high mobility materials that are currently attracting attention.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

  An electrode (drain back electrode) similar to the source bottom electrode 52 may be further provided on the back side of the drain electrode 40.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Semiconductor device, 2 ... Substrate, 3 ... Wafer, 4 ... Junction layer, 10 ... FET, 20 ... Channel layer, 22 ... Upper confinement layer, 24 ... Channel layer, 26 ... Lower confinement layer, 30 ... Gate insulating film , 32 ... gate electrode, 34 ... source contact layer, 36 ... source electrode, 38 ... drain contact layer, 40 ... drain electrode, 50 ... backside insulating film, 52 ... source bottom electrode, 60 ... cap layer.

Claims (2)

A channel layer of a group 3-5 compound semiconductor;
A gate insulating film formed in the gate region of the first surface of the channel layer;
A drain contact layer and a source contact layer formed on each of the drain region and the source region located so as to sandwich the gate region on the first surface of the channel layer;
A back surface insulating film formed on the second surface side opposite to the first surface of the channel layer;
A source lower surface electrode formed in a region facing the source contact layer on a surface opposite to the channel layer of the back surface insulating film;
A field effect transistor comprising:   By arranging the electrode on the surface opposite to the channel layer of the back surface insulating film over an arbitrary range from the source contact layer to the gate end, a high carrier concentration region can be formed on the source side, and A field-effect transistor characterized in that the presence / absence and length of an overlap between a source-side high carrier concentration region and a gate electrode can be freely designed.

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