CN113451353A - Method for forming MRAM device - Google Patents
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Abstract
A method for forming an MRAM device comprises the steps of firstly patterning a second magnetic material layer and a barrier material layer in a magnetic tunnel junction material layer, and stopping etching a first magnetic material layer in the magnetic tunnel junction structure layer, so that a residual magnetic layer formed by redeposition is easy to remove; meanwhile, after the residual magnetic layer is removed by etching, a first protective layer is formed on the side walls of the second magnetic layer and the barrier layer, and then the first magnetic material layer and the bottom electrode material layer are etched by taking the first protective layer as a mask to form the first magnetic layer and the bottom electrode layer, so that the magnetic material redeposited in the subsequent etching process can be prevented from covering the side walls of the barrier layer, the short circuit of the barrier layer can be avoided, and the performance of the MRAM device can be improved.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a method for forming an MRAM device.
Background
Magnetic Random Access Memory (MRAM) is a Memory that uses Magnetic elements.
Among them, Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) has the characteristics of high read-write speed, high density, low power consumption, long data storage time, long service life, and the like, and has immeasurable broad prospects. More significantly, STT-MRAM can be based on existing CMOS fabrication technology and process development, and is technically less difficult to implement, which can directly challenge the low cost of flash memory.
However, the performance of the conventional magnetic random access memory still needs to be improved.
Disclosure of Invention
The problem addressed by the present invention is to provide an MRAM device to improve the performance of magnetic random access memories.
To solve the above problems, the present invention provides a method of forming an MRAM device, the method comprising:
providing a substrate;
forming a bottom electrode material layer and a magnetic tunnel junction material layer on the bottom electrode material layer on the substrate, the magnetic tunnel junction material layer including a first magnetic material layer, a barrier material layer on the first magnetic material layer, and a second magnetic material layer on the barrier material layer;
patterning the second magnetic material layer and the barrier material layer until the surface of the first magnetic material layer is exposed, and forming a second magnetic layer and a barrier layer, wherein the side wall of the second magnetic layer and the side wall of the barrier layer are provided with residual magnetic layers;
etching to remove the residual magnetic layer;
after the residual magnetic layer is removed by etching, forming a first protective layer on the side walls of the second magnetic layer and the barrier layer;
and etching the first magnetic material layer and the bottom electrode material layer by taking the first protective layer as a mask to form a first magnetic layer and a bottom electrode layer.
Optionally, the process of patterning the second magnetic material layer and the barrier material layer includes a first ion beam etching process; the etching angle of the first ion beam etching process is 20-45 degrees, and the energy is 80-800 eV.
Optionally, the process of removing the residual magnetic layer by etching comprises a second ion beam etching process; the etching angle of the second ion beam etching process is 50-80 degrees, and the energy is 20 eV-200 eV.
Optionally, the first magnetic material layer is a reference material layer, and the second magnetic material layer is a free material layer; the first magnetic layer is a reference layer, and the second magnetic layer is a free layer.
Optionally, the magnetic tunnel junction material layer further comprises a capping material layer located above the free material layer and a pinned material layer located below the reference material layer; prior to patterning the second magnetic material layer and the barrier material layer, the method further comprises: etching the covering material layer to form a covering layer; the method further comprises the following steps: and etching the pinning material layer by taking the first protective layer as a mask to form a pinning layer in the process of etching the first magnetic material layer and the bottom electrode material layer by taking the first protective layer as a mask.
Optionally, in a process of etching the first magnetic material layer and the bottom electrode material layer with the first protection layer as a mask, a part of the first protection layer is removed by etching, or all of the first protection layer is removed by etching.
Optionally, the method further comprises: before patterning the second magnetic material layer and the barrier material layer, forming a hard mask layer on the magnetic tunnel junction material layer, wherein the hard mask layer comprises a metal hard mask layer and a medium hard mask layer positioned on the metal hard mask layer; patterning the second magnetic material layer and the barrier material layer by using the hard mask layer as a mask; and etching and removing the residual magnetic layer by taking the hard mask layer as a mask.
Optionally, the material of the dielectric hard mask layer comprises SiO2 or SiN, and the thickness is 500 nm-800 nm; the metal hard mask layer is made of Ta, TaN, Ti or TiN, and the thickness of the metal hard mask layer is 450 nm-700 nm.
Optionally, the step of forming the first protection layer includes: forming a first protective material layer on the sidewalls of the second magnetic layer and the barrier layer, the top of the second magnetic layer, and the surface of the first magnetic material layer; and etching and removing the top of the second magnetic layer and the first protective material layer on the surface of the first magnetic material layer to form the first protective layer.
Optionally, the process of forming the first protective material layer includes an atomic layer deposition process or a chemical vapor deposition process.
Optionally, the process of etching to remove the top of the second magnetic layer and the first protective material layer over the surface of the first magnetic material layer includes a third ion beam etching process or a reactive ion etching process.
Optionally, the material of the first protection layer includes SiN or SiCN, and the thickness is 10nm to 30 nm.
Optionally, after the first magnetic layer and the bottom electrode layer are formed, the method further includes: and forming a second protective layer covering the side walls of the first magnetic layer, the barrier layer, the second magnetic layer and the bottom electrode layer, the top of the second magnetic layer and the surface of the substrate.
Optionally, the material of the second protective layer is the same as or different from the material of the first protective layer.
Optionally, the thickness of the second protective layer is 10nm to 30 nm.
Optionally, the material of the bottom electrode layer comprises Ta, TaN, Ti or TiN, and the thickness is 15nm to 25 nm.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the scheme, the second magnetic material layer and the barrier material layer in the magnetic tunnel junction material layer are patterned firstly, and etching of the first magnetic material layer in the magnetic tunnel junction structure layer is stopped, so that the number of residual magnetic layers formed by redeposition can be reduced, the depth of the residual magnetic layers is not too large, the shielding effect in the residual magnetic removing process is reduced, and the residual magnetic layers are easy to clean; and simultaneously, after the residual magnetic layer is removed by etching, forming a first protective layer on the side walls of the second magnetic layer and the barrier layer, and etching the first magnetic material layer and the bottom electrode material layer by taking the first protective layer as a mask to form a first magnetic layer and a bottom electrode layer. In the process of etching the first magnetic material layer and the bottom electrode material layer, the barrier layer is isolated by the first protective layer, so that the magnetic material redeposited in the etching process can be prevented from covering the side wall of the barrier layer, the magnetic material deposited on the side wall of the barrier layer can be prevented from being in direct contact with the barrier layer, short circuit is avoided, and the performance of the MRAM device can be improved.
Drawings
Fig. 1 and 2 are schematic diagrams of a method of forming an MRAM device.
FIG. 3 is a flow chart illustrating a method of forming an MRAM device in an embodiment of the invention;
fig. 4 to 11 are intermediate structural diagrams corresponding to steps of a method of forming an MRAM device in an embodiment of the present invention.
Detailed Description
It is known in the art that the performance of the existing MRAM devices is to be improved.
Referring to fig. 1, a substrate (not shown) is provided on which a bottom electrode material layer 110 and a magnetic tunnel junction material layer 120 on the bottom electrode material layer are formed.
Referring to fig. 2, a patterned hard mask layer 130 is formed on the magnetic tunnel junction material layer 120, and the magnetic tunnel junction structure layer 120 and the bottom electrode layer 110 are etched using the patterned hard mask layer 130 as a mask, thereby forming a bottom electrode 115 and a magnetic tunnel junction structure 125 located above the bottom electrode 115. The hard mask layer 130 includes a metal hard mask layer 131 and a dielectric hard mask layer 132 located on the metal hard mask layer 131.
The magnetic tunnel junction material layer 120 includes a first magnetic material layer 121, a barrier material layer 122 on the first magnetic material layer 121, and a second magnetic material layer 123 on the barrier material layer 122. The first and second magnetic material layers 121 and 123 are made of a magnetic material, and the barrier material layer 122, which is an insulating layer between the first and second magnetic material layers 121 and 123, is made of a non-magnetic material.
In the process of etching the magnetic tunnel junction structure layer 120 and the bottom electrode layer 110 by using the patterned hard mask layer 130 as a mask, the magnetic materials in the first magnetic material layer 121 and the second magnetic material layer 123 may be redeposited on the sidewall of the barrier layer 122', so as to form a residual magnetic layer 140. The presence of residual magnetic layer 140 will cause first magnetic layer 121 'and second magnetic layer 123' to communicate with each other, forming a short circuit.
One method proposes that after the magnetic tunnel junction structure 125 is etched, an ion beam etching process or a reactive ion etching process is used to remove the residual magnetic layer 140 redeposited on the sidewall of the magnetic tunnel junction structure 125. However, due to the blocking effect, the magnetic material layer 140 deposited on the sidewall of the magnetic tunnel junction structure 125 cannot be completely removed by the ion beam etching process or the reactive ion etching process. Thermal oxidation is typically also performed to completely remove the magnetic material layer 140 deposited on the sidewalls of the magnetic tunnel junction structure 125. On one hand, the thermal oxidation treatment can cause the magnetic materials in the magnetic tunnel junction structure to be oxidized together, so that the performance of the magnetic tunnel junction structure is reduced; on the other hand, high temperatures during thermal oxidation process may also degrade the performance of the magnetic tunnel junction structure 125.
In order to solve the above problem, an embodiment of the present invention provides a method for forming an MRAM device, including: providing a substrate; forming a bottom electrode material layer and a magnetic tunnel junction material layer on the bottom electrode material layer on the substrate, the magnetic tunnel junction material layer including a first magnetic material layer, a barrier material layer on the first magnetic material layer, and a second magnetic material layer on the barrier material layer; patterning the second magnetic material layer and the barrier material layer until the surface of the first magnetic material layer is exposed, and forming a second magnetic layer and a barrier layer, wherein the side wall of the second magnetic layer and the side wall of the barrier layer are provided with residual magnetic layers; etching to remove the residual magnetic layer; after the residual magnetic layer is removed by etching, forming a first protective layer on the side walls of the second magnetic layer and the barrier layer; and etching the first magnetic material layer and the bottom electrode material layer by taking the first protective layer as a mask to form a first magnetic layer and a bottom electrode layer.
In the forming method of the MRAM device provided in the embodiment of the present invention, by first patterning the second magnetic material layer and the barrier material layer in the magnetic tunnel junction structure layer, and stopping etching the first magnetic material layer in the magnetic tunnel junction structure layer, the number of magnetic materials redeposited on the side wall of the partial magnetic tunnel junction structure layer can be reduced, and the depth of the residual magnetic layer is not too large, so that the shielding effect in the residual magnetic removal process is reduced, and thus the residual magnetic layer is easy to clean; and simultaneously, after the residual magnetic layer is removed by etching, forming a first protective layer on the side walls of the second magnetic layer and the barrier layer, and etching the first magnetic material layer and the bottom electrode material layer by taking the first protective layer as a mask to form a first magnetic layer and a bottom electrode layer. In the process of etching the first magnetic material layer and the bottom electrode material layer, the barrier layer is isolated by the first protective layer, so that the magnetic material redeposited in the etching process can be prevented from covering the side wall of the barrier layer, the magnetic material deposited on the side wall of the barrier layer can be prevented from being in direct contact with the barrier layer, short circuit is avoided, and the performance of the MRAM device can be improved.
Fig. 3 is a flow chart illustrating a method of forming an MRAM device in an embodiment of the present invention.
Referring to fig. 3, a method for forming an MRAM device in an embodiment of the present invention may specifically include:
step S301: providing a substrate;
step S302: forming a bottom electrode material layer and a magnetic tunnel junction material layer on the bottom electrode material layer on the substrate, the magnetic tunnel junction material layer including a first magnetic material layer, a barrier material layer on the first magnetic material layer, and a second magnetic material layer on the barrier material layer;
step S303: patterning the second magnetic material layer and the barrier material layer until the surface of the first magnetic material layer is exposed, and forming a second magnetic layer and a barrier layer, wherein the side wall of the second magnetic layer and the side wall of the barrier layer are provided with residual magnetic layers;
step S304: etching to remove the residual magnetic layer;
step S305: after the residual magnetic layer is removed by etching, forming a first protective layer on the side walls of the second magnetic layer and the barrier layer;
step S306: and etching the first magnetic material layer and the bottom electrode material layer by taking the first protective layer as a mask, and forming a first magnetic layer and a bottom electrode layer.
A method of forming an MRAM device in an embodiment of the present invention will be described in further detail with reference to fig. 4 through 11.
Referring to fig. 4, a substrate (not shown) is provided, on which a first metal layer 400, a dielectric layer 410 on the first metal layer 400, and a plug 411 penetrating the dielectric layer, and a bottom electrode material layer 420 on the dielectric layer 410 and the plug 411 are formed.
In a specific implementation, the substrate provides a process platform for subsequent formation of the MRAM device.
In a specific implementation, the base can be a silicon substrate or a germanium substrate or the like. In addition, other devices, such as PMOS transistors and NMOS transistors, may be formed in the substrate; an isolation structure can be formed in the substrate, wherein the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure; the substrate may also have CMOS devices formed therein, such as NMOS transistors and/or PMOS transistors. Similarly, a conductive member may be formed in the substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like.
The first metal layer 400 may be a bottom metal layer M1 or an intermediate metal layer Mn (n is an integer greater than 1) in the MRAM device, which may be made of a magnetic material such as copper or tungsten.
The dielectric layer 410 is used to isolate the adjacent plugs 411.
In a specific implementation, dielectric layer 410 may be made of an oxide or a low-K material having a dielectric constant lower than that of silicon dioxide. In this embodiment, the dielectric layer 410 is made of silicon dioxide (SiO 2). In other embodiments, dielectric layer 410 may also comprise, for example, silicon oxide, fluorine or carbon doped silicon oxide, porous silicon oxide, spin-on organic polymers, or inorganic polymers such as hydrogen silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), and the like.
In a specific implementation, the plug 411 serves as a contact between the first metal layer 400 and a subsequently formed bottom electrode.
In this embodiment, the plug 411 is formed by a damascene process. Specifically, the dielectric layer 410 is etched to form a through hole penetrating through the dielectric layer 410, and the bottom of the through hole exposes the material of the semiconductor substrate 410; the via is filled with a conductive material, such as copper, and a planarization process, such as a chemical mechanical polishing process or an etch-back process, is performed to make the top surface of the filled conductive material flush with the top surface of the dielectric layer 410, thereby forming a plug 411 located in the dielectric layer 410 and penetrating through the dielectric layer 410.
The bottom electrode material layer 420 provides a process foundation for forming the bottom electrode of the Magnetic Tunnel Junction (MTJ).
In an embodiment of the present invention, the material of the bottom electrode material layer 420 may include Ta, TaN, Ti or TiN, and the thickness is 15nm to 25 nm.
The bottom electrode material layer 420 may be formed over the dielectric layer 410 and the plug 411 using a process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD).
Referring to fig. 5, a magnetic tunnel junction material layer 430 is formed on the bottom electrode layer 420.
The magnetic tunnel junction material layer 430 serves as a subsequent formation of more than two Magnetic Tunnel Junction (MTJ) structures by etching.
The formation process of the magnetic tunnel junction material layer 430 includes a Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD) process.
The magnetic tunnel junction material layer 430 includes: a first magnetic material layer 431, a barrier material layer 432 over the first magnetic material layer 431, and a second magnetic material layer 433 over the barrier material layer 432. In this embodiment, the first magnetic material layer 431 is a reference material layer, and the second magnetic material layer 433 is a free material layer.
In addition, when the first magnetic material layer 431 is a reference material layer and the second magnetic material layer 433 is a free material layer, the magnetic tunnel junction material layer 430 may further include a pinning material layer below the reference material layer, or may further include a seed material layer below the pinning material layer, and may further include a capping material layer above the free material layer.
In other embodiments, the first magnetic material layer 431 is a free material layer, and the second magnetic material layer 433 is a reference material layer. When the first magnetic material layer 431 is a free material layer and the second magnetic material layer 433 is a reference material layer, the magnetic tunnel junction material layer 430 may further include a pinned material layer on the reference material layer and a seed layer under the free material layer.
Referring to fig. 6, a patterned hard mask layer 440 is formed over the magnetic tunnel junction material layer 430.
The hard mask layer 440 serves as a mask for etching the magnetic tunnel junction material layer 430 and the bottom electrode material layer 420.
In this embodiment, the hard mask layer 440 includes a metal hard mask layer 441 and a dielectric hard mask layer 442 located on the metal hard mask layer 441. Wherein the metal hard mask layer 441 is made of Ta, TaN, Ti or TiN and has a thickness of 450nm to 700 nm; the material of the dielectric hard mask layer 442 comprises SiO2 or SiN, and the thickness is 500 nm-800 nm.
The step of forming the patterned hard mask layer 440 may comprise: forming a metal hard mask material layer over the magnetic tunnel junction material layer 430 and a dielectric hard mask material layer over the metal hard mask material layer; forming a patterned photoresist layer on the dielectric hard mask material layer; and sequentially etching the dielectric hard mask material layer and the metal mask material layer by taking the patterned photoresist layer as a mask until the top surface of the magnetic tunnel junction structure material layer 430 is exposed to form a patterned metal hard mask layer 441 and a patterned dielectric hard mask layer 442, namely forming the patterned hard mask layer 440.
Referring to fig. 7, the second magnetic material layer 433 and the barrier material layer 432 are patterned by using the patterned hard mask layer 440 as a mask until the surface of the first magnetic material layer 431 is exposed, and a second magnetic layer and a barrier layer are formed, wherein sidewalls of the second magnetic layer and the barrier layer have a residual magnetic layer.
The second magnetic layer is formed by etching the second magnetic material layer 433 and the barrier layer is formed by etching the barrier material layer 432.
In this embodiment, when the first magnetic material layer is a reference material layer and the second magnetic material layer is a free material layer, the first magnetic layer is a reference layer and the second magnetic layer is a free layer, and specifically, the patterned hard mask layer 440 is used as a mask to pattern the free material layer and the barrier material layer 432 to expose the surface of the reference material layer, so as to form the free layer and the barrier layer.
In this embodiment, in order to obtain a more precise morphology of the magnetic tunnel junction structure, the second magnetic material layer 433 ' and the barrier material layer 432 are etched by a first ion beam etching process with an etching angle of 20 ° to 45 ° and an energy of 80eV to 800eV, so as to form a second magnetic layer 433 ' and a barrier layer 432 '. In other embodiments, the etching process to form the second magnetic layer 433 'and the barrier layer 432' can also be a Reactive Ion Etching (RIE) process.
During the etching process to form the second magnetic layer 433 'and the barrier layer 432', the magnetic material of the second magnetic material layer 433 may be deposited on the sidewall of the barrier layer 432 'or possibly on the sidewall of the second magnetic layer 433', or even on the sidewall of the hard mask layer 440, so as to form the residual magnetic layer 450.
It is noted that, in the process of forming the second magnetic layer 433 'and the barrier layer 432', the first magnetic material layer 431 is used as an etching stop layer, and the residual magnetic layer 450 formed by re-deposition only comes from the second magnetic material layer 433, and does not include the residual magnetic layer re-deposited in the process of etching the first magnetic material layer 431, so that the number of the residual magnetic layers 450 formed by re-deposition is small, and the subsequent removal is easy.
Secondly, since the second magnetic material layer and the barrier material layer and the first magnetic material layer 431 are patterned to serve as etching stop layers, at this time, the second magnetic material layer and the barrier material layer are etched but the first magnetic material layer and the bottom electrode material layer are not etched, so that the etching thickness is reduced, the depth of the position of the residual magnetic layer 450 is not too large, the shielding effect in the residual magnetic removing process can be reduced subsequently, and the residual magnetic layer is easy to remove. In this embodiment, during the process of forming the second magnetic layer 433 'and the barrier layer 432', a part of the dielectric hard mask layer 442 is also etched and removed, and only the remaining part of the dielectric hard mask layer 442 remains on the metal hard mask layer 441.
In this embodiment, before patterning the second magnetic material layer and the barrier material layer, the method further includes: and etching the covering material layer to form a covering layer. Specifically, before patterning the second magnetic material layer and the barrier material layer, the hard mask layer 440 is used as a mask to etch the cover material layer, so as to form a cover layer.
Referring to fig. 8, the residual magnetic layer 450 is etched away.
In this embodiment, the residual magnetic layer 450 on the sidewall of the barrier layer 432' is completely removed by a second ion beam etching process with an etching angle of 50 ° to 80 ° and an energy of 20eV to 200 eV. In other embodiments, the residual magnetic layer 450 may also be etched away using a reactive ion etching process.
It should be noted that, when the sidewalls of the second magnetic layer 433 'and the sidewalls of the metal hard mask layer 441 and the sidewalls of the dielectric hard mask layer 442 also have the residual magnetic layers, the etching process for removing the residual magnetic layers 450 on the sidewalls of the barrier layer 432' further includes etching the residual magnetic layers on the sidewalls of the second magnetic layer 433 'and the sidewalls of the hard mask layer 440, so as to further reduce the possibility that the residual magnetic layers are redeposited on the sidewalls of the barrier layer 432', and thus reduce the risk of short circuit.
In this embodiment, the residual magnetic layer is removed by etching using the hard mask layer as a mask.
Referring to fig. 9, after the residual magnetic layer 450 is etched away, a first protective layer 460 is formed on the sidewalls of the second magnetic layer 433 'and the barrier layer 432'.
The first protection layer 460 may also be located on the sidewalls of the dielectric hard mask layer 442 and the sidewalls of the metal hard mask layer 441. In other embodiments, the first protection layer 460 does not cover the sidewalls of the dielectric hard mask layer 442 and the sidewalls of the metal hard mask layer 441.
In a specific implementation, after performing the step of etching to remove the residual magnetic layer 450, the sidewalls of the dielectric hard mask layer 442, the sidewalls of the metal hard mask layer 441, the sidewalls of the second magnetic layer 433 'and the sidewalls of the barrier layer 432' will be free of magnetic material. To avoid redeposition of magnetic material on the sidewalls of the barrier layer 432 ' during subsequent etching of the first magnetic material layer and the bottom electrode material layer, a first protective layer 460 is formed on the sidewalls of the second magnetic layer 433 ' and the sidewalls of the barrier layer 432 '.
In the embodiment of the present invention, the first protection layer 460 is made of SiN or SiCN, and has a thickness of 10nm to 30 nm.
The method of forming the first protective layer 460 may include: forming a first protective material layer on sidewalls of the second magnetic layer 433 ' and the barrier layer 432 ', on a top of the second magnetic layer 433 ', and on a surface of the exposed first magnetic material layer 431; and etching to remove the first protective material layer covering the top of the second magnetic layer and the surface of the first magnetic material layer, and only remaining the first protective material layer on the side wall of the second magnetic layer 433 'and the side wall of the barrier layer 432', thereby forming the first protective layer 460.
The process for forming the first protective material layer comprises an atomic layer deposition process or a chemical vapor deposition process. The process for removing the top of the second magnetic layer and the first protective material layer on the surface of the first magnetic material layer by etching comprises a third ion beam etching process or a reactive ion etching process.
In this embodiment, in the step of forming the first protective material layer, the first protective material layer further covers the top and sidewalls of the dielectric hard mask layer 442 and the sidewalls of the metal hard mask layer 441. In the process of removing the first protective material layer covering the top of the second magnetic layer and the surface of the first magnetic material layer by etching, the first protective material layer on the sidewall of the dielectric hard mask layer 442 and the sidewall of the metal hard mask layer 441 is remained.
Referring to fig. 10, after the first protective layer 460 is formed, the first magnetic material layer 431 and the bottom electrode material layer 420 are etched using the first protective layer 460 as a mask to form a first magnetic layer 431' and a bottom electrode layer 425.
The first magnetic layer 431' is formed by etching the first magnetic material layer 431, and the bottom electrode layer 425 is formed by etching the bottom electrode material layer 420.
In this embodiment, the etching process for forming the first magnetic layer 431' and the bottom electrode layer 425 is a third plasma beam etching process with an etching angle of 50 ° to 80 ° and energy of 80eV to 800eV, so as to obtain a more precise morphology of the magnetic tunnel junction structure.
During the above-mentioned process of continuing to etch the first magnetic material layer 431 and the bottom electrode material layer 420, a portion of the hard mask layer 440 and a portion of the first protective layer are also removed together. In this embodiment, when the hard mask layer includes a dielectric hard mask layer 441 and a metal hard mask layer 442, in the process of continuously etching the first magnetic material layer 431 and the bottom electrode material layer 420, the dielectric hard mask layer 442 and a part of the metal hard mask layer 441 and a part of the first protection layer 460 are etched and removed together. In other embodiments, during the process of continuously etching the first magnetic material layer 431 and the bottom electrode material layer 420, all of the first protection layer 460 is etched away together.
When the magnetic tunnel junction material layer 435 includes a pinning material layer and a seed material layer, in the process of etching the first magnetic material layer 431 and the bottom electrode material layer 420 with the first protection layer 460 as a mask, the method further includes: and a step of etching the pinning material layer using the first protective layer 460 as a mask to form the pinning layer and the seed layer.
In this embodiment, the magnetic tunnel junction structure 435 includes a first magnetic layer 431 ', a second magnetic layer 433 ', and a barrier layer 432 '.
When the magnetic tunnel junction material layer 430 includes a pinning material layer, a capping material layer, and a seed material layer, the magnetic tunnel junction structure 435 further includes a capping layer, a pinning layer, and a seed layer. Referring to fig. 11, a second protective layer 470 covering sidewalls of the first magnetic layer 431 ', the barrier layer 432', the second magnetic layer 433 ', and the bottom electrode layer 425, a top of the second magnetic layer 433', and a substrate surface is formed.
Specifically, in this embodiment, the second protective layer 470 is formed on the top and sidewalls of the metal hard mask layer 441, the sidewalls of the magnetic tunnel junction structure 435, and the sidewalls of the bottom electrode layer 425, and the exposed surface of the dielectric layer 410.
The second protection layer 470 is used to form a shielding effect on the top and the sidewall of the hard mask layer 440, the sidewall of the magnetic tunnel junction structure 435, the sidewall of the bottom electrode layer 425, and the exposed top surface of the dielectric layer 410, so as to prevent the magnetic tunnel junction structure 435 from being damaged by a subsequent etching process, for example, prevent the magnetic tunnel junction structure 435 from being damaged by a subsequent cleaning process.
In the embodiment of the present invention, the second protection layer 470 is made of the same material as the first protection layer, such as SiN or SiCN. In other embodiments, the second protective layer 470 is a different material than the first protective layer.
In one embodiment, the thickness of the second protective layer 470 is 10nm to 30 nm.
The process of forming the second protective layer 470 may include a Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD) process.
In this embodiment, when the first protection layer 460 having a remaining partial thickness is located on the sidewall of the metal hard mask layer 441 and the sidewall of the magnetic tunnel junction structure 435, the second protection layer 470 further covers the first protection layer 460. In other embodiments, when the first protective layer of the sidewalls of the metal hard mask layer 441 and the magnetic tunnel junction structure 435 is completely etched away, the second protective layer covers the sidewalls of the first magnetic layer 431 ', the barrier layer 432', the second magnetic layer 433 'and the bottom electrode layer 425, the top of the second magnetic layer 433', and the exposed surface of the dielectric layer 410.
According to the scheme in the embodiment of the invention, the second magnetic material layer and the barrier material layer in the magnetic tunnel junction structure layer are patterned at first, and the etching of the first magnetic material layer in the magnetic tunnel junction structure layer is stopped, so that the quantity of the magnetic materials redeposited on the side wall of the partial magnetic tunnel junction structure can be reduced, the depth of the residual magnetic layer is not too large, the shielding effect in the residual magnetic removing process is reduced, and the residual magnetic layer is easy to clean; and simultaneously, after the residual magnetic layer is removed by etching, forming a first protective layer on the side walls of the second magnetic layer and the barrier layer, and etching the first magnetic material layer and the bottom electrode material layer by taking the first protective layer as a mask to form a first magnetic layer and a bottom electrode layer. In the process of etching the first magnetic material layer and the bottom electrode material layer, the barrier layer is isolated by the first protective layer, so that the magnetic material redeposited in the etching process can be prevented from covering the side wall of the barrier layer, the magnetic material deposited on the side wall of the barrier layer can be prevented from being in direct contact with the barrier layer, short circuit is avoided, and the performance of the MRAM device can be improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (16)
1. A method of forming an MRAM device, comprising:
providing a substrate;
forming a bottom electrode material layer and a magnetic tunnel junction material layer on the bottom electrode material layer on the substrate, the magnetic tunnel junction material layer including a first magnetic material layer, a barrier material layer on the first magnetic material layer, and a second magnetic material layer on the barrier material layer;
patterning the second magnetic material layer and the barrier material layer until the surface of the first magnetic material layer is exposed, and forming a second magnetic layer and a barrier layer, wherein the side wall of the second magnetic layer and the side wall of the barrier layer are provided with residual magnetic layers;
etching to remove the residual magnetic layer;
after the residual magnetic layer is removed by etching, forming a first protective layer on the side walls of the second magnetic layer and the barrier layer;
and etching the first magnetic material layer and the bottom electrode material layer by taking the first protective layer as a mask to form a first magnetic layer and a bottom electrode layer.
2. The method of claim 1, wherein the process of patterning the second magnetic material layer and the barrier material layer comprises a first ion beam etching process; the etching angle of the first ion beam etching process is 20-45 degrees, and the energy is 80-800 eV.
3. The method of claim 1, wherein the process of etching away the residual magnetic layer comprises a second ion beam etching process; the etching angle of the second ion beam etching process is 50-80 degrees, and the energy is 20 eV-200 eV.
4. The method of claim 1, wherein the first magnetic material layer is a reference material layer, and the second magnetic material layer is a free material layer; the first magnetic layer is a reference layer, and the second magnetic layer is a free layer.
5. The method of forming an MRAM device of claim 4, wherein the magnetic tunnel junction material layer further comprises a capping material layer located above the free material layer and a pinned material layer located below the reference material layer;
prior to patterning the second magnetic material layer and the barrier material layer, the method further comprises: etching the covering material layer to form a covering layer;
the method further comprises the following steps: and etching the pinning material layer by taking the first protective layer as a mask to form a pinning layer in the process of etching the first magnetic material layer and the bottom electrode material layer by taking the first protective layer as a mask.
6. The method of claim 1, wherein during the etching of the first magnetic material layer and the bottom electrode material layer using the first protective layer as a mask, a portion of the first protective layer is removed by etching, or the entire first protective layer is removed by etching.
7. The method of forming an MRAM device of claim 1, further comprising:
before patterning the second magnetic material layer and the barrier material layer, forming a hard mask layer on the magnetic tunnel junction material layer, wherein the hard mask layer comprises a metal hard mask layer and a medium hard mask layer positioned on the metal hard mask layer;
patterning the second magnetic material layer and the barrier material layer by using the hard mask layer as a mask;
and etching and removing the residual magnetic layer by taking the hard mask layer as a mask.
8. The method of claim 7, wherein a material of the dielectric hard mask layer comprises SiO2Or SiN with a thickness of 500 nm-800 nm;
the metal hard mask layer is made of Ta, TaN, Ti or TiN, and the thickness of the metal hard mask layer is 450 nm-700 nm.
9. The method of forming an MRAM device of claim 1, wherein the step of forming the first protective layer comprises:
forming a first protective material layer on the sidewalls of the second magnetic layer and the barrier layer, the top of the second magnetic layer, and the surface of the first magnetic material layer;
and etching and removing the top of the second magnetic layer and the first protective material layer on the surface of the first magnetic material layer to form the first protective layer.
10. The method of claim 9, wherein the process of forming the first protective material layer comprises an atomic layer deposition process or a chemical vapor deposition process.
11. The method of claim 9, wherein the process of etching away the top of the second magnetic layer and the first protective material layer over the surface of the first magnetic material layer comprises a third ion beam etching process or a reactive ion etching process.
12. The method of claim 1, wherein the first protective layer comprises SiN or SiCN and has a thickness of 10nm to 30 nm.
13. The method of forming an MRAM device of claim 1, further comprising, after forming the first magnetic layer and the bottom electrode layer:
and forming a second protective layer covering the side walls of the first magnetic layer, the barrier layer, the second magnetic layer and the bottom electrode layer, the top of the second magnetic layer and the surface of the substrate.
14. The method of claim 13, wherein a material of the second protective layer is the same as or different from a material of the first protective layer.
15. The method of claim 13, wherein the second protective layer has a thickness of 10nm to 30 nm.
16. The method of claim 1, wherein the bottom electrode layer comprises Ta, TaN, Ti or TiN and has a thickness of 15nm to 25 nm.
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1740396A (en) * | 2004-08-03 | 2006-03-01 | 三星电子株式会社 | Etching solution and utilization comprise that the process of this solution forms the method for semiconducter device |
US20180033959A1 (en) * | 2015-02-04 | 2018-02-01 | Everspin Technologies, Inc. | Magnetoresistive Stack/Structure and Method of Manufacturing Same |
CN109273595A (en) * | 2017-07-18 | 2019-01-25 | 恩智浦有限公司 | The method for forming tunnel magnetoresistive (TMR) element and TMR sensor element |
CN110061029A (en) * | 2018-01-19 | 2019-07-26 | 上海磁宇信息科技有限公司 | A kind of magnetic RAM memory unit and its manufacturing method |
-
2020
- 2020-03-26 CN CN202010223192.8A patent/CN113451353B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1740396A (en) * | 2004-08-03 | 2006-03-01 | 三星电子株式会社 | Etching solution and utilization comprise that the process of this solution forms the method for semiconducter device |
US20180033959A1 (en) * | 2015-02-04 | 2018-02-01 | Everspin Technologies, Inc. | Magnetoresistive Stack/Structure and Method of Manufacturing Same |
CN109273595A (en) * | 2017-07-18 | 2019-01-25 | 恩智浦有限公司 | The method for forming tunnel magnetoresistive (TMR) element and TMR sensor element |
CN110061029A (en) * | 2018-01-19 | 2019-07-26 | 上海磁宇信息科技有限公司 | A kind of magnetic RAM memory unit and its manufacturing method |
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