CN114256142A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN114256142A CN114256142A CN202011019323.7A CN202011019323A CN114256142A CN 114256142 A CN114256142 A CN 114256142A CN 202011019323 A CN202011019323 A CN 202011019323A CN 114256142 A CN114256142 A CN 114256142A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, forming a discrete channel structure on the substrate of the device region, forming a power supply track line in the substrate of the power supply track region, forming a grid structure crossing the channel structure on the substrate, forming an active drain doping region in the channel structure at two sides of the grid structure, and forming an interlayer dielectric layer on the substrate at the side part of the grid structure and the power supply track line; forming a conductive through hole penetrating through the interlayer dielectric layer on part of the power supply track line to expose the power supply track line; filling a protective layer in the conductive through hole; forming an interconnection groove penetrating through the interlayer dielectric layer at the top of the source-drain doped region, wherein the side wall of the interconnection groove is exposed out of the protective layer; and forming a conductive plug positioned in the conductive through hole and a source-drain interconnection layer positioned in the interconnection groove, wherein the source-drain interconnection layer is in contact with the side wall of the conductive plug. The embodiment of the invention is beneficial to increasing the process window for forming the conductive through hole and the interconnection groove.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
The logic chip is composed of standard cells. The size of the standard cell depends on the metal pitch, standard cell height, polysilicon pitch, and whether it is a Single Diffusion Barrier (SDB) or a Double Diffusion Barrier (DDB). Chip scaling has been driven by Metal Pitch (MP) and Polysilicon Pitch (PP) scaling for many years, but MP scaling faces the challenges of lithographic process limitations and resistance increase. And polysilicon pitch scaling has been slowed due to device problems. The introduction of design process co-optimization (DTCO) makes compressing standard cell height a major scaling option. As the cell height is scaled down, the number of fins per cell per single device is also gradually reduced, which will also result in a reduction in drive current.
The widths of the power supply rails (Vdd and Vss) of the standard cell are typically weighted to be within the value of MP. The power rails provide power to the various components of the chip and are typically provided by metal layers in Back End of Line (BEOL) processes. However, the power rails take up more space.
To meet the demands of continuous logic chip scaling, and to optimize Power supply capability when the metal spacing is very tight, one current approach is to move the Power Rails down into the Si substrate to form Buried Power Rails (BPR).
In the buried power rail structure, the power rail is buried in the substrate and extends into a Shallow Trench Isolation (STI) module, thereby facilitating the release of interconnected wiring resources. Moreover, the buried power rail provides a lower resistance local current distribution for techniques that increase BEOL resistance with pitch scaling. In addition, the buried power rail is also beneficial to reducing the influence of wiring congestion and resistance degradation on VDD, VSS, grid-shaped distribution of word lines and bit lines, and improving the writing margin and reading speed.
In devices with embedded power rail structures, it is also often necessary to connect out the embedded power rails using conductive plugs. However, forming a conductive plug (Via-BPR) for electrically connecting a buried power rail currently presents a significant challenge.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which are advantageous to increase a process window for forming a conductive Via and an interconnection trench, and correspondingly increase a process window for forming a conductive plug (Via-BPR) for electrically connecting an embedded power rail.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a device area and a power supply track area, a discrete channel structure is formed on the substrate in the device area, a power supply track line is formed in the substrate in the power supply track area, the extension direction of the power supply track line is parallel to the extension direction of the channel structure, a grid structure crossing the channel structure is formed on the substrate, source and drain doped areas are formed in the channel structures on two sides of the grid structure, and interlayer dielectric layers covering the source and drain doped areas are formed on the substrate on the side part of the grid structure and the power supply track line; forming a conductive through hole penetrating through the interlayer dielectric layer on part of the power supply track line to expose the power supply track line; filling a protective layer in the conductive through hole; forming an interconnection groove penetrating through the interlayer dielectric layer at the top of the source-drain doped region, wherein the side wall of the interconnection groove exposes out of the protective layer along the extension direction of the gate structure; and forming a conductive plug which is positioned in the conductive through hole and is contacted with the power supply track line, and a source-drain interconnection layer which is positioned in the interconnection groove and is contacted with the source-drain doped region, wherein the source-drain interconnection layer is contacted with the side wall of the conductive plug.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate including a device region and a power rail region; the channel structure is separated on the substrate of the device region; the power supply track line is positioned in the substrate of the power supply track area, and the extension direction of the power supply track line is parallel to the extension direction of the channel structure; a gate structure located on the substrate and spanning the channel structure; the source-drain doped region is positioned in the channel structures at two sides of the grid structure; the interlayer dielectric layer is positioned on the substrate at the side part of the grid structure and covers the source drain doped region; the conductive through hole penetrates through the interlayer dielectric layer positioned on part of the power supply track line and exposes the power supply track line; the protective layer is filled in the conductive through hole; and the interconnection groove penetrates through the interlayer dielectric layer at the top of the source-drain doped region, and the side wall of the interconnection groove is exposed out of the protective layer along the extension direction of the grid structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the embodiment of the invention, a conductive through hole is formed firstly, a protective layer is filled in the conductive through hole, and then an interconnection groove is formed; therefore, in the step of forming the conductive through hole, the photoetching and etching processes are carried out on the flat top surface, so that the process window for forming the conductive through hole is increased; the protective layer is filled in the conductive through hole, so that a flat surface can be provided for the manufacturing process of forming the interconnection groove, the difficulty of photoetching and etching processes for forming the interconnection groove is reduced, and the process window for forming the interconnection groove is enlarged The probability of damage to the power supply rail line is reduced; in summary, the embodiment of the present invention is beneficial to increasing the process window for forming the conductive Via and the interconnection trench, correspondingly improving the consistency of the critical dimension and the profile morphology of the conductive Via, and increasing the process window for forming a conductive plug (Via-BPR) for electrically connecting an embedded power rail, thereby improving the formation quality of the conductive plug and optimizing the performance of the semiconductor structure.
Drawings
Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
FIGS. 6-7 are schematic views of alternative methods for forming semiconductor structures corresponding to various steps;
fig. 8 to 24 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background, forming a conductive plug (Via-BPR) for connecting a buried power rail currently presents a significant challenge.
The reason why forming the conductive plug (Via-BPR) has been more challenging is analyzed in conjunction with a method of forming a semiconductor structure. Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1 and 2, fig. 1 is a top view, and fig. 2 is a cross-sectional view of fig. 1 taken along aa, providing a substrate (not shown), including a device region 10a and a power rail region 10b, the substrate of the device region 10a is formed with a discrete channel structure 1, the substrate of the power supply rail region 10b is formed with a power supply rail line 2, the extending direction of the power supply track line 2 is parallel to the extending direction of the channel structure 1, an isolating layer 3 covering the power supply track line 2 is formed on the substrate exposed out of the channel structure 1, the top surface of the isolation layer 3 is lower than the top surface of the channel structure 1, a gate structure 4 crossing the channel structure 1 is formed on the isolation layer 3, and a source-drain doped region 5 is formed in the channel structure 1 at two sides of the gate structure 4, and an interlayer dielectric layer 6 covering the source-drain doped region 5 is formed on the isolation layer 3 at the side part of the gate structure 4.
Referring to fig. 3, an initial conductive via 7 penetrating through the interlayer dielectric layer 6 above a portion of the power supply rail line 2 and an interconnection trench 8 penetrating above the source-drain doped region 5 are formed, and the interconnection trench 8 is communicated with the initial conductive via 7 along the extending direction of the gate structure 4.
Referring to fig. 4, the isolation layer 3 under the initial conductive via 7 is etched, so that the initial conductive via 7 forms a conductive via 9 exposing the power rail line 2.
The step of etching the isolation layer 3 below the initial conductive via 7 comprises: forming a filling layer (not shown) filled in the initial conductive through hole 7 and the interconnection groove 8, wherein the filling layer is further covered on the interlayer dielectric layer 6 and the gate structure 4; etching the filling layer in the initial conductive through hole 7 and the isolating layer 3 below the initial conductive through hole 7 to form the conductive through hole 9; and removing the filling layer.
Referring to fig. 5, a conductive material is filled in the interconnection trench 8 and the conductive via 9, and a source-drain interconnection layer 81 located in the interconnection trench 8 and a conductive plug 91 located in the conductive via 9 are formed.
In the above method, in the step of forming the filling layer, since the concentrations of the interconnection trenches 8 and the initial conductive through holes 7 of the Dense pattern Area (Dense Area) and the sparse pattern Area (ISO Area) are different, the number of the interconnection trenches 8 and the initial conductive through holes 7 of the sparse pattern Area is smaller than the number of the interconnection trenches 8 and the initial conductive through holes 7 of the Dense pattern Area, and in the step of forming the filling layer, the filling rate of the filling layer in the sparse pattern Area is higher than that in the Dense pattern Area, and therefore, the top surface of the filling layer in the sparse pattern Area is higher than that in the Dense pattern Area, the difference in the height uniformity of the top surface of the filling layer in the Dense pattern Area is large, and in the step of etching the filling layer in the Dense pattern Area and the isolation layer 3 under the initial conductive through holes 7, the thickness of the filling layer in the Dense pattern Area is different, the etching time and the etching amount of the isolation layer 3 in the regions with different pattern densities are different, so that the consistency of the opening size and the profile appearance of the conductive through hole 9 in the regions with different pattern densities is poor, the consistency of the key size and the profile appearance of the formed conductive plug 91 is poor, and the process window for forming the Via-BPR is small.
There is also a method of forming the conductive plug. Fig. 6 to 7 are schematic structural diagrams corresponding to steps in another method for forming a semiconductor structure. The method is not repeated again in the same places as the method, and the method is different from the method in that:
referring to fig. 6, after providing a substrate (not shown), a channel structure (not shown), a power supply rail line 11, an isolation layer 12, a gate structure 13, a source-drain doped region 14, and an interlayer dielectric layer 15, a conductive via 16 penetrating through a portion of the interlayer dielectric layer 15 and the isolation layer 12 on top of the power supply rail line 11 is formed.
Referring to fig. 7, after the conductive via 16 is formed, an interconnection trench 17 penetrating through the interlayer dielectric layer 15 on the top of the source-drain doped region 14 is formed.
However, in the above method, in the step of forming the interconnection trench 17 penetrating through the interlayer dielectric layer 15 on the top of the source-drain doped region 14, the conductive Via 16 is exposed in an etching process environment, and re-etching (double etch) is easily caused on the sidewall and the bottom of the conductive Via 16, so that it is difficult to control the opening size and the depth of the conductive Via 16, which results in poor consistency of the profile morphology and the opening size of the conductive Via 16, and also easily causes damage to the power track line 11 at the bottom of the conductive Via 16, and it is difficult to form the Via-BPR.
In order to solve the technical problem, in the method for forming the semiconductor structure provided by the embodiment of the invention, a conductive through hole is formed first, a protective layer is filled in the conductive through hole, and then an interconnection groove is formed; therefore, in the step of forming the conductive through hole, the photoetching and etching processes are carried out on the flat top surface, so that the process window for forming the conductive through hole is increased; the protective layer is filled in the conductive through hole, so that a flat surface can be provided for the manufacturing process of forming the interconnection groove, the difficulty of photoetching and etching processes for forming the interconnection groove is reduced, and the process window for forming the interconnection groove is enlarged The probability of damage to the power supply rail line is reduced; in summary, the embodiment of the present invention is beneficial to increasing the process window for forming the conductive Via and the interconnection trench, correspondingly improving the consistency of the critical dimension and the profile morphology of the conductive Via, and increasing the process window for forming a conductive plug (Via-BPR) for electrically connecting an embedded power rail, thereby improving the formation quality of the conductive plug and optimizing the performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 8 to 24 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 8 to 10, fig. 8 is a top view, fig. 9 is a cross-sectional view along AA of fig. 8, fig. 10 is a cross-sectional view at BB of fig. 8, and a substrate 100 is provided, which includes a device region I and a power rail region II, a discrete channel structure 110 is formed on the substrate 100 of the device region I, a power rail line 120 is formed in the substrate 100 of the power rail region II, an extending direction of the power rail line 120 is parallel to an extending direction of the channel structure 110, a gate structure 140 crossing the channel structure 110 is formed on the substrate 100, active and drain doped regions 150 are formed in the channel structures 110 at two sides of the gate structure 140, and an interlayer dielectric layer 160 covering the active and drain doped regions 150 is formed on the substrate 100 at the side of the gate structure 140.
The substrate 100 is used to provide a process platform for subsequent processing.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The substrate 100 of the device region I is used to form transistors, such as: one or both of a PMOS transistor and an NMOS transistor.
As an example, the channel structure 110 is a fin. Accordingly, a fin field effect transistor (FinFET) is formed on the substrate 100 in the device region I. In this embodiment, the material of the fin is the same as that of the substrate 100, and the material of the fin is silicon. In other embodiments, the material of the fin may be a semiconductor material suitable for forming the fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin may also be different from that of the substrate.
In other embodiments, the channel structure is spaced apart from the substrate, the channel structure includes one or more spaced apart channel layers, and the gate structure covers a portion of the top of the channel structure and surrounds the channel layers. Accordingly, a Gate All Around (GAA) transistor or a fork gate transistor (forkheet) may be formed on the substrate of the device region.
The power rail region II is used to form a power rail line 120. Power rail lines 120 are used to provide power to the various components of the chip. In this embodiment, the Power rail Line 120 is located in the substrate 100 of the Power rail region II, the Power rail Line 120 is a Buried Power Rail (BPR), which is beneficial to releasing wiring resources of Back-End interconnection, and is beneficial to reducing the height of a standard cell, so as to meet the requirement of continuous logic chip miniaturization, and in addition, the Buried Power rail adopts pitch miniaturization and increases the technology of Back End of Line (BEOL) resistance, and is also beneficial to providing lower resistance local current distribution.
The power rail line 120 is a long strip-shaped structure, an extending direction (as shown by x direction in fig. 8) of the power rail line 120 is parallel to the extending direction of the channel structure 110, and a space is formed between the power rail line 120 and the channel structure 110.
The material of the power supply rail line 120 is a conductive material. In this embodiment, the material of the power supply rail line 120 is a metal material including one or more of Co, W, Ni, and Ru. The resistivity of the material of the power rail line 120 is low, which is beneficial to improving RC delay and increasing the processing speed of the chip.
In this embodiment, an insulating layer 125 is further formed between the sidewall of the power supply rail line 120 and the substrate 100, and the insulating layer 125 is used to insulate the power supply rail line 120 from the device region I substrate 100. Therefore, the material of the insulating layer 125 is an insulating material, such as: silicon oxide, silicon oxynitride, silicon nitride, or the like.
In this embodiment, an isolation layer 130 covering the power rail line 120 is further formed on the substrate 100 exposed by the channel structure 110, and a top surface of the isolation layer 130 is lower than a top surface of the channel structure 110.
The isolation layer 130 is used to isolate the adjacent channel structures 110, and the isolation layer 130 is also used to isolate the substrate 100 from the gate structure 140. In this embodiment, the channel structure 110 is a Fin portion, a portion of the Fin portion exposed out of the isolation layer 130 is used as an Active Fin portion (Active Fin) for providing a conductive channel when the device operates.
In this embodiment, the isolation layer 130 is a Shallow Trench Isolation (STI) structure, and the isolation layer 130 is made of an insulating material, for example: one or more of silicon oxide, silicon oxynitride, and silicon nitride.
The gate structure 140 serves as a device gate for controlling the conduction channel to be turned on or off during device operation. In the present embodiment, the gate structure 140 is a metal gate structure.
In the present embodiment, the gate structure 140 is located on the isolation layer 130. The extending direction of the gate structure 140 (as shown in the y-direction in fig. 8) is perpendicular to the extending direction of the channel structure 110 and the power supply rail line 120.
In this embodiment, a gate capping layer 145 is further formed on top of the gate structure 140. When an interconnection groove penetrating through the interlayer dielectric layer 160 on the top of the source-drain doped region 150 is formed subsequently, the gate cap layer 145 is used for protecting the top of the gate structure 140, so that the probability of damage to the gate structure 140 and short circuit between the gate structure 140 and the source-drain interconnection layer is reduced.
The gate capping layer 145 is made of a material having an etching selectivity with the interlayer dielectric layer 160, so as to ensure that the gate capping layer 145 can protect the gate structure 110. In this embodiment, the material of the gate capping layer 145 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate capping layer 145 is silicon nitride.
In this embodiment, a sidewall spacer 170 is further formed on the sidewalls of the gate structure 140 and the gate capping layer 145.
The sidewall 170 is used to define a formation position of the source-drain doped region 150, the sidewall 170 is located on a sidewall of the gate structure 140 and is also used to protect the sidewall of the gate structure 140, in addition, a source-drain interconnection layer penetrating through the interlayer dielectric layer 160 and contacting with the source-drain doped region 150 is formed subsequently, and the sidewall 170 is located between the source-drain interconnection layer and the gate structure 140 and is also used to isolate the source-drain interconnection layer from the gate structure 140.
In this embodiment, the material of the sidewall spacer 170 is a low-k dielectric material or an ultra-low-k dielectric material, so that the effective capacitance between the source-drain interconnection layer and the gate structure 140 is favorably reduced.
In this embodiment, for convenience of illustration and description, only the sidewall 170 is illustrated in fig. 9.
The source drain doped region 150 is used to provide a source of carriers when the device is in operation. When an NMOS device is formed, N-type ions are doped in the source-drain doped region 150; when forming a PMOS device, the source drain doped region 150 is doped with P-type ions. In this embodiment, the source-drain doped region 150 is located in the channel structure 110 at two sides of the gate structure 140 and the sidewall 170.
In this embodiment, along the extending direction of the gate structure 140, the source-drain doped regions 150 located in the plurality of channel structures 110 are in contact with each other (as shown in fig. 8 and 10).
The interlevel dielectric layer 160 serves to isolate adjacent devices. The interlayer dielectric layer 160 is made of an insulating material, and includes: one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 160 is made of silicon oxide.
In this embodiment, the interlayer dielectric layer 160 covers the sidewall of the sidewall 170, and the interlayer dielectric layer 160 is located on the isolation layer 130 at the side of the gate structure 140.
In this embodiment, a Contact Etch Stop Layer (CESL) (not shown) is further formed between the source-drain doped region 150 and the interlayer dielectric Layer 160 and between the isolation Layer 130 and the interlayer dielectric Layer 160. In the subsequent step of forming the interconnection trench, the contact etch stop layer is used for temporarily defining the stop position of etching, so as to improve the uniformity of etching and reduce the probability of damaging the source/drain doped region 150. In this embodiment, the contact etch stop layer is made of silicon nitride.
Referring to fig. 11 to 13, fig. 11 is a top view, fig. 12 is a cross-sectional view taken along direction AA of fig. 11, and fig. 13 is a cross-sectional view taken at position BB of fig. 11, wherein a conductive via 180 is formed through an interlayer dielectric layer 160 located on a portion of the power supply rail line 120, exposing the power supply rail line 120.
The conductive via 180 provides a spatial location for a subsequent formation of a conductive plug in contact with the power rail line 120. In this embodiment, the conductive via 180 penetrates through a portion of the interlayer dielectric layer 160 and the isolation layer 130 on top of the power rail line 120.
In this embodiment, the conductive via 180 is formed first, and the step of forming the conductive via 180 includes the processes of performing the photolithography process and the etching process, so that, in the step of forming the conductive via 180, the photolithography process and the etching process are performed on the flat top surface, which is beneficial to increasing the process window for forming the conductive via 180, reducing the difficulty of the photolithography process and the etching process, and correspondingly beneficial to improving the profile controllability of the conductive via 180.
In this embodiment, in the extending direction of the gate structure 140, the conductive through hole 180 is located in the interlayer dielectric layer 160 and the isolation layer 130 at the end of the source-drain doped region 150, so that after an interconnection groove penetrating through the interlayer dielectric layer 160 at the top of the source-drain doped region 150 is formed subsequently, the interconnection groove can be communicated with the conductive through hole 180 in the extending direction of the gate structure 140.
In this embodiment, the step of forming the conductive via 180 includes: forming a planar layer (not shown), an anti-reflection layer (not shown), and a pattern layer (not shown) stacked in sequence from bottom to top on the interlayer dielectric layer 160 and the gate capping layer 145, wherein a pattern opening (not shown) is formed in the pattern layer above a portion of the power rail line 120; sequentially etching the interlayer dielectric layer 160 and the isolation layer 130 along the pattern opening to form a conductive through hole 180 exposing the power rail line 120; and removing the flat layer, the anti-reflection layer and the pattern layer.
The flat layer is used for providing a flat surface for forming the pattern layer, so that the pattern precision of the pattern layer is improved. In this embodiment, the material of the planarization layer is Spin-On Carbon (SOC).
The anti-reflection layer is used for reducing reflection effect during exposure, thereby improving the transfer precision of the pattern. In this embodiment, the Anti-reflective layer is made of a BARC (Bottom Anti-reflective coating) material.
The pattern layer is used as a mask for etching the interlayer dielectric layer 160 and the isolation layer 130.
In this embodiment, the material of the pattern layer is a photoresist, and the process for forming the pattern layer is a photolithography process. In the embodiment, the flat layer and the anti-reflection layer are both formed on the flat surface, so that the thickness consistency of the flat layer and the thickness consistency of the anti-reflection layer are high, and a flat surface is correspondingly provided for forming the pattern layer, thereby being beneficial to improving the pattern transfer precision in the photoetching process, and further improving the pattern precision and the appearance quality of the pattern opening.
In this embodiment, the interlayer dielectric layer 160 and the isolation layer 130 are sequentially etched along the pattern opening by using an anisotropic dry etching process, which is beneficial to improving the profile controllability of etching and the pattern transfer accuracy. The process for removing the flat layer, the anti-reflection layer and the pattern layer comprises one or two of an ashing process and a wet photoresist removing process.
In this embodiment, the following steps further include: the conductive via 180 is filled with a protective layer, and the protective layer is also removed after the formation of the interconnection trench and before the formation of the conductive plug and the source-drain interconnection layer. With combined reference to fig. 14 and fig. 15, fig. 14 is a cross-sectional view based on fig. 12, fig. 15 is a cross-sectional view based on fig. 13, and after the conductive via 180 is formed and before the protective layer is formed, the method for forming the semiconductor structure further includes: a pad layer 210 is formed on the bottom and sidewalls of the conductive via 180.
After the protective layer is subsequently filled in the conductive through hole 180, the liner layer 210 is located between the bottom of the protective layer and the power supply rail line 120, and in the subsequent step of removing the protective layer, the liner layer 210 can define the stop position of etching, which is beneficial to improving the consistency of etching, preventing the power supply rail line 120 from being damaged, accurately controlling the opening size and the profile morphology of the conductive through hole 180, and reducing the difficulty of subsequently removing the protective layer.
In this embodiment, the pad layer 210 is further formed on the interlayer dielectric layer 160 and the gate capping layer 145.
In this embodiment, the material of the liner layer 210 is a dielectric material, the material of the liner layer 210 is different from the material of the power supply rail line 120, and in the subsequent process of removing the liner layer 210 located at the bottom of the conductive through hole 180, the liner layer 210 can have a higher etching selection ratio, which is beneficial to ensuring the protective effect of the liner layer 210 on the power supply rail line 120, and is correspondingly beneficial to preventing damage to the power supply rail line 120 and reducing the process difficulty of removing the liner layer 210 located at the bottom of the conductive through hole 180. In addition, in this embodiment, the material of the subsequent protection layer includes a metal material, and the material of the liner layer 210 is a dielectric material, so that it is ensured that the liner layer 210 and the protection layer have a higher etching selectivity ratio in the subsequent protection layer removal process, and accordingly it is ensured that the liner layer 210 can play a role in defining an etching stop position.
The material of the liner layer 210 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride. As an example, the material of the pad layer 210 is silicon nitride.
The thickness of the pad layer 210 should not be too small, otherwise the effect of the pad layer 210 for defining the etching stop position and the protection effect on the power rail line 120 are easily reduced; the thickness of the liner layer 210 should not be too large, otherwise the remaining space and the remaining opening size of the conductive via 180 are too small, which may increase the difficulty of filling the passivation layer in the conductive via 180. For this reason, in the present embodiment, the thickness of the pad layer is 2nm to 5 nm.
In this embodiment, the process of forming the liner layer 210 includes an atomic layer deposition process. The atomic layer deposition has a high step coverage capability, so that the liner layer 210 is easily formed at the bottom and the sidewall of the conductive via 180, and the thickness uniformity and the density of the liner layer 210 are improved.
Referring to fig. 16 and 17, fig. 16 is a sectional view based on fig. 14, and fig. 17 is a sectional view based on fig. 15, in which a protective layer 200 is filled in the conductive via 180.
By filling the protective layer 200 in the conductive through hole 180, a flat surface can be provided for a subsequent process of forming the interconnection groove, which is beneficial to reducing the difficulty of photoetching and etching processes for forming the interconnection groove and increasing the process window for forming the interconnection groove, and moreover, the protective layer 200 can also play a role in protecting the power supply track line 120 and the conductive through hole 180 in the process of forming the interconnection groove, thereby being beneficial to accurately controlling the opening size and the profile morphology of the conductive through hole 180 and reducing the probability of damage to the power supply track line 120.
In this embodiment, the protection layer 200 is also used to occupy a space for a subsequent formation of a conductive plug.
In this embodiment, the top surface of the protection layer 200 is flush with the top surfaces of the interlayer dielectric layer 160 and the gate capping layer 145. In this embodiment, the protection layer 200 is formed on the pad layer 210.
In this embodiment, the material of the protection layer 200 includes a metal material. After the protective layer 200 is formed, the exposed top surface of the semiconductor structure includes the top surface of the interlayer dielectric layer 160, the top surface of the gate cap layer 145 and the top surface of the sidewall 170, the materials of the interlayer dielectric layer 160, the gate cap layer 145 and the sidewall 170 are all non-metal materials, specifically, the materials of the interlayer dielectric layer 160, the gate cap layer 145 and the sidewall 170 are all dielectric materials, and a high etching selection ratio is easily realized between the non-metal materials and the metal materials, so that the protective layer 200 is made of the metal materials, and thus the protective layer 200 is not easily subjected to false etching in the subsequent process of forming the interconnection trench. Moreover, in the embodiment, the protection layer 200 is also removed subsequently, so that in the subsequent process of removing the protection layer 200, the erroneous etching of other film layer structures (such as the interlayer dielectric layer 160, the gate cap layer 145 and the sidewall 170) is not easily caused, which is not only beneficial to improving the protection effect of the protection layer 200 on the conductive via 180 and the power supply rail line 120, but also beneficial to reducing the process difficulty of subsequently removing the protection layer 200, and in addition, the metal material has certain mechanical strength, and is easy to form a flat and high-smoothness surface through a planarization process, thereby being beneficial to improving the height consistency of the top surfaces of the protection layer 200, the interlayer dielectric layer 160 and the gate cap layer 145, so as to provide a flat surface for forming the interconnection trench.
Specifically, the material of the protection layer 200 includes one or more of W, Co, Ru, Ti, TiN, Ta, TaN, and Ni. As an example, the material of the protective layer 200 is W.
In other embodiments, in the step of forming the protective layer, a material of the protective layer is a conductive material, and the protective layer is in contact with the power supply rail line; the step of forming the conductive plug thereby comprises: using the protective layer in the conductive via as a conductive plug. In this embodiment, in order to reduce the resistance of the conductive plug to reduce the RC delay, the material of the protective layer is a material having low resistivity, and includes one or more of W, Co, Ru, and Ni.
In this embodiment, the step of forming the protection layer 200 includes: forming a protective material layer (not shown) in the conductive via 180, wherein the protective material layer further covers the interlayer dielectric layer 160; and removing the protective material layer higher than the top surface of the interlayer dielectric layer 160 by using a planarization process, wherein the residual protective material layer in the conductive through hole 180 is used as the protective layer 200.
The process for forming the protective material layer comprises one or more processes of physical vapor deposition, chemical vapor deposition and electrochemical plating. In this embodiment, a chemical vapor deposition process is used to form the protective material layer.
In this embodiment, the protective material layer is formed on the liner layer 210, and in the step of removing the protective material layer higher than the top surface of the interlayer dielectric layer 160, the liner layer 210 higher than the top surface of the interlayer dielectric layer 160 is also removed, so as to expose the top surface of the interlayer dielectric layer 160, thereby facilitating the subsequent etching of the interlayer dielectric layer 160 to form an interconnection trench exposing the source-drain doped region 150, and in the same step, the protective material layer and the liner layer 210 higher than the top surface of the interlayer dielectric layer 160 are removed, which is also beneficial to improving the process integration degree.
In this embodiment, the planarization process includes a chemical mechanical planarization process. The chemical mechanical planarization process is a global planarization process, and is beneficial to reducing the difficulty of removing the protective material layer higher than the top surface of the interlayer dielectric layer 160, and improving the height consistency of the planarized protective material layer, the top surfaces of the interlayer dielectric layer 160 and the gate cap layer 145, so as to provide a surface with high flatness for the subsequent formation of the interconnection groove.
Referring to fig. 18 to 20, fig. 18 is a top view, fig. 19 is a cross-sectional view taken along direction AA of fig. 18, fig. 20 is a cross-sectional view taken along position BB of fig. 18, an interconnection trench 220 is formed to penetrate through the interlayer dielectric layer 160 on top of the source-drain doped region 150, and the protection layer 200 is exposed from the sidewall of the interconnection trench 220 along the extending direction of the gate structure 140. The interconnect trench 220 is used to provide a spatial location for forming source and drain interconnect layers.
As can be seen from the foregoing, in the present embodiment, the protective layer 200 is filled in the conductive via 180, so as to provide a flat surface for the process of forming the interconnection groove 220, which is beneficial to reducing the difficulty of the photolithography and etching process for forming the interconnection groove 220, increasing the process window for forming the interconnection groove 220, and correspondingly improving the consistency of the profile morphology and the consistency of the opening size of the interconnection groove 220. Moreover, compared with the scheme of forming the interconnection groove first and then forming the conductive through hole, the embodiment is also favorable for avoiding the problem that the difference of the etching rate and the etching time of the conductive through hole is large due to the large height difference of the top surfaces of the filling layers filled in the interconnection groove in different pattern concentration areas, and correspondingly is favorable for improving the consistency of the opening size and the profile appearance of the conductive through hole 180.
Along the extending direction of the gate structure 140, the protective layer 200 is exposed from the side wall of the interconnection groove 220, so that after the protective layer 200 is subsequently removed, and the source-drain interconnection layer located in the interconnection groove 220 and the conductive plug located in the conductive through hole 180 are formed, the source-drain interconnection layer can be in contact with the side wall of the conductive plug, and further, the source-drain interconnection layer and the conductive plug are electrically connected.
In this embodiment, the interconnection groove 220 further penetrates through a portion of the liner layer 210 located on the sidewall of the protection layer 200, so as to expose a portion of the sidewall of the protection layer 200.
In this embodiment, the step of forming the interconnection groove 220 includes: forming a metal hard mask layer 230 (as shown in fig. 20) on the interlayer dielectric layer 160, wherein a mask opening 240 (as shown in fig. 20) located above the source-drain doped region 150 is formed in the metal hard mask layer 230; and etching the interlayer dielectric layer 160 below the mask opening 240 by taking the metal hard mask layer 230 as a mask.
The metal hard mask layer 230 is used as a mask for etching the interlayer dielectric layer 160. In this embodiment, the metal hard mask layer 230 is made of TiN.
In this embodiment, the step of forming the metal hard mask layer 230 includes: forming a hard mask material layer (not shown) on the interlayer dielectric layer 160, the gate capping layer 145 and the protection layer 200; forming an organic mask layer on the hard mask material layer; and patterning the hard mask material layer by taking the organic mask layer as a mask.
In this embodiment, the hard mask material layer is formed on a flat surface, so that a process window for patterning the hard mask material layer to form the metal hard mask layer 230 is large, which is beneficial to improving the precision of pattern transfer and correspondingly improving the consistency of the opening size and the profile shape of the mask opening 240.
In this embodiment, the metal hard mask layer 230 is used as a mask, and an anisotropic dry etching process is used to etch the interlayer dielectric layer 160 below the mask opening 240.
The method for forming the semiconductor structure further comprises the following steps: the metal hard mask layer 230 is removed.
Referring to fig. 21 and 22 in combination, fig. 21 is a cross-sectional view based on fig. 19, fig. 22 is a cross-sectional view based on fig. 20, and in this embodiment, the method for forming the semiconductor structure further includes: the protective layer 200 is removed to expose the conductive via 180 in preparation for the subsequent formation of a conductive plug in contact with the power rail line 120.
In this embodiment, the protection layer 200 is exposed in the etching environment for forming the interconnect trench 220, the surface smoothness and the interface quality of the protection layer 200 are relatively low, and the protection layer 200 is removed in order to improve the formation quality of the conductive plug and improve the contact performance between the conductive plug and the source-drain interconnect layer.
In this embodiment, in the step of removing the protection layer 200, the conductive via 180 is exposed, and the conductive via 180 is communicated with the interconnection groove 220.
In this embodiment, the method for forming the semiconductor structure further includes: in the step of removing the protection layer 200, the metal hard mask layer 230 is removed.
By removing the metal hard mask layer 230 and the protection layer 200 in the same step, the process for removing the protection layer 200 is compatible with the existing process, which is beneficial to improving the process integration degree and simplifying the process flow.
In this embodiment, the process of removing the protection layer 200 and the metal hard mask layer 230 includes a wet etching process; the etching solution of the wet etching process comprises a mixed Solution (SPM) of concentrated sulfuric acid and hydrogen peroxide.
The SPM solution has a very high corrosion to metals and metal-containing compound materials, so that the passivation layer 200 and the metal hard mask layer 230 can be removed, and the SPM solution can have a high etching selectivity to other layers (e.g., the interlayer dielectric layer 160, the pad layer 210, and the source/drain doped region 150).
It should be noted that, in this embodiment, the solution temperature of the concentrated sulfuric acid is 50 ℃ to 200 ℃, so that the protective layer 200 and the metal hard mask layer 230 are ensured to have a high etching rate, and damage to the device due to an excessively high temperature is prevented.
In this embodiment, after the passivation layer 200 is removed, the pad layer 210 at the bottom and the sidewall of the conductive via 180 is exposed. Therefore, with combined reference to fig. 23 and 24, fig. 23 is a cross-sectional view based on fig. 21, fig. 24 is a cross-sectional view based on fig. 22, and after removing the protective layer 200, the method for forming a semiconductor structure further includes: the liner layer 210 at the bottom of the conductive via 180 is removed to expose the top surface of the power rail line 120, so that a subsequent conductive plug can contact the power rail line 120.
In this embodiment, the process of removing the pad layer 210 at the bottom of the conductive via 180 includes an anisotropic etching process. By selecting the anisotropic etching process, the liner layer 210 at the bottom of the conductive via 180 can be removed by etching, accordingly, the liner layer 210 at the sidewall of the conductive via 180 is retained, and the liner layer 210 is made of a dielectric material, so that the performance of the semiconductor structure is slightly affected.
Specifically, the anisotropic etching process includes a maskless Dry Etch (Blanket Dry Etch) process. The maskless dry etching process does not need to use a mask, thereby being beneficial to saving the cost and reducing the process complexity.
In other embodiments, the process of removing the liner layer at the bottom of the conductive via includes a wet etching process. The wet etching process has the characteristic of isotropic etching, can remove the liner layers at the bottom and the side wall of the conductive through hole, and has the advantages of small thickness of the liner layer, small difficulty in removing the liner layer and short time required for removing the liner layer.
In particular, in the semiconductor field, before the subsequent formation of the conductive plug and the source/drain interconnection layer, a Pre-clean (Pre-clean) is usually performed on the bottom and the sidewall of the conductive via and the interconnection trench to remove impurities on the surface of the conductive via and the interconnection trench, so as to provide a good surface state for the formation of the conductive plug and the source/drain interconnection layer. The liner layer can be removed in the process of pre-cleaning, which is correspondingly beneficial to improving the process integration degree and the process compatibility.
With continued reference to fig. 23 and 24, a conductive plug 250 located in the conductive via 180 and contacting the power supply rail line 120, and a source-drain interconnect layer 260 located in the interconnect trench 220 and contacting the source-drain doped region 150 are formed, and the source-drain interconnect layer 160 contacts with a sidewall of the conductive plug 250.
As can be seen from the foregoing, the process window for forming the conductive via 180 and the interconnect trench 220 is large, and the consistency of the profile shape and the opening size of the conductive via 180 is high, which is beneficial to improving the consistency of the profile shape and the size of the conductive plug 250, and the consistency of the profile shape and the opening size of the interconnect trench 220 is high, and is also beneficial to improving the consistency of the profile shape and the size of the source-drain interconnect layer 260. In summary, the present embodiment is advantageous for improving the performance of the semiconductor structure.
The conductive plugs 250 contact the power rail lines 120 to make electrical connections between the power rail lines 120 and external circuitry or other interconnect structures. The source-drain interconnection layer 260 is in contact with the source-drain doped region 150, so that the source-drain doped region 150 is electrically connected with an external circuit or other interconnection structures.
In this embodiment, the source-drain interconnection layer 160 contacts with the sidewall of the conductive plug 250, so that the source-drain doped region 150 is electrically connected to the power rail line 120, and the source-drain doped region 150 can be powered by the power rail line 120 when the device is in operation.
In this embodiment, the source-drain interconnection layer 160 and the power rail line 120 are made of the same material, and include one or more of Co, W, Ni, and Ru.
In this embodiment, the steps of forming the conductive plug 250 and the source-drain interconnection layer 260 include: in the same step, conductive materials are filled in the conductive via 180 and the interconnection groove 220 to form a conductive plug 250 located in the conductive via 180 and a source-drain interconnection layer 260 located in the interconnection groove 220.
The conductive plug 250 and the source-drain interconnection layer 260 are formed in the same step, so that the process integration degree is improved, the process is simplified, the conductive plug 250 and the source-drain interconnection layer 260 are integrated, and the contact performance between the conductive plug 250 and the source-drain interconnection layer 260 is correspondingly improved.
In other embodiments, the conductive plug and the source-drain interconnection layer can be formed in different steps according to actual process requirements.
In other embodiments, the protective layer may not be removed when the protective layer is in contact with the power supply rail line and the protective layer is selected to be a material having a low resistivity, depending on the actual process. Accordingly, the step of forming the conductive plug includes: using the protective layer in the conductive via as the conductive plug.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 18 to 20, fig. 18 is a top view, fig. 19 is a cross-sectional view along AA of fig. 18, and fig. 20 is a cross-sectional view at BB of fig. 18, showing a schematic structural view of an embodiment of the semiconductor structure of the present invention.
The semiconductor structure includes: a substrate 100 including a device region I and a power rail region II; a channel structure 110 separated from the substrate 100 in the device region I; a power rail line 120 located in the substrate 100 of the power rail region II, an extending direction of the power rail line 120 being parallel to an extending direction of the channel structure 110; a gate structure 140 located on the substrate 100 and crossing the channel structure 110; the source-drain doped region 150 is positioned in the channel structures 110 at two sides of the gate structure 140; an interlayer dielectric layer 160 located on the substrate 100 at the side of the gate structure 140 and covering the source-drain doped region 150; a conductive via 180 penetrating the interlayer dielectric layer 160 on a portion of the power rail line 120; a protective layer 200 filled in the conductive via 180; the interconnection groove 220 penetrates through the interlayer dielectric layer 160 at the top of the source-drain doped region 150, and the protective layer 200 is exposed out of the side wall of the interconnection groove 220 along the extension direction of the gate structure 140.
The protection layer 200 is filled in the conductive via 180, and can provide a flat surface for the forming process of the interconnect trench 220, so as to be beneficial to reducing the difficulty of the photolithography and etching processes for forming the interconnect trench 220 and increasing the process window for forming the interconnect trench 220 in the forming process of the interconnect trench 220, and the conductive via 180 of the embodiment is formed before the interconnect trench 220, and is also beneficial to avoiding the problem that the difference in the top surface height of the filling layer filled in the interconnect trench in different pattern concentration areas is too large, which results in the large difference in the etching rate and etching time of the conductive via, and is correspondingly beneficial to improving the consistency of the opening size and the profile shape of the conductive via 180, and the protection layer 200 can also play a role in protecting the power rail line 120 and the conductive via 180 in the forming process of the interconnect trench 220, so as to be beneficial to accurately controlling the opening size and the profile shape of the conductive via 180, Reducing the chance of damage to the power rail line 120; in summary, the embodiment is beneficial to increasing the process window for forming the conductive via 180 and the interconnection groove 220, and correspondingly improving the consistency of the critical dimension and the profile morphology of the conductive via 180, thereby improving the formation quality of the conductive plug and optimizing the performance of the semiconductor structure.
The substrate 100 is used to provide a process platform for the fabrication process. In this embodiment, the substrate 100 is a silicon substrate.
The substrate 100 of the device region I is used to form transistors, such as: one or both of a PMOS transistor and an NMOS transistor.
In this embodiment, the number of the channel structures 110 is multiple, and the channel structures 110 are arranged in parallel at intervals. As an example, the channel structure 110 is a fin. Accordingly, a fin field effect transistor (FinFET) is formed on the substrate 100 in the device region I.
In this embodiment, the material of the fin is the same as that of the substrate 100, and the material of the fin is silicon.
In other embodiments, the channel structure is spaced apart from the substrate, the channel structure includes one or more spaced apart channel layers, and the gate structure covers a portion of the top of the channel structure and surrounds the channel layers. Accordingly, a Gate All Around (GAA) transistor or a fork gate transistor (forkheet) may be formed on the substrate of the device region.
Power supply rail region II is used to form power supply rail line 120. Power rail lines 120 are used to provide power to the various components of the chip. In this embodiment, the Power rail Line 120 is located in the substrate 100 of the Power rail region II, the Power rail Line 120 is a Buried Power Rail (BPR), which is beneficial to releasing wiring resources of Back-End interconnection and reducing the height of a standard cell to meet the requirement of continuous logic chip scaling, and in addition, the Buried Power rail adopts a technology of pitch scaling to increase Back-End of Line (BEOL) resistance, and is beneficial to providing lower resistance local current distribution.
The power rail line 120 is a long strip-shaped structure, an extending direction (as shown by x direction in fig. 18) of the power rail line 120 is parallel to an extending direction of the channel structure 110, and a space is formed between the power rail line 120 and the channel structure 110.
The material of the power supply rail line 120 is a conductive material. In this embodiment, the power rail line 120 is made of a metal material including one or more of Co, W, Ni, and Ru. The resistivity of the material of the power rail line 120 is low, which is beneficial to improving RC delay and increasing the processing speed of the chip.
In this embodiment, the semiconductor structure further includes: an insulating layer 125 between a sidewall of the power rail line 120 and the substrate 100, the insulating layer 125 serving to insulate the power rail line 120 from the device region I substrate 100. Therefore, the material of the insulating layer 125 is an insulating material.
In this embodiment, the semiconductor structure further includes: an isolation layer 130 on the substrate 100 exposed by the channel structure 110 and covering the power rail line 120, wherein a top surface of the isolation layer 130 is lower than a top surface of the channel structure 110.
The isolation layer 130 is used to isolate the adjacent channel structures 110, and the isolation layer 130 is also used to isolate the substrate 100 from the gate structure 140. In this embodiment, the channel structure 110 is a fin portion, a portion of the fin portion exposed out of the isolation layer 130 is used as an effective fin portion, and the effective fin portion is used for providing a conductive channel when the device operates.
In this embodiment, the isolation layer 130 is a Shallow Trench Isolation (STI) structure, and the isolation layer 130 is made of an insulating material, for example: one or more of silicon oxide, silicon oxynitride, and silicon nitride.
The gate structure 140 serves as a device gate for controlling the conduction channel to be turned on or off during device operation. In the present embodiment, the gate structure 140 is a metal gate structure.
In the present embodiment, the gate structure 140 is located on the isolation layer 130. The extending direction of the gate structure 140 (as shown in the y-direction in fig. 18) is perpendicular to the extending direction of the channel structure 110 and the power supply rail line 120.
In this embodiment, the semiconductor structure further includes: a gate capping layer 145 on top of the gate structure 140. In the step of forming the interconnection trench 220, the gate capping layer 145 is used for protecting the top of the gate structure 140, so as to reduce the probability that the gate structure 140 is damaged and short-circuit occurs between the gate structure 140 and the source-drain interconnection layer.
The gate capping layer 145 is made of a material having an etching selectivity with the interlayer dielectric layer 160, so as to ensure that the gate capping layer 145 can protect the gate structure 110. The material of the gate capping layer 145 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
In this embodiment, the semiconductor structure further includes: and the side wall 170 is positioned on the side walls of the gate structure 140 and the gate cap layer 145. The sidewall 170 is used to define a formation position of the source-drain doped region 150, the sidewall 170 is further used to protect a sidewall of the gate structure 140, and in addition, after a source-drain interconnection layer is formed in the interconnection trench 220, the sidewall 170 is located between the source-drain interconnection layer and the gate structure 140 and is further used to perform an isolation function between the source-drain interconnection layer and the gate structure 140.
In this embodiment, the material of the sidewall spacer 170 is a low-k dielectric material or an ultra-low-k dielectric material, so that the effective capacitance between the source-drain interconnection layer and the gate structure 140 is favorably reduced. In this embodiment, for convenience of illustration and description, only the sidewall 170 is illustrated in fig. 19.
The source drain doped region 150 is used to provide a source of carriers when the device is in operation. When an NMOS device is formed, N-type ions are doped in the source-drain doped region 150; when forming a PMOS device, the source drain doped region 150 is doped with P-type ions. In this embodiment, the source-drain doped region 150 is located in the channel structure 110 at two sides of the gate structure 140 and the sidewall 170.
In this embodiment, along the extending direction of the gate structure 140, the source-drain doped regions 150 in the plurality of channel structures 110 are in contact with each other.
The interlevel dielectric layer 160 serves to isolate adjacent devices. The material of the interlayer dielectric layer 160 is an insulating material. In this embodiment, the interlayer dielectric layer 160 is made of silicon oxide. In this embodiment, the interlayer dielectric layer 160 covers the sidewalls of the sidewalls 170, and the interlayer dielectric layer 160 is located on the isolation layer 130 at the side of the gate structure 140.
In this embodiment, the semiconductor structure further includes: contact etch stop layers (not shown) are located between the source-drain doped region 150 and the interlayer dielectric layer 160, and between the isolation layer 130 and the interlayer dielectric layer 160. In the step of forming the interconnect trench 220, the contact etch stop layer is used to temporarily define the stop position of the etching, thereby improving the uniformity of the etching and reducing the probability of damage to the source and drain doped regions 150. In this embodiment, the contact etch stop layer is made of silicon nitride.
Conductive via 180 is used to provide a spatial location for the subsequent formation of a conductive plug. In this embodiment, the conductive via 180 penetrates through the interlayer dielectric layer 160 and the isolation layer 130 on top of a portion of the power rail line 120.
In this embodiment, in the extending direction of the gate structure 140, the conductive through hole 180 is located in the interlayer dielectric layer 160 and the isolation layer 130 at the end of the source-drain doped region 150, so that the interconnection groove 220 can communicate with the conductive through hole 180 in the extending direction of the gate structure 140.
The protection layer 200 is filled in the conductive via 180 and is used for providing a flat surface for a forming process of the interconnection groove 220, thereby being beneficial to reducing difficulty of photoetching and etching processes for forming the interconnection groove 220 and increasing a process window for forming the interconnection groove 220, and moreover, in the forming process of the interconnection groove 220, the protection layer 200 can also play a role in protecting the power supply rail line 120 and the conductive via 180, being beneficial to accurately controlling the opening size and the profile morphology of the conductive via 180 and reducing the probability of damage to the power supply rail line 120. The protective layer 200 also occupies a spatial location for the formation of conductive plugs.
Therefore, in this embodiment, the top surface of the protection layer 200 is flush with the top surfaces of the interlayer dielectric layer 160 and the gate capping layer 145.
In this embodiment, the material of the protection layer 200 includes a metal material. The exposed top surfaces of the semiconductor structure include the top surfaces of the interlayer dielectric layer 160, the gate capping layer 145 and the sidewall spacers 170, the materials of the interlayer dielectric layer 160, the gate cap layer 145 and the sidewall spacers 170 are all non-metal materials, specifically, the materials of the interlayer dielectric layer 160, the gate cap layer 145 and the sidewall spacers 170 are all dielectric materials, and a high etching selection ratio is easily realized between the non-metal materials and the metal materials, so that by making the material of the protective layer 200 include the metal materials, so that the protective layer 200 is not easily mis-etched in the formation process of the interconnection groove 220, and in addition, the metal material has a certain mechanical strength, a flat and highly smooth surface is easily formed by the planarization process, thereby advantageously improving the uniformity of the top surface height of the protection layer 200 with respect to the interlevel dielectric layer 160 and the gate capping layer 145 so as to provide a flat surface for forming the interconnect trench 220.
Moreover, in the embodiment, the protection layer 200 is also removed subsequently, so that in the subsequent process of removing the protection layer 200, the wrong etching of other film structures (such as the interlayer dielectric layer 160, the gate cap layer 145 and the sidewall spacers 170) is not easily caused, which is not only beneficial to improving the protection effect of the protection layer 200 on the conductive through hole 180 and the power rail line 120, but also beneficial to reducing the process difficulty of subsequently removing the protection layer 200.
Specifically, the material of the protection layer 200 includes one or more of W, Co, Ru, Ti, TiN, Ta, TaN, and Ni. As an example, the material of the protective layer 200 is W.
In other embodiments, the material of the protective layer is a conductive material, and the protective layer is in contact with the power supply rail line; thereby enabling the protective layer located in the conductive via to be used as a conductive plug. In this embodiment, in order to reduce the resistance of the conductive plug to reduce the RC delay, the material of the protective layer is a material having low resistivity, and includes one or more of W, Co, Ru, and Ni.
In this embodiment, the semiconductor structure further includes: a pad layer 210 between sidewalls of the protection layer 200 and the conductive via 180, and between a bottom of the protection layer 200 and the power rail line 120. Specifically, the pad layer 210 is located between the sidewall of the passivation layer 200 and the sidewall of the interlayer dielectric layer 160, between the sidewall of the passivation layer 200 and the sidewall of the isolation layer 130, and between the bottom of the passivation layer 200 and the power rail line 120.
In this embodiment, in the subsequent step of removing the protection layer 200, the liner layer 210 can define an etching stop position, which is beneficial to improving the etching consistency, preventing the power rail line 120 from being damaged, enabling the opening size and the profile morphology of the conductive through hole 180 to be accurately controlled, and reducing the difficulty of removing the protection layer 200.
In this embodiment, the material of the liner layer 210 is a dielectric material, the material of the liner layer 210 is different from the material of the power supply rail line 120, and in the subsequent process of removing the liner layer 210 located at the bottom of the conductive through hole 180, a higher etching selection ratio can be implemented for the power supply rail line 120, which is beneficial to ensuring the protective effect of the liner layer 210 on the power supply rail line 120, and is correspondingly beneficial to preventing damage to the power supply rail line 120 and reducing the process difficulty of removing the liner layer 210 located at the bottom of the conductive through hole 180. In addition, in this embodiment, the material of the pad layer 210 is different from the material of the protection layer 200, specifically, the material of the protection layer 200 is a metal material, and the material of the pad layer 210 is a dielectric material, so that it is ensured that the pad layer 210 and the protection layer 200 have a higher etching selectivity ratio in a subsequent process of removing the protection layer 200, and accordingly, the pad layer 210 can play a role in defining an etching stop position.
The material of the liner layer 210 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride. As an example, the material of the pad layer 210 is silicon nitride.
The thickness of the pad layer 210 should not be too small, otherwise the effect of the pad layer 210 for defining the etching stop position and the protection effect on the power rail line 120 are easily reduced; the thickness of the liner layer 210 should not be too large, otherwise the remaining space and the remaining opening of the conductive via 180 are too small, which may increase the difficulty of filling the passivation layer 200 in the conductive via 180. For this reason, in the present embodiment, the thickness of the pad layer is 2nm to 5 nm.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (22)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a device area and a power supply track area, a discrete channel structure is formed on the substrate in the device area, a power supply track line is formed in the substrate in the power supply track area, the extension direction of the power supply track line is parallel to the extension direction of the channel structure, a grid structure crossing the channel structure is formed on the substrate, source and drain doped areas are formed in the channel structures on two sides of the grid structure, and interlayer dielectric layers covering the source and drain doped areas are formed on the substrate on the side part of the grid structure and the power supply track line;
forming a conductive through hole penetrating through the interlayer dielectric layer on part of the power supply track line to expose the power supply track line;
filling a protective layer in the conductive through hole;
forming an interconnection groove penetrating through the interlayer dielectric layer at the top of the source-drain doped region, wherein the side wall of the interconnection groove exposes out of the protective layer along the extension direction of the gate structure;
and forming a conductive plug which is positioned in the conductive through hole and is contacted with the power supply track line, and a source-drain interconnection layer which is positioned in the interconnection groove and is contacted with the source-drain doped region, wherein the source-drain interconnection layer is contacted with the side wall of the conductive plug.
2. The method of forming a semiconductor structure of claim 1, further comprising: after the interconnection groove is formed and before the conductive plug and the source drain interconnection layer are formed, removing the protective layer to expose the conductive through hole;
the step of forming the conductive plug includes: and filling a conductive material in the conductive through hole to form the conductive plug positioned in the conductive through hole.
3. The method of forming a semiconductor structure of claim 2, wherein after forming the conductive via and before forming the protective layer, the method of forming a semiconductor structure further comprises: forming a liner layer at the bottom and the side wall of the conductive through hole;
in the step of forming the interconnection groove, the interconnection groove also penetrates through a part of the liner layer positioned on the side wall of the protective layer;
after removing the protective layer and before forming the conductive plug and the source-drain interconnection layer, the method for forming the semiconductor structure further comprises the following steps: and removing the liner layer at the bottom of the conductive through hole to expose the top surface of the power supply rail line.
4. The method of claim 3, wherein the liner layer is formed of a dielectric material.
5. The method of forming a semiconductor structure of claim 3, wherein the liner layer has a thickness of 2nm to 5 nm.
6. The method of claim 3, wherein the process of removing the liner layer at the bottom of the conductive via comprises a wet etching process or an anisotropic dry etching process.
7. The method of forming a semiconductor structure according to claim 2, wherein a material of the protective layer is a metal material; the metal material comprises one or more of W, Co, Ru, Ti, TiN, Ta, TaN and Ni.
8. The method of forming a semiconductor structure according to claim 2, wherein in the step of removing the protective layer, the conductive via is exposed, the conductive via being in communication with the interconnection groove;
the step of forming the conductive plug and the source-drain interconnection layer comprises the following steps: and filling a conductive material in the conductive through hole and the interconnection groove in the same step to form the conductive plug positioned in the conductive through hole and the source-drain interconnection layer positioned in the interconnection groove.
9. The method of forming a semiconductor structure of claim 2, wherein the step of forming the interconnect trench comprises: forming a metal hard mask layer on the interlayer dielectric layer, wherein a mask opening positioned above the source-drain doped region is formed in the metal hard mask layer; etching the interlayer dielectric layer below the mask opening by taking the metal hard mask layer as a mask;
the method for forming the semiconductor structure further comprises the following steps: and in the step of removing the protective layer, removing the metal hard mask layer.
10. The method of claim 9, wherein the process of removing the protective layer and the metal hard mask layer comprises a wet etching process; the etching solution of the wet etching process comprises a mixed solution of concentrated sulfuric acid and hydrogen peroxide.
11. The method of claim 10, wherein the concentrated sulfuric acid has a solution temperature of 50 ℃ to 200 ℃.
12. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the protective layer, a material of the protective layer is a conductive material, and the protective layer is in contact with the power supply rail line;
the step of forming the conductive plug includes: using the protective layer in the conductive via as the conductive plug.
13. The method of forming a semiconductor structure of claim 1, wherein forming the protective layer comprises: forming a protective material layer in the conductive through hole, wherein the protective material layer also covers the interlayer dielectric layer;
and removing the protective material layer higher than the top surface of the interlayer dielectric layer by adopting a planarization process, wherein the residual protective material layer in the conductive through hole is used as the protective layer.
14. The method of claim 1, wherein the channel structure is a fin; or the channel structure and the substrate are arranged at intervals, the channel structure comprises one or more channel layers arranged at intervals, and the grid structure covers part of the top of the channel structure and surrounds the channel layers.
15. The method of forming a semiconductor structure according to claim 1, wherein in the step of providing a substrate, an isolation layer covering the power supply rail line is further formed on the substrate exposed by the channel structure, a top surface of the isolation layer is lower than a top surface of the channel structure, the gate structure is located on the isolation layer, and the interlayer dielectric layer is located on the isolation layer at a side of the gate structure;
in the step of forming the conductive via, the conductive via penetrates through a portion of the interlayer dielectric layer and the isolation layer on the top of the power supply rail line.
16. A semiconductor structure, comprising:
a substrate including a device region and a power rail region;
the channel structure is separated on the substrate of the device region;
the power supply track line is positioned in the substrate of the power supply track area, and the extension direction of the power supply track line is parallel to the extension direction of the channel structure;
a gate structure located on the substrate and spanning the channel structure;
the source-drain doped region is positioned in the channel structures at two sides of the grid structure;
the interlayer dielectric layer is positioned on the substrate at the side part of the grid structure and covers the source drain doped region;
the conductive through hole penetrates through the interlayer dielectric layer positioned on part of the power supply track line and exposes the power supply track line;
the protective layer is filled in the conductive through hole;
and the interconnection groove penetrates through the interlayer dielectric layer at the top of the source-drain doped region, and the side wall of the interconnection groove is exposed out of the protective layer along the extension direction of the grid structure.
17. The semiconductor structure of claim 16, wherein a material of the protective layer comprises a metal material; the metal material comprises one or more of W, Co, Ru, Ti, TiN, Ta, TaN and Ni.
18. The semiconductor structure of claim 17, wherein the semiconductor structure further comprises: a pad layer located between a sidewall of the protection layer and a sidewall of the conductive via, and between a bottom of the protection layer and the power rail line; the liner layer is made of a dielectric material.
19. The semiconductor structure of claim 16, wherein the protective layer is in contact with the power rail line, the protective layer is made of a conductive material, and the protective layer in the conductive via is configured to act as a conductive plug.
20. The semiconductor structure of claim 19, wherein the material of the protective layer comprises one or more of W, Co, Ru, and Ni.
21. The semiconductor structure of claim 16, wherein the channel structure is a fin; or the channel structure and the substrate are arranged at intervals, the channel structure comprises one or more channel layers arranged at intervals, and the grid structure covers part of the top of the channel structure and surrounds the channel layers.
22. The semiconductor structure of claim 16, wherein the semiconductor structure further comprises:
an isolation layer on the substrate exposed from the channel structure and covering the power supply rail line, wherein a top surface of the isolation layer is lower than a top surface of the channel structure;
the grid structure is positioned on the isolation layer;
the interlayer dielectric layer is positioned on the isolation layer at the side part of the grid structure;
the conductive through hole penetrates through the interlayer dielectric layer and the isolation layer at the top of the power supply rail line.
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