CN114256140A

CN114256140A - Semiconductor structure and forming method thereof

Info

Publication number: CN114256140A
Application number: CN202011017177.4A
Authority: CN
Inventors: 呼翔
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-09-24
Filing date: 2020-09-24
Publication date: 2022-03-29

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, a channel structure, a power supply track line, a grid structure, a source-drain doped region and an interlayer dielectric layer; forming conductive vias through the interlevel dielectric layer on a portion of the power rail line, including a bottom via and a top via on the bottom via; forming a bottom plug in the bottom through hole, the bottom plug being in contact with the power rail line; forming a filling medium layer for filling the top through hole on the bottom plug; etching the interlayer dielectric layer and the filling dielectric layer to form an interconnection groove penetrating through the interlayer dielectric layer at the top of the source-drain doped region and expose a top through hole; and filling the top through hole and the interconnection groove to form a top plug which is positioned in the top through hole and is contacted with the bottom plug and a source-drain interconnection layer which is positioned in the interconnection groove and is contacted with the source-drain doped region, wherein the top plug and the bottom plug form a conductive plug. The embodiment of the invention is beneficial to increasing the process window for forming the Via-BPR.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

The logic chip is composed of standard cells. The size of the standard cell depends on the metal pitch, standard cell height, polysilicon pitch, and whether it is a Single Diffusion Barrier (SDB) or a Double Diffusion Barrier (DDB). Chip scaling has been driven by Metal Pitch (MP) and Polysilicon Pitch (PP) scaling for many years, but MP scaling faces the challenges of lithographic process limitations and resistance increase. And polysilicon pitch scaling has been slowed due to device problems. The introduction of design process co-optimization (DTCO) makes compressing standard cell height a major scaling option. As the cell height is scaled down, the number of fins per cell per single device is also gradually reduced, which will also result in a reduction in drive current.

The widths of the power supply rails (Vdd and Vss) of the standard cell are typically weighted to be within the value of MP. The power rails provide power to the various components of the chip and are typically provided by metal layers in Back End of Line (BEOL) processes. However, the power rails take up more space.

To meet the demands of continuous logic chip scaling, and to optimize Power supply capability when the metal spacing is very tight, one current approach is to move the Power Rails down into the Si substrate to form Buried Power Rails (BPR). In the buried power rail structure, the power rail is buried in the substrate and extends into a Shallow Trench Isolation (STI) module, thereby facilitating the release of interconnected wiring resources. Moreover, they provide lower resistance local current distributions for techniques that employ pitch scaling to increase BEOL resistance. In addition, the buried power rail is also beneficial to reducing the influence of wiring congestion and resistance degradation on VDD, VSS, grid-shaped distribution of word lines and bit lines, and improving the writing margin and reading speed.

In devices with embedded power rail structures, it is also often necessary to connect out the embedded power rails using conductive plugs. However, forming a conductive plug (Via-BPR) for electrically connecting a buried power rail currently presents a significant challenge.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which can increase a process window for forming a conductive plug (Via-BPR) for electrically connecting a buried power rail.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a device area and a power supply track area, a discrete channel structure is formed on the substrate in the device area, a power supply track line is formed in the substrate in the power supply track area, the extension direction of the power supply track line is parallel to the extension direction of the channel structure, a grid structure crossing the channel structure is formed on the substrate, source and drain doped areas are formed in the channel structures on two sides of the grid structure, and interlayer dielectric layers covering the source and drain doped areas are formed on the substrate on the side part of the grid structure and the power supply track line; forming a conductive via penetrating through an interlayer dielectric layer on a portion of the power rail line, including a bottom via exposing the power rail line and a top via on the bottom via; forming a bottom plug in contact with the power supply rail line in the bottom through hole, wherein the top surface of the bottom plug is lower than that of the interlayer dielectric layer; forming a filling medium layer for filling the top through hole on the bottom plug; etching the interlayer dielectric layer and the filling dielectric layer to form an interconnection groove penetrating through the interlayer dielectric layer at the top of the source-drain doped region and expose the top through hole, wherein the interconnection groove is communicated with the top through hole along the extension direction of the grid structure; and filling the top through hole and the interconnection groove to form a top plug which is positioned in the top through hole and is contacted with the bottom plug and a source-drain interconnection layer which is positioned in the interconnection groove and is contacted with the source-drain doped region, wherein the top plug and the bottom plug are used for forming a conductive plug.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate including a device region and a power rail region; the channel structure is separated on the substrate of the device region; the power supply track line is positioned in the substrate of the power supply track area, and the extension direction of the power supply track line is parallel to the extension direction of the channel structure; a gate structure located on the substrate and spanning the channel structure; the source-drain doped region is positioned in the channel structures at two sides of the grid structure; the interlayer dielectric layer is positioned on the substrate at the side part of the grid structure and covers the source drain doped region; the conductive plug penetrates through the interlayer dielectric layer above the power supply track line and is in contact with the power supply track line, the conductive plug comprises a bottom plug and a top plug positioned on the bottom plug, and the top surface of the bottom plug is lower than that of the interlayer dielectric layer; and the source-drain interconnection layer penetrates through the interlayer dielectric layer at the top of the source-drain doped region and is in contact with the source-drain doped region, along the extension direction of the grid structure, the source-drain interconnection layer is in contact with the top plug, and the source-drain interconnection layer and the top plug are of an integrated structure.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the method for forming the semiconductor structure provided by the embodiment of the invention, a conductive through hole is formed firstly, the conductive through hole comprises a bottom through hole and a top through hole positioned on the bottom through hole, then a bottom plug is formed in the bottom through hole, the top surface of the bottom plug is lower than the top surface of an interlayer dielectric layer, and a filling dielectric layer for filling the top through hole is formed on the bottom plug, so that a flat surface is provided for photoetching and etching processes for forming an interconnection groove, the process difficulty for forming the interconnection groove is reduced, the process window for forming the interconnection groove is enlarged, the filling dielectric layer can be formed in the top through hole by forming the bottom plug in the bottom through hole, the top surface of the bottom plug is lower than the top surface of the interlayer dielectric layer, and in the step of forming the interconnection groove, the interlayer dielectric layer positioned at the top of the source-drain doped region is etched, the filling dielectric layer on the bottom plug can be etched at the same time, so that the etching difference of forming the interconnection groove and the damage to the source-drain doped region are reduced, the process window for forming the interconnection groove is correspondingly enlarged, the key size and the profile morphology uniformity of the interconnection groove are improved, the process window for forming the conductive plug and the source-drain interconnection layer is further enlarged, the forming quality of the conductive plug and the source-drain interconnection layer is improved, and the performance of the semiconductor structure is improved.

Drawings

Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;

FIGS. 6-7 are schematic views of alternative methods for forming semiconductor structures corresponding to various steps;

fig. 8 to 24 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As can be seen from the background, forming a conductive plug (Via-BPR) for connecting a buried power rail currently presents a significant challenge. The reason why forming the conductive plug (Via-BPR) has been a major challenge is now analyzed in conjunction with a method of forming a semiconductor structure. Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1 and 2, fig. 1 is a top view, fig. 2 is a cross-sectional view of fig. 1 along a direction aa, a substrate (not shown) is provided, and includes a device region 10a and a power rail region 10b, a discrete channel structure 1 is formed on the substrate of the device region 10a, a power rail line 2 is formed in the substrate of the power rail region 10b, an extending direction of the power rail line 2 is parallel to an extending direction of the channel structure 1, an isolation layer 3 covering the power rail line 2 is formed on the substrate exposed by the channel structure 1, a top surface of the isolation layer 3 is lower than a top surface of the channel structure 1, a gate structure 4 crossing the channel structure 1 is formed on the isolation layer 3, a source/drain doped region 5 is formed in the channel structure 1 at two sides of the gate structure 4, and an interlayer dielectric layer 6 covering the source/drain doped region 5 is formed on the isolation layer 3 at a side of the gate structure 4.

Referring to fig. 3, an initial top via 7 penetrating through the interlayer dielectric layer 6 above a portion of the power supply rail line 2 and an interconnection trench 8 penetrating above the source-drain doped region 5 are formed, the interconnection trench 8 and the initial top via 7 communicating in the extending direction of the gate structure 4.

Referring to fig. 4, the isolation layer 3 under the initial top via 7 is etched such that the initial top via 7 forms a top via 9 exposing the power supply rail line 2. The step of etching the isolation layer 3 below the initial top via 7 comprises: forming a filling layer (not shown) filled in the initial top through hole 7 and the interconnection groove 8, wherein the filling layer is also covered on the interlayer dielectric layer 6 and the grid structure 4; etching the filling layer in the initial top through hole 7 and the isolation layer 3 below the initial top through hole 7 to form a top through hole 9; and removing the filling layer.

Referring to fig. 5, a conductive material is filled in the interconnection trench 8 and the top via 9, and a source-drain interconnection layer 81 located in the interconnection trench 8 and a conductive plug 91 located in the top via 9 are formed.

In the above method, since the concentrations of the interconnection trenches 8 and the initial top vias 7 of the Dense pattern Area (Dense Area) and the sparse pattern Area (ISO Area) are different, and the number of the interconnection trenches 8 and the initial top vias 7 of the sparse pattern Area is smaller than the number of the interconnection trenches 8 and the initial top vias 7 of the Dense pattern Area, the filling rate of the filling layer in the sparse pattern Area is higher than the filling rate in the Dense pattern Area in the step of forming the filling layer, and therefore, the top surface of the filling layer in the sparse pattern Area is higher than the top surface of the filling layer in the Dense pattern Area, the difference in the height uniformity of the top surface of the filling layer in the Dense pattern Area is larger, and the thickness of the filling layer in the Dense pattern Area is different from the thickness to be etched in the step of etching the isolation layer 3 below the initial top via 7 and the filling layer in the Dense pattern Area, the etching time and the etching amount of the isolation layer 3 in the regions with different pattern densities are different, so that the consistency of the opening size and the profile shape of the top through hole 9 in the regions with different pattern densities is poor, the consistency of the critical size and the profile shape of the formed conductive plug 91 is poor, and the process window for forming the conductive plug (Via-BPR) for electrically connecting the embedded power rail is small.

There is also a method of forming the conductive plug. Fig. 6 to 7 are schematic structural diagrams corresponding to steps in another method for forming a semiconductor structure. The method is not repeated again in the same places as the method, and the method is different from the method in that:

referring to fig. 6, after providing a substrate (not shown), a channel structure (not shown), a power supply rail line 11, an isolation layer 12, a gate structure 13, a source-drain doped region 14, and an interlayer dielectric layer 15, a top via 16 is formed through a portion of the interlayer dielectric layer 15 on top of the power supply rail line 11 and the isolation layer 12.

Referring to fig. 7, an interconnect trench 17 is formed through the interlayer dielectric layer 15 on top of the source drain doped region 14.

However, in the above method, in the step of forming the interconnection trench 17 penetrating through the interlayer dielectric layer 15 on the top of the source/drain doped region 14, the top Via 16 is exposed in the etching process environment, and re-etching (double etch) is easily caused on the sidewall and the bottom of the top Via 16, so that it is difficult to control the opening size and the depth of the top Via 16, which results in poor uniformity of the profile of the top Via 16 and the opening size, and it is also easy to cause mis-etching on the power rail line 11 at the bottom of the top Via 16, and it is difficult to form the conductive plug (Via-BPR) for electrically connecting the embedded power rail.

In order to solve the technical problem, in the method for forming a semiconductor structure provided by the embodiment of the invention, a conductive through hole is formed, a bottom plug is formed in the bottom through hole, the top surface of the bottom plug is lower than the top surface of an interlayer dielectric layer, and a filling dielectric layer for filling the top through hole is formed on the bottom plug, so that a flat surface is provided for the photoetching and etching process for forming an interconnection groove, the process difficulty for forming the interconnection groove is reduced, the process window for forming the interconnection groove is increased, the filling dielectric layer can be formed in the top through hole by enabling the top surface of the bottom plug to be lower than the top surface of the interlayer dielectric layer, in the step for forming the interconnection groove, the interlayer dielectric layer positioned at the top of the source and drain doped region is etched, the filling dielectric layer positioned on the bottom plug is simultaneously etched, the etching difference for forming the interconnection groove is reduced, and the damage to the source and drain doped region is reduced, the process window for forming the interconnection groove is correspondingly increased, the uniformity of the key size and the profile morphology of the interconnection groove is improved, the process window for forming the conductive plug and the source-drain interconnection layer is further increased, the forming quality of the conductive plug and the source-drain interconnection layer is improved, and the performance of the semiconductor structure is improved.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below. Fig. 8 to 24 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 8 to 10, fig. 8 is a top view, fig. 9 is a cross-sectional view along AA of fig. 8, fig. 10 is a cross-sectional view at BB position of fig. 8, providing a substrate 100 including a device region I and a power rail region II, a discrete channel structure 110 formed on the substrate 100 of the device region I, a power rail line 120 formed in the substrate 100 of the power rail region II, an extending direction of the power rail line 120 being parallel to an extending direction of the channel structure 110, a gate structure 140 formed on the substrate 100 and crossing the channel structure 110, an active drain doped region 150 formed in the channel structure 110 at two sides of the gate structure 140, and an interlayer dielectric layer 160 formed on the substrate 100 at the side of the gate structure 140 and covering the source drain doped region 150.

The substrate 100 is used to provide a process platform for subsequent processing. As an example, the substrate 100 is a silicon substrate. The substrate 100 of the device region I is used to form transistors, such as: one or both of a PMOS transistor and an NMOS transistor.

Channel structure 110 is used to provide a conduction channel for the transistor when the device is in operation. In this embodiment, the number of the channel structures 110 is multiple, and the channel structures 110 are arranged in parallel at intervals.

As an example, the channel structure 110 is a fin. Accordingly, a fin field effect transistor (FinFET) is formed on the substrate 100 in the device region I. In this embodiment, the material of the fin is the same as that of the substrate 100, and the material of the fin is silicon. In other embodiments, the channel structure is spaced apart from the substrate, the channel structure includes one or more spaced apart channel layers, and the gate structure overlies a portion of the top of the channel structure and surrounds the channel layers. Accordingly, a Gate All Around (GAA) transistor or a fork gate transistor (forkheet) may be formed on the substrate of the device region.

Power supply rail region II is used to form power supply rail line 120. Power rail lines 120 are used to provide power to the various components of the chip. In this embodiment, the Power rail Line 120 is located in the substrate 100 of the Power rail region II, the Power rail Line 120 is a Buried Power Rail (BPR), which is beneficial to releasing wiring resources of Back-End interconnection and reducing the height of a standard cell to meet the requirement of continuous logic chip scaling, and in addition, the Buried Power rail adopts the pitch scaling to increase Back-End of Line (BEOL) resistance, which is also beneficial to providing lower resistance local current distribution.

The power rail line 120 is a long strip structure, an extending direction (as shown by x direction in fig. 8) of the power rail line 120 is parallel to the extending direction of the channel structure 110, and a space is formed between the power rail line 120 and the channel structure 110. The material of the power supply rail line 120 is a conductive material. In this embodiment, the material of the power supply rail line 120 is a metal material including one or more of Co, W, Ni, and Ru. The resistivity of the material of the power supply rail line 120 is low, which is advantageous for improving RC delay and increasing the processing speed of the chip.

In this embodiment, an insulating layer 125 is further formed between the sidewall of the power rail line 120 and the substrate 100, and the insulating layer 125 is used to insulate the power rail line 120 from the device region I substrate 100. Thus, the material of the insulating layer 125 is an insulating material, such as: silicon oxide, silicon oxynitride, silicon nitride, or the like.

An isolation layer 130 covering the power rail line 120 is formed on the substrate 100 exposed by the channel structure 110, and a top surface of the isolation layer 130 is lower than a top surface of the channel structure 110. The isolation layer 130 is used to isolate the adjacent channel structures 110, and the isolation layer 130 is also used to isolate the substrate 100 from the gate structure 140. In this embodiment, the channel structure 110 is a Fin portion, a portion of the Fin portion exposed out of the isolation layer 130 is used as an Active Fin portion (Active Fin) for providing a conductive channel when the device operates.

In this embodiment, the isolation layer 130 is a Shallow Trench Isolation (STI) structure, and the isolation layer 130 is made of an insulating material, for example: one or more of silicon oxide, silicon oxynitride, and silicon nitride.

The gate structure 140 serves as a device gate for controlling the conduction channel to be turned on or off during device operation. In the present embodiment, the gate structure 140 is a metal gate structure. In the present embodiment, the gate structure 140 is located on the isolation layer 130. The extending direction of the gate structure 140 (as shown in the y-direction in fig. 8) is perpendicular to the extending direction of the channel structure 110 and the power supply rail line 120.

In this embodiment, a gate capping layer 145 is also formed on top of the gate structure 140. In the subsequent step of forming the through interconnection trench, the gate capping layer 145 is used to protect the top of the gate structure 140, so as to reduce the probability of damage to the gate structure 140 and short-circuiting between the gate structure 140 and the source-drain interconnection layer.

The gate capping layer 145 is made of a material having an etching selectivity with the interlayer dielectric layer 160, so as to ensure that the gate capping layer 145 can protect the gate structure 110. The material of the gate capping layer 145 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate capping layer 145 is silicon nitride.

In this embodiment, a sidewall spacer 170 is further formed on the sidewalls of the gate structure 140 and the gate capping layer 145.

The sidewall 170 is used to define the position of the source-drain doped region 150, the sidewall 170 is also used to protect the sidewall of the gate structure 140, and a source-drain interconnection layer is formed subsequently, and the sidewall 170 is located between the source-drain interconnection layer and the gate structure 140 and is also used to isolate the source-drain interconnection layer from the gate structure 140. In this embodiment, the material of the sidewall spacer 170 is a low-k dielectric material or an ultra-low-k dielectric material, which is beneficial to reducing the effective capacitance between the source-drain interconnection layer and the gate structure 140. In this embodiment, for convenience of illustration and description, only the sidewall 170 is illustrated in fig. 9.

The source drain doped region 150 is used to provide a source of carriers when the device is in operation. When an NMOS device is formed, N-type ions are doped in the source-drain doped region 150; when forming a PMOS device, the source drain doped region 150 is doped with P-type ions. In this embodiment, the source-drain doped region 150 is located in the channel structure 110 at two sides of the gate structure 140 and the sidewall 170. In this embodiment, along the extending direction of the gate structure 140, the source-drain doped regions 150 located in the plurality of channel structures 110 are in contact with each other (as shown in fig. 8 and 10).

The interlevel dielectric layer 160 serves to isolate adjacent devices. The material of the interlayer dielectric layer 160 is an insulating material. In this embodiment, the interlayer dielectric layer 160 is made of silicon oxide. In this embodiment, the interlayer dielectric layer 160 covers the sidewalls of the sidewalls 170, and the interlayer dielectric layer 160 is located on the isolation layer 130 at the side of the gate structure 140.

Referring to fig. 11 to 13, fig. 11 is a top view, fig. 12 is a cross-sectional view of fig. 11 taken along direction AA, and fig. 13 is a cross-sectional view of fig. 11 taken at position BB, forming a conductive via 180 through the interlayer dielectric layer 160 on a portion of the power supply rail line 120, including a bottom via 80 exposing the power supply rail line 120 and a top via 82 on the bottom via 80.

Conductive via 180 is used to provide a spatial location for the subsequent formation of a conductive plug. Wherein, the bottom via 81 is used to provide a space position for forming the bottom plug, and the top via 82 is used to provide a space position for subsequently forming the filling dielectric layer. In this embodiment, the conductive via 180 penetrates through the interlayer dielectric layer 160 and the isolation layer 130 at the top of a portion of the power rail line 120.

In this embodiment, the conductive via 180 is formed first, and the step of forming the conductive via 180 includes the processes of performing the photolithography process and the etching process, so that, in the step of forming the conductive via 180, the photolithography process and the etching process are performed on the flat top surface, which is beneficial to increasing the process window for forming the conductive via 180, reducing the difficulty of the photolithography process and the etching process, and correspondingly beneficial to improving the profile controllability of the conductive via 180.

In this embodiment, the conductive through hole 180 is located in the interlayer dielectric layer 160 and the isolation layer 130 at the end of the source-drain doped region 150 along the extending direction of the gate structure 140, so that after an interconnection groove penetrating through the interlayer dielectric layer 160 at the top of the source-drain doped region 150 is formed subsequently, the interconnection groove can be communicated with the top through hole 82 along the extending direction of the gate structure 140.

In this embodiment, the step of forming the conductive via 180 includes: a planarization layer (not shown), an anti-reflection layer (not shown), and a pattern layer (not shown) are formed on the interlayer dielectric layer 160 and the gate capping layer 145, and the pattern layer is formed with a pattern opening (not shown) above a portion of the power rail line 120; sequentially etching the interlayer dielectric layer 160 and the isolation layer 130 along the pattern opening to form a conductive via 180 exposing the power rail line 120; and removing the flat layer, the anti-reflection layer and the pattern layer.

The flat layer is used for providing a flat surface for forming the pattern layer, so that the pattern precision of the pattern layer is improved. In this embodiment, the material of the planarization layer is Spin-On Carbon (SOC). The anti-reflection layer serves to reduce the reflection effect at the time of exposure, thereby improving the transfer accuracy of the pattern. In this embodiment, the Anti-reflective layer is a Bottom Anti-reflective coating (BARC) material. The patterned layer is used as a mask for etching the interlayer dielectric layer 160 and the isolation layer 130.

In this embodiment, the material of the pattern layer is a photoresist, and the process for forming the pattern layer is a photolithography process. In the embodiment, the flat layer and the anti-reflection layer are both formed on the flat surface, the thickness consistency of the flat layer and the thickness consistency of the anti-reflection layer are high, and the flat surface is correspondingly provided for forming the pattern layer, so that the pattern transfer precision in the photoetching process is improved, and the pattern precision and the appearance quality of the pattern opening are further improved.

In this embodiment, the interlayer dielectric layer 160 and the isolation layer 130 are sequentially etched along the pattern opening by using an anisotropic dry etching process, which is beneficial to improving the profile controllability of etching and the pattern transfer accuracy. And removing the flat layer, the anti-reflection layer and the pattern layer by adopting one or two of an ashing process and a wet photoresist removing process.

Referring to fig. 14 and 15, fig. 14 is a cross-sectional view based on fig. 12, and fig. 15 is a cross-sectional view based on fig. 13, a bottom plug 210 contacting the power rail line 120 is formed in the bottom via 81, and a top surface of the bottom plug 210 is lower than a top surface of the interlayer dielectric layer 160.

By forming the bottom plug 210 in the bottom through hole 81 and making the top surface of the bottom plug 210 lower than the top surface of the interlayer dielectric layer 160, the top through hole 82 can be exposed, a space is reserved for a filling dielectric layer for subsequently forming the filling top through hole 82, a flat surface is further provided for the subsequent photoetching and etching process for forming the interconnection groove, the process difficulty for forming the interconnection groove is reduced, and the process window for forming the interconnection groove is increased. Moreover, the bottom plug 210 is formed in the bottom through hole 81, and the top surface of the bottom plug 210 is lower than the top surface of the interlayer dielectric layer 160, so that a filling dielectric layer can be formed in the top through hole 82 subsequently, and accordingly, in the step of forming the interconnection groove subsequently, not only the interlayer dielectric layer 160 at the top of the source-drain doped region 150 is etched, but also the filling dielectric layer can be etched simultaneously, which is beneficial to reducing the etching difference when the interconnection groove is formed, and reducing the damage to the source-drain doped region 150, correspondingly increasing the process window for forming the interconnection groove, and improving the uniformity of the key size and the profile morphology of the interconnection groove, so that the process window for forming the conductive plug and the source-drain interconnection layer is increased, the formation quality of the conductive plug and the source-drain interconnection layer is improved, and the performance of the semiconductor structure is improved.

The bottom plug 210 is used to form a conductive plug with a subsequent top plug, which is used to make an electrical connection between the power rail line 120 and an external circuit or other interconnect structure. The material of the bottom plug 210 is a conductive material. In the present embodiment, the material of the bottom plug 210 is a metal material, including one or more of Co, W, Ni, and Ru. The resistivity of the material of the bottom plug 210 is low, which is beneficial to improving the RC delay and increasing the processing speed of the chip.

The distance between the top surface of the bottom plug 210 and the top surface of the source-drain doped region 150 is not too large, otherwise, the effect of reducing the etching difference during forming the interconnection trench and the damage to the source-drain doped region 150 is not obvious in the subsequent process of forming the interconnection trench. Therefore, in the present embodiment, in the process of forming the bottom plug 210, the distance between the top surface of the bottom plug 210 and the top surface of the source/drain doped region 150 is less than or equal to

As an example, the top surface of the bottom plug 210 is flush with the top surface of the source drain doped region 150. Therefore, the top heights of the bottom plug 210 and the source-drain doped region 150 have good consistency, which is beneficial to making the effect of reducing the subsequent etching difference of the formed interconnection groove and the etching damage of the source-drain doped region 150 more obvious.

In this embodiment, the step of forming the bottom plug 210 includes: a bottom plug 210 is formed in the bottom via 81 using a selective deposition process. By using the selective deposition process, the bottom plug 210 can be selectively deposited on the surface of a film layer with strong conductivity (e.g., a metal layer) and a film layer with weak conductivity (e.g., a conductive layer or a dielectric layer with weak conductivity), that is, the bottom plug 210 can be selectively formed on the top surface of the power rail line 120 and on the surface of the interlayer dielectric layer 160 or the gate capping layer 145, so that the bottom plug 210 can be precisely formed on the top surface of the power rail line 120, which correspondingly improves the alignment accuracy of the bottom plug 210 and the power rail line 120. Moreover, during the formation of the bottom plug 210, no etching process is required, simplifying the process steps.

In the present embodiment, the selective deposition process is a selective chemical vapor deposition (selective CVD) process. The selective chemical vapor deposition process has a good selective deposition effect and high process stability.

In other embodiments, the selective deposition process may also be a Selective Electroless Metal Deposition (SEMD) process. By utilizing the SEMD process, the conductive material can be selectively deposited on the surface of the conductive layer with strong conductivity, and the deposition selectivity is also higher.

In other embodiments, the step of forming the bottom plug may further include: forming an initial plug filled in the conductive through hole; and etching back part of the initial plug with the residual initial plug in the bottom through hole as the bottom plug. The process for forming the initial plug comprises one or more of a chemical vapor deposition process, a physical vapor deposition process and an electrochemical plating process. The process of etching back the initial plug of partial thickness includes a dry etch process.

Referring to fig. 16 to 18, fig. 16 is a top view, fig. 17 is a cross-sectional view along AA of fig. 16, and fig. 18 is a cross-sectional view at BB of fig. 16, a filling dielectric layer 190 filling the top via 82 is formed on the bottom plug 210.

By forming the filling dielectric layer 190 filling the top through hole 82, a flat surface can be provided for the subsequent photoetching and etching process for forming the interconnection groove, which is beneficial to reducing the process difficulty for forming the interconnection groove and increasing the process window for forming the interconnection groove, and accordingly, in the subsequent step for forming the interconnection groove, not only the interlayer dielectric layer 160 at the top of the source-drain doped region 150 is etched, but also the filling dielectric layer can be simultaneously etched, which is beneficial to reducing the etching difference when the interconnection groove is formed and the damage to the source-drain doped region 150, so that the process window for forming the interconnection groove is correspondingly increased, and the key size and the uniformity of the profile morphology of the interconnection groove are improved.

The fill dielectric layer 190 is used to occupy space for the subsequent formation of the top plug. The material of the filling dielectric layer 190 is a dielectric material, so that the etching properties of the filling dielectric layer 190 and the interlayer dielectric layer 160 are close to each other, which is correspondingly beneficial to reducing the etching difference when the interconnection groove is formed subsequently, the material of the filling dielectric layer 190 is a dielectric material, the material of the bottom plug 210 is a metal material, a high etching selection ratio is provided between the filling dielectric layer 190 and the bottom plug 210, and in the subsequent etching process of the interlayer dielectric layer 160 at the top of the source-drain doped region 150 and the filling dielectric layer 190 on the bottom plug 210, the etching process is easily stopped on the bottom plug 210, so that the etching process difficulty can be realized, and the etching damage to the source-drain doped region 150 can be reduced. Specifically, the material of the filling dielectric layer 190 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, amorphous silicon, silicon carbide, silicon oxycarbide, and silicon oxycarbonitride. As an example, the material of the filling dielectric layer 190 is the same as the material of the interlayer dielectric layer 160, which is beneficial to further improve the process compatibility.

In other embodiments, the material of the filling Dielectric layer may be one or more of Spin-On Carbon (SOC), amorphous Carbon, Organic Dielectric Layer (ODL), Bottom Anti-reflective Coating (BARC), Silicon-containing Anti-reflective Coating (Si-ARC), Deep UV absorbing Oxide (DUO), Dielectric Anti-reflective Coating (DARC), and Advanced Patterning Film (APF).

In this embodiment, the step of forming the filling dielectric layer 190 includes: forming a dielectric material layer (not shown) filling the top via 82, the dielectric material layer also overlying the interlevel dielectric layer 160; the dielectric material layer above the top surface of the interlayer dielectric layer 160 is removed by a planarization process, and the dielectric material layer remaining in the top via 82 is used as a filling dielectric layer 190.

In this embodiment, the process of forming the dielectric material layer includes one or both of an atomic layer deposition process and a flow-type chemical vapor deposition process. The process of forming the dielectric material layer is a process with strong gap filling capability, so as to improve the filling capability and the filling quality of the filling dielectric layer 190 in the top through hole 82.

In this embodiment, the planarization process includes a chemical mechanical planarization process. The chemical mechanical planarization process is one of global planarization processes, and is beneficial to reducing the difficulty of the planarization process and improving the consistency of the top surface heights of the filling dielectric layer 190 and the interlayer dielectric layer 160, so that a surface with high flatness is provided for the subsequent photoetching and etching process for forming the interconnection groove, and the precision of pattern transfer is correspondingly improved.

Referring to fig. 19 to 21, fig. 19 is a top view, fig. 20 is a cross-sectional view along AA in fig. 19, fig. 21 is a cross-sectional view along BB in fig. 19, the interlayer dielectric layer 160 and the filling dielectric layer 190 are etched to form an interconnection trench 200 penetrating through the interlayer dielectric layer 160 on the top of the source-drain doped region 150 and expose the top via 82, and the interconnection trench 200 is communicated with the top via 82 along the extending direction of the gate structure 140.

In this embodiment, because the bottom plug 210 is formed in the bottom through hole 81, the filling dielectric layer 190 is formed in the top through hole 82, and the height difference between the bottom plug 210 and the top surface of the source-drain doped region 150 is small, not only the interlayer dielectric layer 160 on the top of the source-drain doped region 150 is etched, but also the filling dielectric layer 190 on the bottom plug 210 can be simultaneously etched, which is beneficial to reducing the etching difference for forming the interconnection groove 200 and the etching damage to the source-drain doped region 150, correspondingly increasing the process window for forming the interconnection groove 200, and improving the uniformity of the key size and the profile morphology of the interconnection groove 200.

In this embodiment, the process for etching the interlayer dielectric layer 160 and the filling dielectric layer 190 includes an anisotropic dry etching process. The anisotropic dry etching process has high etching profile controllability and etching precision, and is favorable for improving the precision of pattern transfer.

Referring to fig. 22 to 24, fig. 22 is a top view, fig. 23 is a cross-sectional view along AA of fig. 22, fig. 24 is a cross-sectional view at BB position of fig. 22, the top via 82 and the interconnect trench 200 are filled, and a top plug 220 located in the top via 82 and contacting the bottom plug 210 and a source-drain interconnect layer 230 located in the interconnect trench 200 and contacting the source-drain doped region 150 are formed, the top plug 220 and the bottom plug 210 being used for forming a conductive plug 300.

As can be seen from the foregoing, in the embodiment, the process window for forming the interconnection trench 200 and the conductive via 180 is increased, the uniformity of the critical dimension and the profile morphology of the interconnection trench 200 is improved, the process window for forming the conductive plug 300 and the source-drain interconnection layer 230 is further increased, the formation quality of the conductive plug 300 and the source-drain interconnection layer 230 is improved, and the performance of the semiconductor structure is improved. Moreover, in the present embodiment, the difference in depth between the top via 82 and the interconnection groove 200 is small, and the filling consistency is also improved in the process of filling the top via 82 and the interconnection groove 200.

The conductive plugs 300 are in contact with the power rail lines 120 to make electrical connection between the power rail lines 120 and external circuitry or other interconnect structures. The source-drain interconnect layer 230 contacts the source-drain doped region 150, thereby electrically connecting the source-drain doped region 150 to an external circuit or other interconnect structure.

In this embodiment, the top through hole 82 is communicated with the interconnection groove 200, so that the top through hole 82 and the interconnection groove 200 are filled, and the formed top plug 220 and the source-drain interconnection layer 230 are of an integrated structure, so that not only the source-drain doped region 150 and the source-drain interconnection layer 120 are electrically connected, but also the source-drain doped region 150 can be powered through the source-drain interconnection layer 120 when the device works, and the improvement of the contact performance between the conductive plug 250 and the source-drain interconnection layer 260 is facilitated.

Accordingly, in this embodiment, the material of the top plug 220 and the source-drain interconnect layer 230 is the same. In this embodiment, the material of the top plug 220 and the source-drain interconnection layer 230 includes one or more of W, Co, Ru, and Ni. In this embodiment, the process of forming the top plug 220 and the source-drain interconnection layer 230 includes one or more of a chemical vapor deposition process, a physical vapor deposition process, and an electrochemical plating process.

Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 22 to 24, fig. 22 is a top view, fig. 23 is a cross-sectional view along AA of fig. 22, and fig. 24 is a cross-sectional view at BB of fig. 22, showing a schematic structural view of an embodiment of the semiconductor structure of the present invention.

The semiconductor structure includes: a substrate 100 including a device region I and a power rail region II; a channel structure 110 separated on the substrate 100 of the device region I; a power rail line 120 located in the substrate 100 of the power rail region II, an extending direction (as shown by x direction in fig. 22) of the power rail line 120 being parallel to the extending direction of the channel structure 110; a gate structure 140 located on the substrate 100 and crossing the channel structure 110; source-drain doped regions 150 in the channel structures 110 on both sides of the gate structure 140; an interlayer dielectric layer 160 located on the substrate 100 at the side of the gate structure 140 and covering the source-drain doped region 150; a conductive plug 300 penetrating through the interlayer dielectric layer 160 above the power rail line 120 and contacting the power rail line 120, wherein the conductive plug 300 includes a bottom plug 210 and a top plug 220 located on the bottom plug 210, and a top surface of the bottom plug 210 is lower than a top surface of the interlayer dielectric layer 160; the source-drain interconnection layer 230 penetrates through the interlayer dielectric layer 160 on the top of the source-drain doped region 150 and is in contact with the source-drain doped region 150, the source-drain interconnection layer 230 is in contact with the top plug 220 in the extending direction of the source-gate structure 140, and the source-drain interconnection layer 230 and the top plug 220 are of an integrated structure.

In this embodiment, the conductive plug 300 includes a bottom plug 210 and a top plug 220 located on the bottom plug 210, and the source-drain interconnection layer 230 and the top plug 220 are of an integrated structure, because the conductive via is formed first, and includes a bottom via and a top via located on the bottom via, then the bottom plug 210 is formed in the bottom via, and a filling dielectric layer filling the top via is formed on the bottom plug 210, thereby providing a flat surface for the photolithography and etching process for forming the interconnection trench, which is beneficial to reducing the process difficulty for forming the interconnection trench, increasing the process window for forming the interconnection trench, and in the step of forming the interconnection trench, not only the interlayer dielectric layer 160 located on the top of the source-drain doped region 150 is etched, but also the filling dielectric layer located on the bottom plug 210 is etched at the same time, which is beneficial to reducing the etching difference for forming the interconnection trench, and reducing the damage to the source-drain doped region 150, correspondingly, the process window for forming the interconnection groove is enlarged, the uniformity of the key size and the profile morphology of the interconnection groove is improved, the source-drain interconnection layer 230 is formed in the interconnection groove, the process window for forming the conductive plug 300 and the source-drain interconnection layer 230 is further enlarged, the forming quality of the electrical plug 300 and the source-drain interconnection layer 230 is improved, and the performance of the semiconductor structure is improved.

In this embodiment, the substrate 100 is a silicon substrate. The substrate 100 of the device region I is used to form transistors, such as: one or both of a PMOS transistor and an NMOS transistor.

As an example, the channel structure 110 is a fin. Accordingly, a FinFET is formed on the substrate 100 in the device region I. In this embodiment, the material of the fin is the same as that of the substrate 100, and the material of the fin is silicon. In other embodiments, the channel structure is spaced apart from the substrate, the channel structure includes one or more spaced apart channel layers, and the gate structure overlies a portion of the top of the channel structure and surrounds the channel layers. Accordingly, a GAA transistor or forkshet may be formed on the substrate in the device region.

The power rail line 120 is a strip structure, the extending direction of the power rail line 120 is parallel to the extending direction of the channel structure 110, and a space is formed between the power rail line 120 and the channel structure 110. The material of the power supply rail line 120 is a conductive material. In this embodiment, the material of the power supply rail line 120 is a metal material including one or more of Co, W, Ni, and Ru. The resistivity of the material of the power supply rail line 120 is low, which is advantageous for improving RC delay and increasing the processing speed of the chip.

In this embodiment, the semiconductor structure further includes: and an insulating layer 125 between the sidewall of the power rail line 120 and the substrate 100. The insulating layer 125 serves to isolate the power supply rail line 120 from the device region I substrate 100.

In this embodiment, the semiconductor structure further includes: an isolation layer 130 is disposed on the substrate 100 exposed by the channel structure 110 and covers the power rail line 120, and a top surface of the isolation layer 130 is lower than a top surface of the channel structure 110.

The isolation layer 130 is used to isolate the adjacent channel structures 110, and the isolation layer 130 is also used to isolate the substrate 100 from the gate structure 140. In this embodiment, the channel structure 110 is a fin, a portion of the fin exposed out of the isolation layer 130 is used as an effective fin, and the effective fin is used to provide a conductive channel during device operation. The material of the isolation layer 130 is an insulating material, such as: one or more of silicon oxide, silicon oxynitride, and silicon nitride.

The gate structure 140 serves as a device gate for controlling the conduction channel to be turned on or off during device operation. In the present embodiment, the gate structure 140 is a metal gate structure. In the present embodiment, the gate structure 140 is located on the isolation layer 130. The extending direction of the gate structure 140 (as shown in the y-direction in fig. 22) is perpendicular to the extending direction of the channel structure 110 and the power supply rail line 120.

In this embodiment, the semiconductor structure further includes: a gate capping layer 145 on top of the gate structure 140. In the formation steps of the source-drain interconnection layer 230 and the conductive plug 300, the gate capping layer 145 is used for protecting the top of the gate structure 140, so as to reduce the possibility of damage to the gate structure 140 and short-circuit between the gate structure 140 and the source-drain interconnection layer 230 or the conductive plug 300.

The gate capping layer 145 is selected to have an etch selectivity with the interlayer dielectric layer 160. As an example, the material of the gate capping layer 145 is silicon nitride.

The semiconductor structure further includes: spacers 170 (shown in fig. 23) are located on the sidewalls of the gate structure 140 and the gate cap 145. In this embodiment, the material of the sidewall wall 170 is a low-k dielectric material or an ultra-low-k dielectric material. In this embodiment, for convenience of illustration and description, only the sidewall 170 is illustrated in fig. 23.

The source drain doped region 150 is used to provide a source of carriers when the device is in operation. When an NMOS device is formed, N-type ions are doped in the source-drain doped region 150; when forming a PMOS device, the source drain doped region 150 is doped with P-type ions. In this embodiment, along the extending direction of the gate structure 140, the source-drain doped regions 150 in the plurality of channel structures 110 are in contact with each other.

The interlevel dielectric layer 160 serves to isolate adjacent devices. In this embodiment, the interlayer dielectric layer 160 is made of silicon oxide. In this embodiment, the interlayer dielectric layer 160 covers the sidewalls of the sidewalls 170, and the interlayer dielectric layer 160 is located on the isolation layer 130 at the side of the gate structure 140.

The conductive plugs 300 are in contact with the power rail lines 120 to make electrical connection between the power rail lines 120 and external circuitry or other interconnect structures. In this embodiment, the conductive plug 300 penetrates through the interlayer dielectric layer 160 and the isolation layer 130 at the top of a portion of the power rail line 120.

The top surface of the bottom plug 210 is lower than the top surface of the interlayer dielectric layer 160, so that a top through hole can be exposed, a space is reserved for forming a filling dielectric layer for filling the top through hole on the bottom plug 210, a flat surface is further provided for the photoetching and etching process for forming the source-drain interconnection layer 230, the process difficulty for forming the source-drain interconnection layer 230 is reduced, and the process window for forming the source-drain interconnection layer 230 is increased.

Moreover, by forming the bottom plug 210 in the bottom through hole 81, in the step of forming the interconnection trench, not only the interlayer dielectric layer 160 at the top of the source-drain doped region 150 is etched, but also the filling dielectric layer can be simultaneously etched, which is beneficial to reducing the etching difference when the interconnection trench is formed and reducing the damage to the source-drain doped region 150, correspondingly increasing the process window for forming the interconnection trench, improving the uniformity of the key size and the profile morphology of the interconnection trench, further increasing the process window for forming the conductive plug 300 and the source-drain interconnection layer 230, improving the formation quality of the conductive plug 300 and the source-drain interconnection layer 230, and improving the performance of the semiconductor structure.

The material of the bottom plug 210 is a conductive material. In the present embodiment, the material of the bottom plug 210 is a metal material, including one or more of Co, W, Ni, and Ru. The resistivity of the material of the bottom plug 210 is low, which is beneficial to improving the RC delay and increasing the processing speed of the chip.

The distance between the top surface of the bottom plug 210 and the top surface of the source-drain doped region 150 is not too large, otherwise, the effect of reducing the etching difference during forming the interconnection trench and the damage to the source-drain doped region 150 is not obvious in the process of forming the interconnection trench. Therefore, in the present embodiment, in the process of forming the bottom plug 210, the distance between the top surface of the bottom plug 210 and the top surface of the source/drain doped region 150 is less than or equal to

As an example, the bottom plug 210 is flush with the top surface of the source drain doped region 150. Therefore, the top heights of the bottom plug 210 and the source-drain doped region 150 have good consistency, which is beneficial to making the effect of reducing the etching difference of the formed interconnection groove and the etching damage of the source-drain doped region 150 more obvious.

The top plug 220 and the source-drain interconnection layer 230 are of an integrated structure, so that electrical connection between the source-drain doped region 150 and the power supply rail line 120 is achieved, power can be supplied to the source-drain doped region 150 through the power supply rail line 120 when the device works, and the improvement of the contact performance between the conductive plug 250 and the source-drain interconnection layer 260 is facilitated. In this embodiment, the top plug 220 and the bottom plug 210 are made of the same material.

In this embodiment, the conductive plug 300 is located in the interlayer dielectric layer 160 and the isolation layer 130 at the end of the source-drain doped region 150 along the extending direction of the gate structure 140, so that the conductive plug 300 can contact with the source-drain interconnection layer 230 along the extending direction of the gate structure 140.

The source-drain interconnect layer 230 contacts the source-drain doped region 150, thereby electrically connecting the source-drain doped region 150 to an external circuit or other interconnect structure. Accordingly, in this embodiment, the material of the top plug 220 and the source-drain interconnect layer 230 is the same. In this embodiment, the material of the top plug 220 and the source-drain interconnection layer 230 includes one or more of W, Co, Ru, and Ni.

The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a device area and a power supply track area, a discrete channel structure is formed on the substrate in the device area, a power supply track line is formed in the substrate in the power supply track area, the extension direction of the power supply track line is parallel to the extension direction of the channel structure, a grid structure crossing the channel structure is formed on the substrate, source and drain doped areas are formed in the channel structures on two sides of the grid structure, and interlayer dielectric layers covering the source and drain doped areas are formed on the substrate on the side part of the grid structure and the power supply track line;

forming a conductive via penetrating through an interlayer dielectric layer on a portion of the power rail line, including a bottom via exposing the power rail line and a top via on the bottom via;

forming a bottom plug in contact with the power supply rail line in the bottom through hole, wherein the top surface of the bottom plug is lower than that of the interlayer dielectric layer;

forming a filling medium layer for filling the top through hole on the bottom plug;

etching the interlayer dielectric layer and the filling dielectric layer to form an interconnection groove penetrating through the interlayer dielectric layer at the top of the source-drain doped region and expose the top through hole, wherein the interconnection groove is communicated with the top through hole along the extension direction of the grid structure;

and filling the top through hole and the interconnection groove to form a top plug which is positioned in the top through hole and is contacted with the bottom plug and a source-drain interconnection layer which is positioned in the interconnection groove and is contacted with the source-drain doped region, wherein the top plug and the bottom plug are used for forming a conductive plug.

2. The method of forming a semiconductor structure of claim 1, wherein the step of forming the bottom plug comprises: forming a bottom plug in the bottom via hole by using a selective deposition process;

or forming an initial plug filled in the conductive through hole; and etching back part of the initial plug with the residual initial plug in the bottom through hole as the bottom plug.

3. The method of claim 2, wherein the selective deposition process comprises a selective chemical vapor deposition process or a selective electroless metal deposition process.

4. The method of claim 2, wherein the process of forming the initial plug comprises one or more of a chemical vapor deposition process, a physical vapor deposition process, and an electrochemical plating process.

5. The method of claim 2, wherein the process of back-etching a portion of the thickness of the initial plug comprises a dry etching process.

6. The method for forming a semiconductor structure according to claim 1, wherein in the process of forming the bottom plug, a distance between a top surface of the bottom plug and a top surface of the source-drain doped region is less than or equal to

7. The method for forming a semiconductor structure according to claim 1, wherein a top surface of the bottom plug is flush with a top surface of the source-drain doped region during the forming of the bottom plug.

8. The method of forming a semiconductor structure of claim 1, wherein forming the fill dielectric layer comprises: forming a dielectric material layer filled in the top through hole, wherein the dielectric material layer is also positioned on the interlayer dielectric layer;

and removing the dielectric material layer higher than the top surface of the interlayer dielectric layer by adopting a planarization process, and using the residual dielectric material layer positioned in the top through hole as the filling dielectric layer.

9. The method according to claim 1, wherein the material of the filling dielectric layer comprises one or more of silicon oxide, silicon oxynitride, silicon nitride, amorphous silicon, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, spin-on carbon, amorphous carbon, organic dielectric layer, bottom anti-reflective coating, silicon-containing anti-reflective coating, deep ultraviolet light absorbing oxide layer, dielectric anti-reflective coating, and advanced patterning film.

10. The method of claim 1, wherein the material of the fill dielectric layer is the same as the material of the interlevel dielectric layer.

11. The method of claim 1, wherein the etching the interlevel dielectric layer and the fill dielectric layer comprises an anisotropic dry etch process.

12. The method for forming the semiconductor structure according to claim 1, wherein the process for forming the top plug and the source drain interconnection layer comprises one or more of a chemical vapor deposition process, a physical vapor deposition process and an electrochemical plating process.

13. The method of claim 1, wherein the channel structure is a fin; or the channel structure and the substrate are arranged at intervals, the channel structure comprises one or more channel layers arranged at intervals, and the grid structure covers part of the top of the channel structure and surrounds the channel layers.

14. The method of forming a semiconductor structure according to claim 1, wherein in the step of providing a substrate, an isolation layer covering the power supply rail line is further formed on the substrate exposed by the channel structure, a top surface of the isolation layer is lower than a top surface of the channel structure, the gate structure is located on the isolation layer, and the interlayer dielectric layer is located on the isolation layer at a side of the gate structure;

in the step of forming the conductive via, the conductive via penetrates through a portion of the interlayer dielectric layer and the isolation layer on the top of the power supply rail line.

15. A semiconductor structure, comprising:

a substrate including a device region and a power rail region;

the channel structure is separated on the substrate of the device region;

the power supply track line is positioned in the substrate of the power supply track area, and the extension direction of the power supply track line is parallel to the extension direction of the channel structure;

a gate structure located on the substrate and spanning the channel structure;

the source-drain doped region is positioned in the channel structures at two sides of the grid structure;

the interlayer dielectric layer is positioned on the substrate at the side part of the grid structure and covers the source drain doped region;

the conductive plug penetrates through the interlayer dielectric layer above the power supply track line and is in contact with the power supply track line, the conductive plug comprises a bottom plug and a top plug positioned on the bottom plug, and the top surface of the bottom plug is lower than that of the interlayer dielectric layer;

and the source-drain interconnection layer penetrates through the interlayer dielectric layer at the top of the source-drain doped region and is in contact with the source-drain doped region, along the extension direction of the grid structure, the source-drain interconnection layer is in contact with the top plug, and the source-drain interconnection layer and the top plug are of an integrated structure.

16. The semiconductor structure of claim 15, wherein a distance between a top surface of the bottom plug and a top surface of the source drain doped region is less than or equal to

17. The semiconductor structure of claim 15, wherein a top surface of the bottom plug is flush with a top surface of the source drain doped region.

18. The semiconductor structure of claim 15, wherein the material of the bottom plug comprises one or more of W, Co, Ru, and Ni.

19. The semiconductor structure of claim 15, wherein the channel structure is a fin; or the channel structure and the substrate are arranged at intervals, the channel structure comprises one or more channel layers arranged at intervals, and the grid structure covers part of the top of the channel structure and surrounds the channel layers.

20. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises: an isolation layer on the substrate exposed from the channel structure and covering the power supply rail line, wherein a top surface of the isolation layer is lower than a top surface of the channel structure;

the grid structure is positioned on the isolation layer;

the interlayer dielectric layer is positioned on the isolation layer at the side part of the grid structure;

the conductive plug penetrates through the interlayer dielectric layer and the isolation layer at the top of the power supply rail line.