CN113471245A - MRAM device and method of forming the same - Google Patents
MRAM device and method of forming the same Download PDFInfo
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- CN113471245A CN113471245A CN202010235486.2A CN202010235486A CN113471245A CN 113471245 A CN113471245 A CN 113471245A CN 202010235486 A CN202010235486 A CN 202010235486A CN 113471245 A CN113471245 A CN 113471245A
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
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Abstract
An MRAM device and method of forming the same, the method comprising: providing a substrate; forming a bottom material layer and a magnetic tunnel junction material layer on the bottom material layer on the substrate; imaging the magnetic tunnel junction material layer and stopping at the bottom material layer to enable the magnetic tunnel junction material layer to form a magnetic tunnel junction structure; forming a first dielectric layer on the bottom material layer at the side part of the magnetic tunnel junction structure; forming a top electrode material layer on the first dielectric layer and the magnetic tunnel junction structure; and etching the top electrode material layer, the first dielectric layer and the bottom material layer to form a top electrode layer on the magnetic tunnel junction structure and a bottom electrode layer at the bottom of the magnetic tunnel junction structure. The scheme can avoid direct contact between the magnetic material deposited on the side wall of the barrier layer and the barrier layer, and avoid short circuit, thereby improving the performance of the MRAM device.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to an MRAM device and a method of forming the same.
Background
Semiconductor memory devices are used in semiconductor integrated circuits to provide data storage. Among them, a Magnetic Random Access Memory (MRAM) is a Memory using a Magnetic element.
MRAM is a non-volatile memory that stores data by programming a Magnetic Tunnel Junction (MTJ) that is part of an MRAM bit cell. Data is stored in the MTJ, and the data stored in the MRAM bit cell can remain even when power is turned off.
However, the performance of existing MRAM devices still remains to be improved.
Disclosure of Invention
The invention provides a method for forming an MRAM device to improve the performance of the MRAM device.
To solve the above problems, the present invention provides a method of forming an MRAM device, the method comprising:
providing a substrate;
forming a bottom material layer and a magnetic tunnel junction material layer on the bottom material layer on the substrate;
imaging the magnetic tunnel junction material layer and stopping at the bottom material layer to enable the magnetic tunnel junction material layer to form a magnetic tunnel junction structure;
forming a first dielectric layer on the bottom material layer at the side part of the magnetic tunnel junction structure;
forming a top electrode material layer on the first dielectric layer and the magnetic tunnel junction structure;
and etching the top electrode material layer, the first dielectric layer and the bottom material layer to form a top electrode layer on the magnetic tunnel junction structure and a bottom electrode layer at the bottom of the magnetic tunnel junction structure.
Optionally, the magnetic tunnel junction material layer comprises a pinned material layer located above the bottom material layer, a reference material layer located above the pinned material layer, a barrier material layer located above the reference material layer, and a free material layer located above the barrier material layer; the magnetic tunnel junction structure comprises a pinned layer, a reference layer located on the pinned layer, a barrier layer located on the reference layer, and a free layer located on the barrier layer;
or, the magnetic tunnel junction material layer comprises a free material layer located above the bottom material layer, a barrier material layer located above the free material layer, a reference material layer located above the barrier material layer, and a pinned material layer located above the reference material layer; the magnetic tunnel junction structure includes a free layer, a barrier layer on the free layer, a reference layer on the barrier layer, and a pinned layer on the reference layer.
Optionally, the bottom material layer comprises a bottom electrode material layer and a seed material layer located over the bottom electrode material layer.
Optionally, in the process of patterning the magnetic tunnel junction material layer, the seed material layer is used as an etching stop layer;
the step of etching the top electrode material layer, the first dielectric layer and the bottom material layer comprises: and etching the top electrode material layer, the first dielectric layer, the seed material layer and the bottom electrode material layer to form a bottom electrode layer on the bottom electrode material layer and form a seed layer on the bottom electrode layer on the seed material layer.
Optionally, in the process of patterning the magnetic tunnel junction material layer, the seed material layer is further etched to form a seed layer, and the bottom electrode material layer is used as an etching stop layer.
Optionally, the material of the bottom electrode material layer comprises Ta, TaN, Ti or TiN, and the thickness is 15nm to 25 nm; the seed layer is made of Ta or Ru and has a thickness of 1-5 nm.
Optionally, the method further comprises: forming a protective layer on the side wall of the magnetic tunnel junction structure; the first dielectric layer covers the side wall of the protective layer.
Optionally, the step of forming the protective layer and the first dielectric layer includes: forming a protective material layer on the side wall and the top of the magnetic tunnel junction structure and the surface of the bottom material layer on the side part of the magnetic tunnel junction structure; forming a first dielectric material layer on the protective material layer; and flattening the first medium material layer and the protective material layer until the first medium material layer and the protective material layer on the top of the magnetic tunnel junction structure are removed, so that the first medium material layer forms a first medium layer, and the protective material layer forms a protective layer.
Optionally, the process of forming the protective material layer includes a chemical vapor deposition process or an atomic layer deposition process.
Optionally, the material of the protective layer includes SiN or SiCN, and the thickness is 10nm to 30 nm.
Optionally, the method further comprises: forming a hard mask layer on the magnetic tunnel junction material layer before patterning the magnetic tunnel junction material layer, wherein the hard mask layer comprises a metal hard mask layer and a medium hard mask layer positioned on the metal hard mask layer; and patterning the magnetic tunnel junction material layer by taking the hard mask layer as a mask.
Optionally, the metal hard mask layer material comprises Ta, TaN, Ti or TiN, and the thickness is 450nm to 700 nm; the dielectric hard mask layer material comprises silicon dioxide or silicon nitride, and the thickness is 500 nm-800 nm.
Optionally, the process for etching the top electrode material layer, the first dielectric layer and the bottom material layer is an ion beam etching process or a reactive ion etching process.
Optionally, the etching angle of the ion beam etching process is 20-45 degrees, and the energy is 80-800 eV; the processing gas used by the ion beam etching process comprises Ar, Kr or Xe.
Optionally, the processing gas used in the reactive ion etching process includes CH3OH, CO, NH3, and CH3CH2 OH.
Optionally, the material of the top electrode comprises Ta, TaN, Ti or TiN, and the thickness is 50nm to 100 nm.
Optionally, etching the top electrode material layer, the first dielectric layer and the bottom material layer to form an opening penetrating through the top electrode material layer, the first dielectric layer and the bottom material layer; the method for forming the MRAM device further comprises: and forming a second dielectric layer in the opening and on the top electrode layer.
An embodiment of the present invention further provides an MRAM device, including:
a substrate;
a plurality of discrete bottom electrode layers on the substrate;
magnetic tunnel junction structures respectively located over the bottom electrode layer;
the first dielectric layer is positioned on the substrate at the side part of the magnetic tunnel junction structure, covers the side wall of the magnetic tunnel junction structure, and is higher than the bottom surface of the bottom electrode layer;
top electrode layers respectively located over the magnetic tunnel junction structures;
and the openings are positioned between the adjacent top electrode layers, between the adjacent bottom electrode layers and between the adjacent magnetic tunnel junction structures and penetrate through the first dielectric layer.
Optionally, the MRAM device further comprises: the protective layer is positioned on the side wall of the magnetic tunnel junction structure and also extends to part of the surface of the substrate between the adjacent magnetic tunnel junction structures; the first dielectric layer also covers the protective layer; the opening also penetrates through the protective layer on the surface of the substrate.
Optionally, the material of the protective layer includes SiN or SiCN, and the thickness is 10nm to 30 nm.
Optionally, the MRAM device further comprises: a seed layer located between the bottom electrode layer and the magnetic tunnel junction structure.
Optionally, the bottom surface of the first dielectric layer is higher than the bottom surface of the seed layer; or the bottom surface of the first dielectric layer is higher than the bottom surface of the bottom electrode layer and lower than the bottom surface of the seed layer.
Optionally, the material of the seed layer comprises Ta or Ru, and the thickness is 1 nm-5 nm.
Optionally, the material of the top electrode layer comprises Ta, TaN, Ti or TiN, and the thickness is 50 nm-100 nm; the bottom electrode layer is made of Ta, TaN, Ti or TiN, and the thickness of the bottom electrode layer is 15 nm-25 nm.
Optionally, the MRAM device further comprises: a second dielectric layer in the opening and on the top electrode layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the scheme, the magnetic tunnel junction material layer is patterned and stops at the bottom material layer, so that the magnetic tunnel junction material layer forms a magnetic tunnel junction structure, and a large amount of magnetic materials can be prevented from being deposited on the side wall of the magnetic tunnel junction structure in the process of etching the bottom material layer with larger thickness. After etching to form a magnetic tunnel junction structure, forming a first dielectric layer on a bottom material layer at the side part of the magnetic tunnel junction structure; forming a top electrode material layer on the first dielectric layer and the magnetic tunnel junction structure; and etching the top electrode material layer, the first dielectric layer and the bottom material layer to form a top electrode layer on the magnetic tunnel junction structure and a bottom electrode layer at the bottom of the magnetic tunnel junction structure. In the process of etching the top electrode material layer, the first dielectric layer and the bottom material layer, the first dielectric layer isolates the barrier layer in the magnetic tunnel junction structure, and the magnetic material redeposited in the etching process can be prevented from covering the side wall of the barrier layer, so that the magnetic material deposited on the side wall of the barrier layer can be prevented from being in direct contact with the barrier layer, short circuit is avoided, and the performance of the MRAM device can be improved.
Drawings
Fig. 1 and 2 are schematic diagrams of a method of forming an MRAM device;
FIG. 3 is a flow chart illustrating a method of forming an MRAM device in an embodiment of the invention;
fig. 4 to 10 are schematic intermediate structures corresponding to a method for forming an MRAM device according to an embodiment of the present invention.
Detailed Description
It is known in the art that the performance of the existing MRAM devices is to be improved.
Referring to fig. 1, a substrate 100 is provided having a bottom material layer 110 and a magnetic tunnel junction material layer 120 formed thereon.
Referring to fig. 2, a patterned hard mask layer 130 is formed on the magnetic tunnel junction material layer 120, and the magnetic tunnel junction structure layer 120 and the bottom material layer 110 are etched using the patterned hard mask layer 130 as a mask, thereby forming a bottom electrode 115 and a magnetic tunnel junction structure 125 located above the bottom electrode 115. The hard mask layer 130 includes a metal hard mask layer 131 and a dielectric hard mask layer 132 located on the metal hard mask layer 131.
In the above etching process, the magnetic tunnel junction structure 125 and the bottom electrode 115 are completed in the same etching process. Since the bottom material layer 110 is thicker, the time required for etching the bottom material layer 110 is longer, during the etching process to form the bottom electrode layer 110, a large amount of magnetic material from the bottom material layer 110 may be redeposited on the sidewall of the magnetic tunnel junction structure 125 to form the residual magnetic layer 140, and the residual magnetic layer 140 redeposited on the sidewall of the barrier layer in the magnetic tunnel junction structure 125 may cause short circuit, which seriously affects the performance of the MRAM device.
The embodiment of the invention provides a method for forming an MRAM device, which comprises the following steps: providing a substrate; forming a bottom material layer and a magnetic tunnel junction material layer on the bottom material layer on the substrate; imaging the magnetic tunnel junction material layer and stopping at the bottom material layer to enable the magnetic tunnel junction material layer to form a magnetic tunnel junction structure; forming a first dielectric layer on the bottom material layer at the side part of the magnetic tunnel junction structure; forming a top electrode material layer on the first dielectric layer and the magnetic tunnel junction structure; and etching the top electrode material layer, the first dielectric layer and the bottom material layer to form a top electrode layer on the magnetic tunnel junction structure and a bottom electrode layer at the bottom of the magnetic tunnel junction structure.
In the forming method of the MRAM device provided in the embodiment of the present invention, the magnetic tunnel junction material layer is patterned and stopped at the bottom material layer, so that the magnetic tunnel junction material layer forms a magnetic tunnel junction structure, and a large amount of magnetic materials can be prevented from being redeposited on the side wall of the magnetic tunnel junction structure in the process of etching the bottom material layer with a large thickness. After etching to form a magnetic tunnel junction structure, forming a first dielectric layer on a bottom material layer at the side part of the magnetic tunnel junction structure; forming a top electrode material layer on the first dielectric layer and the magnetic tunnel junction structure; and etching the top electrode material layer, the first dielectric layer and the bottom material layer to form a top electrode layer on the magnetic tunnel junction structure and a bottom electrode layer at the bottom of the magnetic tunnel junction structure. In the process of etching the top electrode material layer, the first dielectric layer and the bottom material layer, the first dielectric layer isolates the barrier layer in the magnetic tunnel junction structure, and the magnetic material redeposited in the etching process can be prevented from covering the side wall of the barrier layer, so that the magnetic material deposited on the side wall of the barrier layer can be prevented from being in direct contact with the barrier layer, short circuit is avoided, and the performance of the MRAM device can be improved.
A method of forming an MRAM device in an embodiment of the present invention will be described in further detail below.
Fig. 3 shows a flow diagram of a method of forming an MRAM device. Referring to fig. 3, a method for forming an MRAM device according to an embodiment of the present invention may specifically include the following steps:
step S301: providing a substrate;
step S302: forming a bottom material layer and a magnetic tunnel junction material layer on the bottom material layer on the substrate;
step S303: imaging the magnetic tunnel junction material layer and stopping at the bottom material layer to enable the magnetic tunnel junction material layer to form a magnetic tunnel junction structure;
step S304: forming a first dielectric layer on the bottom material layer at the side part of the magnetic tunnel junction structure;
step S305: forming a top electrode material layer on the first dielectric layer and the magnetic tunnel junction structure;
step S306: and etching the top electrode material layer, the first dielectric layer and the bottom material layer to form a top electrode layer on the magnetic tunnel junction structure and a bottom electrode layer at the bottom of the magnetic tunnel junction structure.
A method of forming an MRAM device in an embodiment of the present invention will be described in further detail with reference to fig. 4 through 10.
Referring to fig. 4, a substrate (not shown) is provided, on which a first metal layer 400, a dielectric layer 410 on the first metal layer 400, and a plug 411 penetrating the dielectric layer, and a bottom material layer 420 on the dielectric layer 410 and the plug 411 are formed.
In a specific implementation, the substrate provides a process platform for subsequent formation of the MRAM device.
In a specific implementation, the base can be a silicon substrate or a germanium substrate or the like. In addition, other devices, such as PMOS transistors and NMOS transistors, may be formed in the substrate; an isolation structure can be formed in the substrate, wherein the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure; the substrate may also have CMOS devices formed therein, such as NMOS transistors and/or PMOS transistors. Similarly, a conductive member may be formed in the substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like.
The first metal layer 400 may be a bottom metal layer M1 or an intermediate metal layer Mn (n is an integer greater than 1) in the MRAM device, which may be made of a magnetic material such as copper or tungsten.
The dielectric layer 410 is used to isolate the adjacent plugs 411.
In a specific implementation, dielectric layer 410 may be made of an oxide or a low-K material having a dielectric constant lower than that of silicon dioxide. In this embodiment, the dielectric layer 410 is made of silicon dioxide (SiO 2). In other embodiments, dielectric layer 410 may also comprise, for example, silicon oxide, fluorine or carbon doped silicon oxide, porous silicon oxide, spin-on organic polymers, or inorganic polymers such as hydrogen silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), and the like.
In a specific implementation, the plug 411 serves as a contact between the first metal layer 400 and a subsequently formed bottom electrode.
In this embodiment, the plug 411 is formed by a damascene process. Specifically, the dielectric layer 410 is etched to form a through hole penetrating through the dielectric layer 410, and the bottom of the through hole exposes the material of the semiconductor substrate 410; the via is filled with a conductive material, such as copper, and a planarization process, such as a chemical mechanical polishing process or an etch-back process, is performed to make the top surface of the filled conductive material flush with the top surface of the dielectric layer 410, thereby forming a plug 411 located in the dielectric layer 410 and penetrating through the dielectric layer 410.
The bottom material layer 420 provides a process foundation for forming a bottom electrode of a Magnetic Tunnel Junction (MTJ).
In this embodiment, the bottom material layer 420 includes a bottom electrode material layer and a seed material layer on the bottom electrode material layer. The bottom electrode material layer is made of Ta, TaN, Ti or TiN and the like, and the thickness of the bottom electrode material layer is 15 nm-25 nm; the seed material layer is made of Ta or Ru and has the thickness of 1-5 nm.
The bottom material layer 420 may be formed over the dielectric layer 410 and the plug 411 using a process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD).
Referring to fig. 5, a magnetic tunnel junction material layer 430 is formed on the base material layer 420.
The magnetic tunnel junction material layer 430 serves as a subsequent formation of more than two Magnetic Tunnel Junction (MTJ) structures by etching.
The magnetic tunnel junction material layer 430 includes: a first magnetic material layer 431, a barrier material layer 432 over the first magnetic material layer 431, and a second magnetic material layer 433 over the barrier material layer 432. In this embodiment, the first magnetic material layer 431 is a reference material layer, and the second magnetic material layer 433 is a free material layer.
In addition, when the first magnetic material layer 431 is a reference material layer and the second magnetic material layer 433 is a free material layer, the magnetic tunnel junction material layer 430 may further include a pinned material layer below the reference material layer or may further include a capping material layer above the free material layer.
In other embodiments, the first magnetic material layer 431 is a free material layer, and the second magnetic material layer 433 is a reference material layer. When the first magnetic material layer 431 is a free material layer and the second magnetic material layer 433 is a reference material layer, the magnetic tunnel junction material layer 430 may further include a pinned material layer on the reference material layer.
The formation process of the magnetic tunnel junction material layer 430 includes a Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD) process.
Referring to fig. 6, a patterned hard mask layer 440 is formed over the magnetic tunnel junction material layer 430.
The hard mask layer 440 serves as a mask for etching the magnetic tunnel junction material layer 430 and the bottom material layer 420.
In this embodiment, the hard mask layer 440 includes a metal hard mask layer 441 and a dielectric hard mask layer 442 located on the metal hard mask layer 441. Wherein the metal hard mask layer 441 is made of Ta, TaN, Ti or TiN and has a thickness of 450nm to 700 nm; the material of the dielectric hard mask layer 442 comprises SiO2Or SiN with a thickness of 500 nm-800 nm.
The step of forming the patterned hard mask layer 440 may comprise: forming a metal hard mask material layer over the magnetic tunnel junction material layer 430 and a dielectric hard mask material layer over the metal hard mask material layer; forming a patterned photoresist layer on the dielectric hard mask material layer; and sequentially etching the dielectric hard mask material layer and the metal mask material layer by taking the patterned photoresist layer as a mask until the top surface of the magnetic tunnel junction structure material layer 430 is exposed to form a patterned metal hard mask layer 441 and a patterned dielectric hard mask layer 442, namely forming the patterned hard mask layer 440.
Referring to fig. 7, the magnetic tunnel junction structure layer 430 is etched using the patterned hard mask layer 440 as a mask, and etching is stopped on the bottom material layer 420, so as to form a magnetic tunnel junction structure 435.
In the present embodiment, the magnetic tunnel junction structure 435 includes a first magnetic layer 431 ', a barrier layer 432 ' over the first magnetic layer 431 ', and a second magnetic layer 433 ' over the barrier layer 432 '.
In this embodiment, the first magnetic layer 431 'is a reference layer, and the second magnetic layer 433' is a free layer. Accordingly, the magnetic tunnel junction structure 435 may further include a pinned layer located below the reference layer and a capping layer located above the free layer.
In other embodiments, the first magnetic layer 431 'is a free layer and the second magnetic layer 433' is a reference layer. Accordingly, the magnetic tunnel junction structure 435 may further include a pinning layer on the reference layer.
In this embodiment, the bottom material layer 420 includes a bottom electrode material layer and a seed material layer on the bottom electrode material layer. In the process of etching the magnetic tunnel junction structure layer 430 by using the patterned hard mask layer 440 as a mask, the seed material layer is used as an etch stop layer.
In this embodiment, in order to obtain a more precise morphology of the magnetic tunnel junction structure, the magnetic tunnel junction structure layer 430 is etched by an ion beam etching process with an etching angle of 20 ° to 45 ° and energy of 80eV to 800eV, so as to form the magnetic tunnel junction structure 435. In other embodiments, the etching process to form the magnetic tunnel junction structure 435 can also be a Reactive Ion Etching (RIE) process.
In the process of patterning the magnetic tunnel junction structure layer 430, the seed material layer on the bottom electrode material layer is used as an etching stop layer, so that the etching thickness is reduced, the etching time is shortened, and the phenomenon that the magnetic material is redeposited on the side wall of the barrier layer can be avoided.
In this embodiment, in the process of forming the magnetic tunnel junction structure 435 by etching, all the dielectric hard mask layer 442 and part of the metal hard mask layer 441 are also etched and removed together, and only the metal hard mask layer 441 with a part of the remaining thickness is still located on the magnetic tunnel junction structure 435.
In this embodiment, before forming the magnetic tunnel junction structure 435, the method further includes: and etching the covering material layer to form a covering layer. Specifically, before patterning the magnetic tunnel junction structure layer 430, the capping material layer is etched using the hard mask layer 440 as a mask to form a capping layer.
In this embodiment, in the process of forming the magnetic tunnel junction structure 435, etching the pinning material layer to form a pinning layer is further included. Specifically, after the first magnetic layer is formed, the pinning material layer is etched using the hard mask layer 440 as a mask to form a pinning layer.
In other embodiments, during the patterning of the magnetic tunnel junction material layer, the seed material layer is further etched to form a seed layer, and the bottom electrode material layer is used as an etch stop layer.
Referring to fig. 8, after forming the magnetic tunnel junction structure 435, a first dielectric layer 470 is formed on the bottom material layer of the side of the magnetic tunnel junction structure.
In this embodiment, the method further includes: forming a protective layer 460 covering the sidewalls of the magnetic tunnel junction structure 435; the first dielectric layer 470 covers the sidewalls of the protection layer 460.
In this embodiment, the protection layer 460 and the first dielectric layer 470 may be formed to prevent the magnetic material from the seed material layer of the bottom material layer 420 and the bottom electrode material layer from redepositing on the sidewall of the formed mtj structure 435, and particularly to prevent the redeposited magnetic material from forming on the sidewall of the barrier layer during the subsequent etching of the bottom material layer 430. At the same time, the protective layer 460 and the first dielectric layer 470 also provide a process basis for subsequently forming a top electrode material layer over a plurality of the magnetic tunnel junction structures 435 in the same step.
In the embodiment of the invention, the protective layer 460 is made of SiN or SiCN, and has a thickness of 10nm to 30 nm; the first dielectric layer 470 is made of SiO2。
The step of forming the protective layer 460 and the first dielectric layer 470 includes: forming a protective material layer on the side wall and the top of the magnetic tunnel junction structure 435 and the surface of the bottom material layer 420 at the side of the magnetic tunnel junction structure 435; forming a first dielectric material layer on the protective material layer; and planarizing the first dielectric material layer and the protective material layer until the first dielectric material layer and the protective material layer on the top of the magnetic tunnel junction structure 435 are removed, so that the first dielectric material layer forms a first dielectric layer 470, and the protective material layer forms a protective layer 460.
The process for forming the protective material layer includes a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, after forming the protective layer 460, and before subsequently forming the top electrode material layer, the protective layer 460 also covers the bottom material layer 420 surface at the side of the magnetic tunnel junction structure 435.
In this embodiment, a metal hard mask layer 441 with a partial thickness is further remained on the top of the magnetic tunnel junction structure 435, so as to protect the top of the formed magnetic tunnel junction structure 435 in a subsequent process. When a partial thickness of the metal hard mask layer 441 still remains on top of the magnetic tunnel junction structure 435, the protection layer 460 also covers sidewalls of the metal hard mask layer 441; during the planarization of the first dielectric material layer and the protective material layer, the first dielectric material layer and the protective material layer on top of the metal hard mask layer 441 over the top of the magnetic tunnel junction structure 435 are removed.
Referring to fig. 9, a top electrode material layer 480 is formed on the first dielectric layer 470 and on the magnetic tunnel junction structure 435.
Specifically, after forming the first dielectric layer 470 and the protective layer 460, a top electrode material layer 480 is formed to cover the protective layer 460, the first dielectric layer 470 and the magnetic tunnel junction structure 435.
The top electrode material layer 480 is used for subsequent etching to form a top electrode layer over the magnetic tunnel junction structure 435.
In an embodiment of the present invention, the material of the top electrode material layer 480 includes Ta, TaN, Ti, or TiN.
The process of forming the top electrode material layer 480 includes an atomic layer deposition process or a chemical vapor process.
In this embodiment, a metal hard mask layer 441 with a partial thickness is further remained on the top of the magnetic tunnel junction structure 435, and the top electrode material layer 480 covers the protection layer 460, the first dielectric layer 470 and the metal hard mask layer 441.
Referring to fig. 10, the top electrode material layer 480, the first dielectric layer 470 and the bottom material layer 420 are etched to form a top electrode layer 485 on the magnetic tunnel junction structure 435 and a bottom electrode layer 425 at the bottom of the magnetic tunnel junction structure 435.
In this embodiment, specifically, the top electrode material layer 480, the first dielectric layer 470, the protection layer 460 on the surface of the bottom material layer 420 located at the side of the magnetic tunnel junction structure 435, and the bottom electrode material layer are etched, and in the etching process, the seed material layer on the bottom electrode layer is also etched, so that the seed material layer forms the seed layer, and the bottom electrode material layer forms the bottom electrode layer.
In this embodiment, in order to obtain a relatively precise shape, the top electrode layer 480, the first dielectric layer 470, and the bottom material layer 420 are etched by an ion beam etching process with an etching angle of 25 ° to 40 ° and an energy of 80eV to 800 eV. In the embodiment of the present invention, during the etching process of the top electrode layer 480, the first dielectric layer 470, and the bottom material layer 420, the processing gas used in the ion beam etching process includes Ar, Kr, or Xe.
In other embodiments, the top electrode layer 480, the first dielectric layer 470, and the bottom material layer 420 can also be etched using a reactive ion etching process. The processing gas adopted by the reactive ion etching process comprises CH3OH、CO、NH3And CH3CH2And (5) OH. In this embodiment, an opening is formed through the top electrode material layer 480, the first dielectric layer 470 and the bottom electrode layer 425 in the process of forming the top electrode layer 485 on the magnetic tunnel junction structure 435 and the bottom electrode layer 425 at the bottom of the magnetic tunnel junction structure 435. After the opening is formed, a step of forming a second dielectric layer in the opening and on the top electrode layer 485 is also included.
In this embodiment, the opening also penetrates the protection layer 460 on the substrate surface.
The embodiment of the invention also provides an MRAM device.
With continued reference to fig. 10, an MRAM device in an embodiment of the present invention may include: a substrate (not shown); a plurality of discrete bottom electrode layers 425 on the substrate; magnetic tunnel junction structures 435 respectively located over the bottom electrode layers 425; a first dielectric layer 470 on the substrate at the side of the magnetic tunnel junction structure 435, wherein the first dielectric layer 470 covers the sidewall of the magnetic tunnel junction structure 435 and the bottom surface of the first dielectric layer 470 is higher than the bottom surface of the bottom electrode layer 425; top electrode layers 485 respectively located above the magnetic tunnel junction structures 435; openings through the first dielectric layer between adjacent top electrode layers 485, adjacent bottom electrode layers 425, and between adjacent magnetic tunnel junction structures 435.
In this embodiment, the MRAM device further includes: a protective layer 460 on sidewalls of the magnetic tunnel junction structures 435, the protective layer 460 further extending to a portion of the substrate surface between adjacent magnetic tunnel junction structures; the first dielectric layer 470 also covers the protective layer 460; the opening also extends through the protective layer 460 on the surface of the substrate.
In the embodiment of the invention, the protective layer is made of SiN or SiCN and has a thickness of 10 nm-30 nm.
In this embodiment, the MRAM device further includes: a seed layer between the bottom electrode layer 425 and the magnetic tunnel junction structure 435.
In this embodiment, the bottom surface of the first dielectric layer 470 is higher than the bottom surface of the seed layer. In other embodiments, the bottom surface of the first dielectric layer 470 is higher than the bottom surface of the bottom electrode layer 425 and lower than the bottom surface of the seed layer.
In the embodiment of the invention, the material of the seed layer comprises Ta or Ru, and the thickness of the seed layer is 1 nm-5 nm.
In the embodiment of the invention, the material of the top electrode layer comprises Ta, TaN, Ti or TiN, and the thickness is 50 nm-100 nm; the bottom electrode layer is made of Ta, TaN, Ti or TiN, and the thickness of the bottom electrode layer is 15 nm-25 nm.
In an embodiment of the present invention, the MRAM device further includes: a second dielectric layer (not shown) in the opening and on the top electrode layer.
By adopting the scheme in the embodiment of the invention, the magnetic tunnel junction material layer is patterned and stopped at the bottom material layer to form the magnetic tunnel junction structure, so that a large amount of magnetic materials can be prevented from being redeposited on the side wall of the magnetic tunnel junction structure in the process of etching the bottom material layer with larger thickness. After etching to form a magnetic tunnel junction structure, forming a first dielectric layer on a bottom material layer at the side part of the magnetic tunnel junction structure; forming a top electrode material layer on the first dielectric layer and the magnetic tunnel junction structure; and etching the top electrode material layer, the first dielectric layer and the bottom material layer to form a top electrode layer on the magnetic tunnel junction structure and a bottom electrode layer at the bottom of the magnetic tunnel junction structure. In the process of etching the top electrode material layer, the first dielectric layer and the bottom material layer, the first dielectric layer isolates the barrier layer in the magnetic tunnel junction structure, and the magnetic material redeposited in the etching process can be prevented from covering the side wall of the barrier layer, so that the magnetic material deposited on the side wall of the barrier layer can be prevented from being in direct contact with the barrier layer, short circuit is avoided, and the performance of the MRAM device can be improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (25)
1. A method of forming an MRAM device, comprising:
providing a substrate;
forming a bottom material layer and a magnetic tunnel junction material layer on the bottom material layer on the substrate;
imaging the magnetic tunnel junction material layer and stopping at the bottom material layer to enable the magnetic tunnel junction material layer to form a magnetic tunnel junction structure;
forming a first dielectric layer on the bottom material layer at the side part of the magnetic tunnel junction structure;
forming a top electrode material layer on the first dielectric layer and the magnetic tunnel junction structure;
and etching the top electrode material layer, the first dielectric layer and the bottom material layer to form a top electrode layer on the magnetic tunnel junction structure and a bottom electrode layer at the bottom of the magnetic tunnel junction structure.
2. The method of claim 1, wherein the magnetic tunnel junction material layer comprises a pinned material layer over the bottom material layer, a reference material layer over the pinned material layer, a barrier material layer over the reference material layer, and a free material layer over the barrier material layer; the magnetic tunnel junction structure comprises a pinned layer, a reference layer located on the pinned layer, a barrier layer located on the reference layer, and a free layer located on the barrier layer; or, the magnetic tunnel junction material layer comprises a free material layer located above the bottom material layer, a barrier material layer located above the free material layer, a reference material layer located above the barrier material layer, and a pinned material layer located above the reference material layer; the magnetic tunnel junction structure includes a free layer, a barrier layer on the free layer, a reference layer on the barrier layer, and a pinned layer on the reference layer.
3. The method of claim 1, wherein the bottom material layer comprises a bottom electrode material layer and a seed material layer over the bottom electrode material layer.
4. The method of claim 3, wherein said seed material layer is used as an etch stop layer during the patterning of said magnetic tunnel junction material layer;
the step of etching the top electrode material layer, the first dielectric layer and the bottom material layer comprises: and etching the top electrode material layer, the first dielectric layer, the seed material layer and the bottom electrode material layer to form a bottom electrode layer on the bottom electrode material layer and form a seed layer on the bottom electrode layer on the seed material layer.
5. The method of claim 3, wherein during the patterning of the magnetic tunnel junction material layer, the seed material layer is further etched to form a seed layer, and the bottom electrode material layer is used as an etch stop layer.
6. The method of claim 3, wherein the material of the bottom electrode material layer comprises Ta, TaN, Ti or TiN, and has a thickness of 15nm to 25 nm; the seed layer is made of Ta or Ru and has a thickness of 1-5 nm.
7. The method of forming an MRAM device of claim 1, further comprising:
forming a protective layer on the side wall of the magnetic tunnel junction structure; the first dielectric layer covers the side wall of the protective layer.
8. The method of forming an MRAM device of claim 7, wherein the step of forming the protective layer and the first dielectric layer comprises: forming a protective material layer on the side wall and the top of the magnetic tunnel junction structure and the surface of the bottom material layer on the side part of the magnetic tunnel junction structure; forming a first dielectric material layer on the protective material layer; and flattening the first medium material layer and the protective material layer until the first medium material layer and the protective material layer on the top of the magnetic tunnel junction structure are removed, so that the first medium material layer forms a first medium layer, and the protective material layer forms a protective layer.
9. The method of claim 8, wherein forming the protective material layer comprises a chemical vapor deposition process or an atomic layer deposition process.
10. The method of claim 7, wherein the protective layer comprises SiN or SiCN and has a thickness of 10nm to 30 nm.
11. The method of forming an MRAM device of claim 1, further comprising:
forming a hard mask layer on the magnetic tunnel junction material layer before patterning the magnetic tunnel junction material layer, wherein the hard mask layer comprises a metal hard mask layer and a medium hard mask layer positioned on the metal hard mask layer; and patterning the magnetic tunnel junction material layer by taking the hard mask layer as a mask.
12. The method of claim 11, wherein the metal hard mask layer material comprises Ta, TaN, Ti or TiN with a thickness of 450nm to 700 nm; the dielectric hard mask layer material comprises silicon dioxide or silicon nitride, and the thickness is 500 nm-800 nm.
13. The method of claim 1, wherein the etching of the top electrode material layer, the first dielectric layer, and the bottom material layer is an ion beam etching process or a reactive ion etching process.
14. The method of claim 13, wherein the ion beam etching process has an etching angle of 20 ° to 45 ° and an energy of 80eV to 800 eV; the processing gas used by the ion beam etching process comprises Ar, Kr or Xe.
15. The method of claim 13, wherein the process gas used in the reactive ion etching process comprises CH3OH、CO、NH3And CH3CH2OH。
16. The method of claim 1, wherein the top electrode comprises Ta, TaN, Ti or TiN with a thickness of 50nm to 100 nm.
17. The method of claim 1, wherein the top electrode material layer, the first dielectric layer, and the bottom material layer are etched to form an opening through the top electrode material layer, the first dielectric layer, and the bottom material layer; the method for forming the MRAM device further comprises: and forming a second dielectric layer in the opening and on the top electrode layer.
18. An MRAM device, comprising:
a substrate;
a plurality of discrete bottom electrode layers on the substrate;
magnetic tunnel junction structures respectively located over the bottom electrode layer;
the first dielectric layer is positioned on the substrate at the side part of the magnetic tunnel junction structure, covers the side wall of the magnetic tunnel junction structure, and is higher than the bottom surface of the bottom electrode layer;
top electrode layers respectively located over the magnetic tunnel junction structures;
and the openings are positioned between the adjacent top electrode layers, between the adjacent bottom electrode layers and between the adjacent magnetic tunnel junction structures and penetrate through the first dielectric layer.
19. The MRAM device of claim 18, further comprising: the protective layer is positioned on the side wall of the magnetic tunnel junction structure and also extends to part of the surface of the substrate between the adjacent magnetic tunnel junction structures; the first dielectric layer also covers the protective layer; the opening also penetrates through the protective layer on the surface of the substrate.
20. The MRAM device of claim 19, wherein the material of the protective layer comprises SiN or SiCN and has a thickness of 10nm to 30 nm.
21. The MRAM device of claim 18, further comprising: a seed layer located between the bottom electrode layer and the magnetic tunnel junction structure.
22. The MRAM device of claim 21, wherein a bottom surface of the first dielectric layer is higher than a bottom surface of the seed layer; or the bottom surface of the first dielectric layer is higher than the bottom surface of the bottom electrode layer and lower than the bottom surface of the seed layer.
23. The MRAM device of claim 21, wherein the material of the seed layer comprises Ta or Ru and has a thickness in a range of 1nm to 5 nm.
24. The MRAM device of claim 18, wherein the material of the top electrode layer comprises Ta, TaN, Ti or TiN, between 50nm and 100nm thick; the bottom electrode layer is made of Ta, TaN, Ti or TiN, and the thickness of the bottom electrode layer is 15 nm-25 nm.
25. The MRAM device of claim 18, further comprising: a second dielectric layer in the opening and on the top electrode layer.
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