CN113447148B

CN113447148B - Infrared focal plane detector

Info

Publication number: CN113447148B
Application number: CN202110713217.7A
Authority: CN
Inventors: 翟光杰; 潘辉; 武佩; 翟光强
Original assignee: Beijing North Gaoye Technology Co ltd
Current assignee: Beijing North Gaoye Technology Co ltd
Priority date: 2021-06-25
Filing date: 2021-06-25
Publication date: 2022-12-02
Anticipated expiration: 2041-06-25
Also published as: CN113447148A

Abstract

The utility model relates to an infrared focal plane detector, CMOS measurement circuitry and CMOS infrared sensing structure all use CMOS technology preparation in the infrared focal plane detector, among the infrared focal plane detector, first columnar structure is located between reflector layer and the beam structure, and second columnar structure is located between absorption board and the beam structure, and first columnar structure and second columnar structure are solid columnar structure, and infrared focal plane detector still includes metamaterial structure and/or polarization structure. Through the technical scheme of this disclosure, the performance of having solved traditional MEMS technology infrared focal plane detector is low, the pixel scale is low, the low and poor problem of uniformity of yield, be favorable to improving infrared focal plane detector's structural stability, increase the area of absorption board, promote infrared detection sensitivity of infrared focal plane detector, and be favorable to improving infrared focal plane detector and to the absorption rate of incident infrared electromagnetic wave, optimize infrared focal plane detector's performance, reduce infrared focal plane detector optical design's the degree of difficulty.

Description

Infrared focal plane detector

Technical Field

The present disclosure relates to the field of infrared detection technology, and in particular, to an infrared focal plane detector.

Background

The fields of monitoring markets, vehicle and auxiliary markets, home markets, intelligent manufacturing markets, mobile phone applications and the like have strong demands on uncooled high-performance chips, certain requirements are provided for the performance of the chips, the performance consistency and the product price, the potential demands of more than one hundred million chips are expected every year, and the current process scheme and architecture cannot meet the market demands.

At present, an infrared focal plane detector adopts a mode of combining a measuring circuit and an infrared sensing structure, the measuring circuit is prepared by adopting a Complementary Metal-Oxide-Semiconductor (CMOS) process, and the infrared sensing structure is prepared by adopting a Micro-Electro-Mechanical System (MEMS) process, so that the following problems are caused:

(1) The infrared sensing structure is prepared by adopting an MEMS (micro-electromechanical systems) process, polyimide is used as a sacrificial layer, and the infrared sensing structure is incompatible with a CMOS (complementary metal oxide semiconductor) process.

(2) Polyimide is used as a sacrificial layer, so that the problem that the vacuum degree of a detector chip is influenced due to incomplete release exists, the growth temperature of a subsequent film is limited, and the selection of materials is not facilitated.

(3) Polyimide can cause the height of the resonant cavity to be inconsistent, and the working dominant wavelength is difficult to guarantee.

(4) The control of the MEMS process is far worse than that of the CMOS process, and the performance consistency and the detection performance of the chip are restricted.

(5) MEMS has low productivity, low yield and high cost, and can not realize large-scale batch production.

(6) The existing process capability of the MEMS is not enough to support the preparation of a detector with higher performance, and the MEMS has smaller line width and thinner film thickness, so that the miniaturization of a chip is not facilitated.

Disclosure of Invention

In order to solve the technical problem or solve above-mentioned technical problem at least partially, the present disclosure provides an infrared focal plane detector, the performance of having solved traditional MEMS technology infrared focal plane detector is low, the pixel scale is low, the low and poor problem of uniformity of yield, be favorable to improving infrared focal plane detector's structural stability, increase the area of absorption plate, promote infrared detection sensitivity of infrared focal plane detector, and be favorable to improving infrared focal plane detector and to the absorption rate of incident infrared electromagnetic wave, optimize infrared focal plane detector's performance, reduce infrared focal plane detector optical design's the degree of difficulty.

The present disclosure provides an infrared focal plane detector, comprising:

the CMOS infrared sensing structure comprises a CMOS measuring circuit system and a CMOS infrared sensing structure, wherein the CMOS measuring circuit system and the CMOS infrared sensing structure are both prepared by using a CMOS process, and the CMOS infrared sensing structure is directly prepared on the CMOS measuring circuit system;

the CMOS measurement circuit system comprises at least one layer of closed release isolation layer above the CMOS measurement circuit system, wherein the closed release isolation layer is used for protecting the CMOS measurement circuit system from being influenced by a process in the release etching process of manufacturing the CMOS infrared sensing structure;

the CMOS manufacturing process of the CMOS infrared sensing structure comprises a metal interconnection process, a through hole process, an IMD (in-mold decoration) process and an RDL (remote description language) process, wherein the CMOS infrared sensing structure comprises at least three metal interconnection layers, at least three dielectric layers and a plurality of interconnection through holes, the metal interconnection layers at least comprise a reflecting layer and two electrode layers, and the dielectric layers at least comprise two sacrificial layers and one heat-sensitive dielectric layer; the thermal sensitive dielectric layer is used for converting temperature change corresponding to infrared radiation absorbed by the thermal sensitive dielectric layer into resistance change, and further converting an infrared target signal into a signal capable of realizing electric reading through the CMOS measuring circuit system;

the CMOS infrared sensing structure comprises a resonant cavity formed by the reflecting layer and the heat sensitive medium layer, a suspended micro-bridge structure for controlling heat transfer, a first columnar structure and a second columnar structure, wherein the first columnar structure and the second columnar structure have electric connection and support functions;

the infrared focal plane detector also comprises a metamaterial structure and/or a polarization structure, wherein the metamaterial structure or the polarization structure is at least one metal interconnection layer on one side of the third dielectric layer close to the CMOS measuring circuit system, or at least one metal interconnection layer on one side of the fourth dielectric layer far away from the CMOS measuring circuit system, or at least one metal interconnection layer which is arranged between the third dielectric layer and the fourth dielectric layer and is electrically insulated from the second electrode layer, or the second electrode layer is used as a metamaterial structure layer or a polarization structure layer;

the CMOS measuring circuit system is used for measuring and processing an array resistance value formed by one or more CMOS infrared sensing structures and converting an infrared signal into an image electric signal; the CMOS measuring circuit system comprises a bias voltage generating circuit, a column-level analog front-end circuit and a row-level circuit, wherein the input end of the bias voltage generating circuit is connected with the output end of the row-level circuit, the input end of the column-level analog front-end circuit is connected with the output end of the bias voltage generating circuit, the row-level circuit comprises row-level mirror image pixels and row selection switches, and the column-level analog front-end circuit comprises blind pixels; the row-level circuit is distributed in each pixel, selects a signal to be processed according to a row strobe signal of the time sequence generating circuit, and outputs a current signal to the column-level analog front-end circuit under the action of the bias voltage generating circuit so as to perform current-voltage conversion and output;

the column-level analog front-end circuit obtains two paths of currents according to the first bias voltage and the second bias voltage, performs transimpedance amplification on the difference between the two paths of generated currents and outputs the amplified current as an output voltage.

Optionally, the CMOS infrared sensing structure is fabricated on an upper layer or a same layer of a metal interconnection layer of the CMOS measurement circuitry.

Optionally, the sacrificial layer is used for enabling the CMOS infrared sensing structure to form a hollow structure, the material forming the sacrificial layer is silicon oxide, and the sacrificial layer is etched by using a post-CMOS process.

Optionally, the reflective layer is configured to reflect an infrared signal and form the resonant cavity with the thermal sensitive dielectric layer, the reflective layer includes at least one metal interconnection layer, the first pillar structure connects the beam structure and the CMOS measurement circuitry through the metal interconnection process and the via process, and the second pillar structure connects the absorber plate and the beam structure through the metal interconnection process and the via process;

the beam structure sequentially comprises a first dielectric layer, a first electrode layer and a second dielectric layer along the direction far away from the CMOS measuring circuit system, and the absorption plate sequentially comprises a third dielectric layer, a second electrode layer and a fourth dielectric layer; the material for forming the first dielectric layer comprises at least one of amorphous silicon, amorphous germanium-silicon, amorphous carbon or aluminum oxide, the material for forming the second dielectric layer comprises at least one of amorphous silicon, amorphous germanium-silicon, amorphous carbon or aluminum oxide, the material for forming the third dielectric layer comprises at least one of materials with the resistance temperature coefficient larger than a set value and prepared from amorphous silicon, amorphous germanium-silicon or amorphous carbon, and the material for forming the fourth dielectric layer comprises at least one of materials with the resistance temperature coefficient larger than the set value and prepared from amorphous silicon, amorphous germanium-silicon or amorphous carbon; alternatively, the first and second electrodes may be,

along the direction far away from the CMOS measuring circuit system, the beam structure sequentially comprises a first dielectric layer, a first electrode layer and a second dielectric layer, the absorption plate sequentially comprises a third dielectric layer, a second electrode layer, a heat-sensitive dielectric layer and a fourth dielectric layer, or the absorption plate sequentially comprises the third dielectric layer, the heat-sensitive dielectric layer, the second electrode layer and the fourth dielectric layer; wherein the material for forming the first dielectric layer comprises at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon or aluminum oxide, the material for forming the second dielectric layer comprises at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon or aluminum oxide, the material for forming the third dielectric layer comprises at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon or aluminum oxide, the material for forming the fourth dielectric layer comprises at least one of amorphous silicon, amorphous germanium-silicon, amorphous carbon or aluminum oxide, and the material for forming the heat sensitive dielectric layer comprises at least one of materials with the resistance temperature coefficient larger than a set value, which are prepared from titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium-silicon, amorphous germanium-oxygen-silicon, germanium-silicon, germanium-oxygen-silicon, graphene, barium strontium titanate film, copper or platinum;

the material forming the first electrode layer comprises at least one of titanium, titanium nitride, tantalum nitride, titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, nickel-silicon alloy, nickel, chromium, platinum, tungsten, aluminum or copper, and the material forming the second electrode layer comprises at least one of titanium, titanium nitride, tantalum nitride, titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, nickel-silicon alloy, nickel, chromium, platinum, tungsten, aluminum or copper.

Optionally, the first columnar structure comprises a solid structure, and a material constituting the solid structure comprises at least one of tungsten, copper or aluminum;

the side wall of the solid structure is in contact with a sacrificial layer between the beam structure and the CMOS measuring circuit system; alternatively, the first and second electrodes may be,

the side wall of the solid structure is coated with at least one dielectric layer, the solid structure is arranged in contact with the dielectric layer, and the material for forming the dielectric layer comprises at least one of silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminum oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium-silicon, amorphous germanium-oxygen-silicon, germanium-silicon, germanium-oxygen-silicon, graphene, copper or platinum; alternatively, the first and second liquid crystal display panels may be,

solid construction's lateral wall and solid construction closes on CMOS measures circuit system's surface cladding has at least one deck adhesion layer, to outlying in the first columnar structure adhesion layer is kept away from solid construction's lateral wall cladding has the dielectric layer, constitutes the material of adhesion layer includes at least one of titanium, titanium nitride, tantalum or tantalum nitride, constitutes the material of dielectric layer includes at least one in silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminium oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium silicon, amorphous germanium oxygen silicon, germanium silicon, germanium oxygen silicon, graphite alkene, copper or platinum.

Optionally, the second columnar structure comprises a solid structure, and a material constituting the solid structure comprises at least one of tungsten, copper or aluminum;

the side wall of the solid structure is arranged in contact with the sacrificial layer between the beam structure and the absorption plate; alternatively, the first and second electrodes may be,

the side wall of the solid structure is coated with at least one dielectric layer, the solid structure is arranged in contact with the dielectric layer, and the material for forming the dielectric layer comprises at least one of silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminum oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium-silicon, amorphous germanium-oxygen-silicon, germanium-silicon, germanium-oxygen-silicon, graphene, copper or platinum; alternatively, the first and second electrodes may be,

solid construction's lateral wall and solid construction closes on CMOS measurement circuitry's surface cladding has at least one deck adhesion layer, in the second columnar structure outermost periphery the adhesion layer is kept away from solid construction's lateral wall cladding has the dielectric layer, constitutes the material of adhesion layer includes at least one among titanium, titanium nitride, tantalum or the tantalum nitride, constitutes the material of dielectric layer includes at least one among silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminium oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium silicon, amorphous germanium oxygen silicon, germanium silicon germanium, germanium oxygen silicon, graphite alkene, copper or platinum.

Optionally, the first dielectric layer and/or the second dielectric layer between the oppositely arranged beam structures form a patterned film structure, the patterned film structure includes a plurality of stripe patterns, and the patterns in the patterned film structure are symmetrically arranged relative to the beam structures;

at least one hole-shaped structure is formed on the absorption plate, and the hole-shaped structure at least penetrates through the medium layer in the absorption plate; and/or at least one hole-shaped structure is formed on the beam structure, and the hole-shaped structure at least penetrates through the medium layer in the beam structure.

Optionally, the infrared focal plane detector further includes a first reinforcing structure, the first reinforcing structure is disposed corresponding to the position of the first columnar structure and located on one side of the first columnar structure away from the CMOS measurement circuit system, the first reinforcing structure is configured to enhance connection stability between the first columnar structure and the beam structure, and the first reinforcing structure includes a weighted block structure;

the weighting block structure is positioned on one side of the beam structure far away from the CMOS measuring circuit system and is in contact with the beam structure; or a through hole is formed in the position, corresponding to the first columnar structure, of the beam structure, at least part of the first columnar structure is exposed out of the through hole, the weighting massive structure comprises a first part and a second part, the first part is filled in the through hole, the second part is located outside the through hole, and the orthographic projection of the second part covers the orthographic projection of the first part.

Optionally, the infrared focal plane detector further includes a second reinforcing structure, where the second reinforcing structure is disposed corresponding to the position of the second columnar structure and located on a side of the second columnar structure far away from the CMOS measurement circuit system, and the second reinforcing structure includes a weighted block structure;

the absorption plate is provided with a through hole corresponding to the position of the second columnar structure, at least part of the second columnar structure is exposed out of the through hole, the weighting block-shaped structure comprises a first part filling the through hole and a second part located outside the through hole, and the orthographic projection of the second part covers the orthographic projection of the first part.

Optionally, the hermetic release isolation layer is located at an interface between the CMOS measurement circuitry and the CMOS infrared sensing structure and/or in the CMOS infrared sensing structure;

the airtight release isolation layer is located on the reflection layer and is arranged in contact with the reflection layer, the airtight release isolation layer comprises at least one dielectric layer, and the material forming the airtight release isolation layer comprises at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium-silicon, germanium-silicon, amorphous carbon or aluminum oxide.

Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:

the CMOS process is utilized to realize the integrated preparation of the CMOS measuring circuit system and the CMOS infrared sensing structure on the CMOS production line, compared with the MEMS process, the CMOS has no process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS process production line process to prepare the infrared focal plane detector, and the risk caused by the transportation problem and the like is reduced; the infrared focal plane detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the vacuum degree of a detector chip is influenced due to incomplete release of polyimide of the sacrificial layer, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared focal plane detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared focal plane detector; the infrared focal plane detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, and has larger duty ratio, lower thermal conductivity and smaller thermal capacity, thereby having higher detection sensitivity, longer detection distance and better detection performance; the infrared focal plane detector based on the CMOS process can make the size of the detector pixel smaller, realize smaller chip area under the same array pixel and be more beneficial to realizing the miniaturization of the chip; the infrared focal plane detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better meeting design requirements, better product consistency, more contribution to circuit chip adjustment performance and more contribution to industrialized batch production. In addition, absorption plate and beam structure are located the different layers, be favorable to increasing the area of absorption plate, promote infrared detection sensitivity of infrared focal plane detector, first columnar structure and second columnar structure are solid columnar structure, be favorable to improving the mechanical stability of infrared focal plane detector and realize infrared focal plane detector's miniaturization, it still includes metamaterial structure and/or polarization structure to set up infrared focal plane detector, infrared focal plane detector has effectively improved the absorption rate to the infrared electromagnetic wave of incidence, infrared focal plane detector's performance has been optimized.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the embodiments or technical solutions in the prior art description will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic perspective structure diagram of an infrared focal plane detector pixel provided in an embodiment of the present disclosure;

fig. 2 is a schematic cross-sectional structure diagram of an infrared focal plane detector pixel provided in an embodiment of the present disclosure;

FIG. 3 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure;

fig. 4 is a schematic perspective structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure;

fig. 5 is a schematic perspective structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure;

fig. 6 is a schematic perspective structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure;

fig. 7 is a schematic perspective structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure;

fig. 8 is a schematic top view of a polarization structure provided in an embodiment of the present disclosure;

FIG. 9 is a schematic diagram illustrating a top view of another polarization structure provided in an embodiment of the present disclosure;

FIG. 10 is a schematic diagram illustrating a top view of another polarization structure provided in an embodiment of the present disclosure;

fig. 11 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure;

FIG. 12 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided in the embodiments of the present disclosure;

fig. 13 is a schematic structural diagram of a CMOS measurement circuitry provided in an embodiment of the present disclosure;

fig. 14 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided by the embodiment of the disclosure;

fig. 15 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided by the embodiment of the present disclosure;

fig. 16 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided by the embodiment of the disclosure;

fig. 17 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure;

FIG. 18 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided by the embodiment of the present disclosure;

fig. 19 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided by the embodiment of the disclosure;

fig. 20 is a schematic top view of a first dielectric layer according to an embodiment of the disclosure.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.

Fig. 1 is a schematic perspective structure diagram of an infrared focal plane detector pixel provided in an embodiment of the present disclosure, and fig. 2 is a schematic cross-sectional structure diagram of an infrared focal plane detector pixel provided in an embodiment of the present disclosure. Referring to fig. 1 and 2, the infrared focal plane detector includes a plurality of infrared focal plane detector pixels arranged in an array, the CMOS process-based infrared focal plane detector includes a CMOS measurement circuit system 1 and a CMOS infrared sensing structure 2, both the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are manufactured by using a CMOS process, and the CMOS infrared sensing structure 2 is directly manufactured on the CMOS measurement circuit system 1.

Specifically, the CMOS infrared sensing structure 2 is used for converting an external infrared signal into an electric signal and transmitting the electric signal to the CMOS measuring circuit system 1, and the CMOS measuring circuit system 1 reflects temperature information of the corresponding infrared signal according to the received electric signal, so that the temperature detection function of the infrared focal plane detector is realized. The CMOS measuring circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by using a CMOS process, and the CMOS infrared sensing structure 2 is directly prepared on the CMOS measuring circuit system 1, namely, the CMOS measuring circuit system 1 is prepared by using the CMOS process, and then the CMOS infrared sensing structure 2 is continuously prepared by using the CMOS process by using the CMOS production line and parameters of various processes compatible with the production line.

Therefore, the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are integrally prepared on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS process does not have the process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS production line process to prepare the infrared focal plane detector, and the risk caused by the problems of transportation and the like is reduced; the infrared focal plane detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the vacuum degree of a detector chip is influenced due to incomplete release of polyimide of the sacrificial layer, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared focal plane detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared focal plane detector; the infrared focal plane detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, and has larger duty ratio, lower thermal conductivity and smaller thermal capacity, thereby having higher detection sensitivity, longer detection distance and better detection performance; the infrared focal plane detector based on the CMOS process can make the size of the detector pixel smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of the chip; the infrared focal plane detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better meeting design requirements, better product consistency, more contribution to circuit chip adjustment performance and more contribution to industrialized batch production.

Referring to fig. 1 and 2, the cmos infrared sensing structure 2 includes a resonant cavity formed by the reflective layer 4 and the heat sensitive medium layer, a suspended microbridge structure 40 for controlling heat transfer, and a first pillar structure 61 and a second pillar structure 62 having electrical connection and support functions. Specifically, the CMOS infrared sensing structure 2 includes a reflective layer 4 located on the CMOS measurement circuit system 1 and a suspended microbridge structure 40 for controlling heat transfer, the suspended microbridge structure 40 includes an absorption plate 10, the absorption plate 10 includes a heat sensitive medium layer, and a resonant cavity is formed between the reflective layer 4 and the heat sensitive medium layer. The suspended microbridge structure 40 includes an absorption plate 10 and a plurality of beam structures 11, the beam structures 11 are located on one side of the absorption plate 10 close to or far from the CMOS measurement circuitry 1, fig. 1 exemplarily shows that the suspended microbridge structure 40 includes two beam structures 11, and the beam structures 11 are located on one side of the absorption plate 10 close to the CMOS measurement circuitry 1.

The first columnar structure 61 is located between the reflective layer 4 and the beam structure 11, the beam structure 11 is electrically connected to the CMOS measurement circuitry 1 through the first columnar structure 61, that is, the first columnar structure 61 directly electrically connects the supporting pedestal 42 in the reflective layer 4 and the corresponding beam structure 11, the beam structure 11 is electrically connected to the CMOS measurement circuitry 1 through the first columnar structure 61 and the supporting pedestal 42, and the first columnar structure 61 is used for supporting the corresponding beam structure 11 after the sacrificial layer between the reflective layer 4 and the corresponding beam structure 11 is released. The second columnar structure 62 is located between the absorption plate 10 and the beam structure 11, the second columnar structure 62 is directly electrically connected with the absorption plate 10 and the beam structure 11, the absorption plate 10 is used for converting infrared signals into electrical signals and is electrically connected with the first columnar structure 61 through the second columnar structure 62 and the beam structure 11, namely, the electrical signals converted by the absorption plate 10 through the infrared signals are sequentially transmitted to the CMOS measurement circuit system 1 through the second columnar structure 62, the beam structure 11, the first columnar structure 61 and the supporting base 42, the CMOS measurement circuit system 1 processes the received electrical signals to reflect temperature information, non-contact infrared temperature detection of the infrared focal plane detector is achieved, and the second columnar structure 62 is used for supporting the corresponding absorption plate 10 after a sacrificial layer between the corresponding absorption plate 10 and the corresponding released beam structure 11 falls.

The CMOS infrared sensing structure 2 outputs a positive electrical signal and a ground electrical signal through different electrode structures, and the positive electrical signal and the ground electrical signal are transmitted to the corresponding supporting base 42 through different sets of columnar structures, one set of columnar structures includes a first columnar structure 61 and a second columnar structure 62. Illustratively, the CMOS infrared sensing structure 2 may be arranged in a direction parallel to the CMOS measurement circuitry 1, and comprises two sets of pillar structures, one of which may be arranged for transmitting a positive electrical signal and the other for transmitting a ground electrical signal. Or as shown in fig. 1, the direction parallel to the CMOS measurement circuit system 1 is set, the CMOS infrared sensing structure 2 includes four sets of columnar structures, the four sets of columnar structures can be two-two set into one set and respectively transmit positive electric signals and ground electric signals, because the infrared focal plane detector includes a plurality of infrared focal plane detector pixels arranged in an array, the four sets of columnar structures can also select two sets of columnar structures therein to respectively transmit positive electric signals and ground electric signals, and the other two sets of columnar structures provide the adjacent infrared focal plane detector pixels with electric signals for transmission. In addition, the reflective layer 4 includes a reflective plate 41 and a supporting base 42, a portion of the reflective layer 4 is used as a dielectric for electrically connecting the first columnar structure 61 with the CMOS measurement circuit system 1, that is, the supporting base 42, the reflective plate 41 is used for reflecting infrared rays to the heat sensitive medium layer in the absorption plate 10, and the secondary absorption of infrared rays is realized by matching with a resonant cavity formed between the reflective layer 4 and the heat sensitive medium layer in the absorption plate 10, so as to improve the infrared absorption rate of the infrared focal plane detector and optimize the infrared detection performance of the infrared focal plane detector.

Fig. 3 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure. In contrast to the structures shown in fig. 1 and 2, the infrared focal plane detector arrangement beam structure 11 of the structure shown in fig. 3 is located on the side of the absorber plate 10 facing away from the CMOS measurement circuitry 1. Specifically, the electrode layer in the absorption plate 10 is electrically connected to the electrode layer in the beam structure 11 through the second columnar structure 62, the electrode layer in the beam structure 11 is electrically connected to the support base 42 through the first columnar structure 61, and the electrical signal converted by the absorption plate 10 via the infrared signal is transmitted to the CMOS measurement circuit system 1 through the second columnar structure 62, the beam structure 11, the first columnar structure 61, and the support base 42 in sequence.

Combine fig. 1 to 3, it includes solid columnar structure to set up first columnar structure 61, form solid metallic structure at first columnar structure 61 position promptly, second columnar structure 62 includes solid columnar structure, form solid metallic structure at second columnar structure 62 position promptly, solid columnar structure's mechanical stability is better, first columnar structure 61 and beam structure 11 and supporting base 42 have been improved, and the support between second columnar structure 62 and beam structure 11 and absorption plate 10 is connected stability, and then the structural stability of infrared sensor pixel and the infrared focal plane detector including infrared focal plane detector pixel has been improved. In addition, the resistance of the metal solid columnar structure is small, signal loss in the process of electrical signal transmission between the absorption plate 10 and the CMOS measurement circuit system 1 is reduced, the infrared detection performance of the infrared focal plane detector is improved, the size of the metal solid columnar structure is easier to control accurately, namely the solid columnar structure can realize a columnar structure with a smaller size, the requirement on the size of a smaller chip is met, and the infrared focal plane detector is miniaturized. In addition, set up first columnar structure 61 and second columnar structure 62 and be located the different layers for infrared focal plane detector pixel forms bilayer structure, and the area of absorption plate 10 can not be influenced in the setting of beam structure 11, is favorable to increasing the area of absorption plate 10, improves infrared focal plane detector pixel and the infrared detection sensitivity of the infrared focal plane detector who includes infrared focal plane detector pixel.

Exemplarily, as shown in fig. 3, it may be arranged that, in a direction away from the CMOS measurement circuit system 1, the beam structure 11 sequentially includes a first dielectric layer 13, an electrode layer 14, and a second dielectric layer 15, the absorber plate 10 sequentially includes a third dielectric layer 130, a second electrode layer 140, and a fourth dielectric layer 150, and the second electrode layer 140, the second columnar structure 61, the first electrode layer 14, the first columnar structure 61, and the support base 42 in the absorber plate 10 are electrically connected to ensure that the electrical signal generated by the suspended micro-bridge structure 40 is transmitted to the CMOS measurement circuit system 1.

The material forming the first dielectric layer 13 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, or aluminum oxide, the material forming the second dielectric layer 15 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, or aluminum oxide, the material forming the third dielectric layer 130 includes at least one of materials having a temperature coefficient of resistance greater than a set value, which are prepared from amorphous silicon, amorphous germanium, amorphous silicon germanium, or amorphous carbon, the material forming the fourth dielectric layer 150 includes at least one of materials having a temperature coefficient of resistance greater than a set value, which are prepared from amorphous silicon, amorphous germanium, amorphous silicon germanium, or amorphous carbon, and the set value may be, for example, 0.015/K. Therefore, the first dielectric layer 13 serves as a supporting layer in the beam structure 11, the second dielectric layer 15 serves as a passivation layer in the beam structure 11, the third dielectric layer 130 serves as a heat sensitive dielectric layer while serving as a supporting layer in the absorption plate 10, and the fourth dielectric layer 150 also serves as a heat sensitive dielectric layer while serving as a passivation layer in the absorption plate 10, so that the thickness of the absorption plate 10 is reduced, and the preparation process of the infrared focal plane detector is simplified. Specifically, the supporting layer is used for supporting a film layer located above the supporting layer after releasing a sacrificial layer below the supporting layer, the heat-sensitive medium layer is used for converting infrared temperature detection signals into infrared detection electric signals, the second electrode layer 140 and the first electrode layer 14 are used for transmitting the infrared detection electric signals converted by the heat-sensitive medium layer in the absorption plate 10 to the CMOS measurement circuit system 1 through the beam structures 11 on the left side and the right side, the two beam structures 11 respectively transmit positive and negative signals of the infrared detection electric signals, a reading circuit in the CMOS measurement circuit system 1 realizes non-contact infrared temperature detection through analysis of the obtained infrared detection electric signals, and the passivation layer is used for protecting an electrode layer wrapped by the passivation layer from oxidation or corrosion. In addition, corresponding to the beam structure 11, the first electrode layer 14 is located in a closed space formed by the first dielectric layer 13, namely the support layer, and the second dielectric layer 15, namely the passivation layer, so that the first electrode layer 14 in the beam structure 11 is protected; corresponding to the absorber plate 10, the second electrode layer 140 is located in a closed space formed by the third dielectric layer 130, i.e., the support layer, and the fourth dielectric layer 150, i.e., the passivation layer, so that the second electrode layer 140 in the absorber plate 10 is protected.

Exemplarily, as shown in fig. 2, the beam structure 11 may also be arranged along a direction away from the CMOS measurement circuit system 1, the beam structure 11 sequentially includes a first dielectric layer 13, a first electrode layer 14, and a second dielectric layer 15, the absorber plate 10 sequentially includes a third dielectric layer 130, a second electrode layer 140, a second heat-sensitive dielectric layer 120, and a fourth dielectric layer 150, or the absorber plate 10 sequentially includes a third dielectric layer 130, a second heat-sensitive dielectric layer 120, a second electrode layer 140, and a fourth dielectric layer 150, that is, the heat-sensitive dielectric layer 120 of the absorber plate 10 may be arranged on a side of the second electrode layer 140 away from the CMOS measurement circuit system 1, the heat-sensitive dielectric layer 120 of the absorber plate 10 may also be arranged on a side of the second electrode layer 140 close to the CMOS measurement circuit system 1, fig. 2 is exemplarily arranged along a direction away from the CMOS measurement circuit system 1, the absorber plate 10 sequentially includes a third electrode layer 130, a second electrode layer 140, a second heat-sensitive dielectric layer 120, and a fourth dielectric layer 150, the second electrode layer 140, the second column structure 61, the first electrode layer 14, and the first column structure 61 in the absorber plate 11 are arranged in the absorber plate 10, and the support the suspended electrical signal transmission structure 40 to generate the measurement circuit system 1.

The material constituting the first dielectric layer 13 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon or aluminum oxide, the material constituting the second dielectric layer 15 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon or aluminum oxide, the material constituting the third dielectric layer 130 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon or aluminum oxide, the material constituting the fourth dielectric layer 150 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon or aluminum oxide, the material constituting the thermally sensitive dielectric layer 120 includes at least one of materials having a temperature coefficient of resistance greater than a set value, which may be, for example, 0.015/K, and prepared from titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium oxygen, silicon germanium, germanium oxygen silicon, graphene, barium strontium titanate, copper or platinum. Thus, the first dielectric layer 13 acts as a support layer in the beam structure 11, the second dielectric layer 15 acts as a passivation layer in the beam structure 11, the third dielectric layer 130 acts as a support layer in the absorber plate 10, and the fourth dielectric layer 150 acts as a passivation layer in the absorber plate 10. Specifically, the supporting layer is used for supporting a film layer located above the supporting layer after a sacrificial layer below the supporting layer is released, the heat sensitive medium layer 120 is used for converting infrared temperature detection signals into infrared detection electric signals, the second electrode layer 140 and the first electrode layer 14 are used for transmitting the infrared detection electric signals converted from the heat sensitive medium layer 12 in the absorption plate 10 to the CMOS measurement circuit system 1 through the beam structures 11 on the left side and the right side, the two beam structures 11 respectively transmit positive and negative signals of the infrared detection electric signals, a reading circuit in the CMOS measurement circuit system 1 realizes non-contact infrared temperature detection through analysis of the acquired infrared detection electric signals, and the passivation layer is used for protecting an electrode layer wrapped by the passivation layer from oxidation or corrosion. In addition, corresponding to the beam structure 11, the first electrode layer 14 is located in a closed space formed by the first dielectric layer 13, namely the support layer, and the second dielectric layer 15, namely the passivation layer, so that the first electrode layer 14 in the beam structure 11 is protected; corresponding to the absorber plate 10, the second electrode layer 140 is located in a closed space formed by the third dielectric layer 130, i.e., the support layer, and the fourth dielectric layer 150, i.e., the passivation layer, so that the second electrode layer 140 in the absorber plate 10 is protected.

Illustratively, the material constituting the first electrode layer 14 may be configured to include at least one of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel chromium alloy, nickel platinum alloy, nickel silicon alloy, nickel, chromium, platinum, tungsten, aluminum, or copper, wherein when the material of the first electrode layer 14 is at least one of titanium, titanium nitride, tantalum, or tantalum nitride, it is preferable to configure the first electrode layer 14 to be covered by the first dielectric layer 13 and the second dielectric layer 15, which prevents the first electrode layer 14 from being affected by the etching process. The material constituting the second electrode layer 140 includes at least one of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, nickel-silicon alloy, nickel, chromium, platinum, tungsten, aluminum, or copper, wherein when at least one of titanium, titanium nitride, tantalum, or tantalum nitride is used as the material of the second electrode layer 140, it is preferable that the second electrode layer 140 is covered by the third dielectric layer 130 and the fourth dielectric layer 150 to prevent the second electrode layer 140 from being affected by the etching process. In addition, it can also be arranged along a direction away from the CMOS measurement circuit system 1, the absorption plate 10 in the infrared focal plane detector pixel of the structure shown in fig. 2 sequentially includes a third dielectric layer 130, a second electrode layer 140, and a fourth dielectric layer 150, and the absorption plate 10 in the infrared focal plane detector pixel of the structure shown in fig. 3 sequentially includes the third dielectric layer 130, the second electrode layer 140, the heat-sensitive dielectric layer 140, and the fourth dielectric layer 150 or sequentially includes the third dielectric layer 130, the heat-sensitive dielectric layer 140, the second electrode layer 140, and the fourth dielectric layer 150.

Specifically, with reference to fig. 1 to fig. 3, the absorption plate at least includes a third dielectric layer 130, a second electrode layer 140, and a fourth dielectric layer 150, the second electrode layer 140 is located between the third dielectric layer 130 and the fourth dielectric layer 150, the third dielectric layer 130 is located on a side of the second electrode layer 140 close to the CMOS measurement circuit system 1, the infrared focal plane detector further includes a metamaterial structure and/or a polarization structure, the metamaterial structure is at least one metal interconnection layer, the polarization structure is at least one metal interconnection layer, the metamaterial structure or the polarization structure may be at least one metal interconnection layer of the third dielectric layer 130 close to the side of the CMOS measurement circuit system 1, for example, the metal interconnection layer constituting the metamaterial structure or the polarization structure may be located on a side of the third dielectric layer 130 close to the CMOS measurement circuit system 1 and is in contact with the third dielectric layer 130. For example, the metamaterial structure or the polarization structure may be at least one metal interconnection layer on the side of the fourth dielectric layer 150 away from the CMOS measurement circuitry 1, and for example, the metal interconnection layer constituting the metamaterial structure or the polarization structure may be disposed on the side of the fourth dielectric layer 150 away from the CMOS measurement circuitry 1 and in contact with the fourth dielectric layer 150. For example, the metamaterial structure or the polarization structure may be at least one metal interconnection layer located between the third dielectric layer 130 and the fourth dielectric layer 150 and electrically insulated from the second electrode layer 140, for example, the metal interconnection layer constituting the metamaterial structure or the polarization structure may be located between the third dielectric layer 130 and the second electrode layer 140 and electrically insulated from the second electrode layer 140 or located between the fourth dielectric layer 150 and the second electrode layer 140 and electrically insulated from the second electrode layer 140. For example, the second electrode layer 140 may also be disposed as a metamaterial structure layer or a polarization structure layer, i.e., a patterned structure constituting a metamaterial or a polarization structure may be formed on the second electrode layer 140.

Fig. 4 is a schematic perspective structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure. As shown in fig. 4, the metal interconnection layer constituting the metamaterial structure may include a plurality of metal repeating units 20 arranged in an array, each metal repeating unit 20 includes two diagonally arranged L-shaped patterned structures 21, and the infrared absorption spectrum of the infrared focal plane detector is in a 3-30 μm band. As shown in fig. 5, a plurality of patterned hollow structures 22 arranged in an array may be disposed on the metal interconnection layer forming the metamaterial structure, the patterned hollow structures 22 are in an open ring shape, and an infrared absorption spectrum band of the infrared focal plane detector is a band from 3 micrometers to 30 micrometers. As shown in fig. 6, a plurality of linear stripe structures 23 and a plurality of folded stripe structures 24 are disposed on the metal interconnection layer forming the metamaterial structure, and the linear stripe structures 23 and the folded stripe structures 24 are alternately arranged along a direction perpendicular to the linear stripe structures 23, where an infrared absorption spectrum band of the infrared focal plane detector is a band of 8 micrometers to 24 micrometers. Or as shown in fig. 7, a plurality of patterned hollow structures 25 arranged in an array are disposed on the metal interconnection layer forming the metamaterial structure, the patterned hollow structures 25 are regular hexagons, and the infrared absorption spectrum band of the infrared focal plane detector is a 3-30 μm band at this time. It should be noted that, in the embodiments of the present disclosure, specific patterns on the metal interconnection layer constituting the metamaterial structure are not limited, and it is sufficient to ensure that the repeated patterns can realize the functions of the metamaterial structure or the polarization structure.

Specifically, the metamaterial is a material for electromagnetic or optical beam regulation and control by controlling wavefront phase, amplitude and polarization based on the generalized snell's law, and can also be called as a super surface or a super structure, and the super surface or the super structure is an ultrathin two-dimensional array plane, so that the characteristics of electromagnetic waves such as phase, polarization mode, propagation mode and the like can be flexibly and effectively manipulated. The present disclosure utilizes the patterned structures shown in fig. 4 to fig. 7 to form an electromagnetic metamaterial structure, that is, an artificial composite structure or a composite material with supernormal electromagnetic properties is formed, so as to implement clipping of electromagnetic waves and light waves, thereby obtaining an electromagnetic wave absorption special device.

Fig. 8 is a schematic top view of a polarization structure according to an embodiment of the present disclosure. As shown in fig. 8, the polarization structure 26 may include a plurality of gratings 27 arranged in sequence, an interval between adjacent gratings 27 is 10nm to 500nm, the gratings 27 may be linear as shown in fig. 8, or may be curved as shown in fig. 9 and 10, the gratings 27 in the polarization structure 26 may be rotated or combined at any angle, and the polarization structure 26 may be disposed such that the CMOS sensing structure absorbs polarized light in a specific direction. Illustratively, the grating 27 may be a structure formed by etching a metal thin film, i.e., a metal interconnection layer. Specifically, polarization is an important information of light, and polarization detection can expand the information quantity from three dimensions, such as light intensity, light spectrum and space, to seven dimensions, such as light intensity, light spectrum, space, polarization degree, polarization azimuth angle, polarization ellipse ratio and rotation direction, and since the polarization degree of the ground object background is far less than that of the artificial target, the infrared polarization detection technology has very important application in the field of space remote sensing. In the existing polarization detection system, a polarization element is independent from a detector, and a polarizing film needs to be added on a lens of the whole machine or a polarization lens needs to be designed. The existing polarization detection system, which acquires polarization information by rotating a polarization element, has disadvantages of complicated optical elements and complicated optical path system. In addition, the polarization image acquired by combining the polarizer and the detector needs to be processed by an image fusion algorithm, which is not only complex but also relatively inaccurate.

According to the polarization structure 26 and the uncooled infrared focal plane detector, the polarization structure is monolithically integrated, so that monolithic integration of the polarization sensitive infrared focal plane detector can be achieved, difficulty of optical design is greatly reduced, an optical system is simplified, optical elements are reduced, and cost of the optical system is reduced. In addition, the image of the uncooled infrared focal plane detector collection of polarization type through monolithic integration is original infrared image information, and CMOS measurement circuit system 1 only needs to handle the signal that infrared focal plane detector detected and just can obtain accurate image information, and need not carry out the image fusion of current detector, very big promotion the authenticity and the validity of image. In addition, polarization structure 26 also can be located absorption plate 10 top and not with absorption plate 10 contact setting, polarization structure 26 can be for being located the unsettled structure of unsettled microbridge structure 40 top promptly, polarization structure 26 and unsettled microbridge structure 40 can adopt the mode of post connection support or the mode that adopts the bonding to support, polarization structure 26 can the one-to-one bonding with infrared focal plane detector pixel, also can adopt the mode of whole chip bonding. Therefore, the independently suspended metal grating structure cannot cause deformation of the infrared sensitive micro-bridge structure, and the heat-sensitive characteristic of the sensitive film cannot be influenced.

With reference to fig. 1 to 10, at least one hole structure may be formed on the absorption plate 10, wherein the hole structure penetrates through at least the medium layer in the absorption plate 10; and/or, at least one hole-shaped structure is formed on the beam structure 11, and the hole-shaped structure at least penetrates through the medium layer in the beam structure 11, that is, only the absorption plate 10, only the beam structure 11, or both the absorption plate 10 and the beam structure 11 may be provided with the hole-shaped structure. For example, whether the hole structures on the absorption plate 10 or the beam structure 11 are hole structures, the hole structures may be circular hole structures, square hole structures, polygonal hole structures, or irregular pattern hole structures, the shape of the hole structures on the absorption plate 10 and the beam structure 11 is not specifically limited by the embodiments of the present disclosure, and the number of the hole structures on the absorption plate 10 and the beam structure 11 is not specifically limited by the embodiments of the present disclosure.

Therefore, at least one hole-shaped structure is formed on the absorption plate 10, the hole-shaped structure at least penetrates through the dielectric layer in the absorption plate 10, a sacrificial layer which is contacted with the absorption plate 10 and needs to be released finally is arranged in the infrared focal plane detector, the sacrificial layer needs to be corroded by chemical reagents at the end of the infrared focal plane detector manufacturing process when the sacrificial layer is released, the hole-shaped structure on the absorption plate 10 is beneficial to increasing the contact area of the chemical reagents for releasing and the sacrificial layer, and the release rate of the sacrificial layer is accelerated. In addition, the area of the absorption plate 10 is larger than that of the beam structure 11, the hole-shaped structure on the absorption plate 10 is beneficial to releasing the internal stress of the absorption plate 10, optimizing the planarization degree of the absorption plate 10, and being beneficial to improving the structural stability of the absorption plate 10, so that the structural stability of the whole infrared focal plane detector is improved. In addition, at least one hole-shaped structure is formed on the beam structure 11, and the hole-shaped structure at least penetrates through the dielectric layer in the beam structure 11, so that the thermal conductance of the beam structure 11 is further reduced, and the infrared detection sensitivity of the infrared focal plane detector is improved.

Taking the infrared focal plane detector with the structure shown in fig. 3 as an example, at this time, the hole structure on the absorption plate 10 may penetrate through the third medium layer 130 and the fourth medium layer 150 in the absorption plate 10, the hole structure on the absorption plate 10 may also penetrate through the third medium layer 130, the second electrode layer 140 and the fourth medium layer 150 in the absorption plate 10, and the hole structure on the beam structure 11 may penetrate through the first medium layer 13 and the second medium layer 15 in the beam structure 11 where the first electrode layer 14 is not disposed, or the hole structure on the beam structure 11 may penetrate through the first medium layer 13, the electrode layer 14 and the second medium layer 15 in the beam structure 11. Taking the infrared focal plane detector with the structure shown in fig. 2 as an example, at this time, the hole structure on the absorption plate 10 may penetrate through the third medium layer 130 and the fourth medium layer 150 in the absorption plate 10, the hole structure on the absorption plate 10 may also penetrate through the third medium layer 130, the second electrode layer 140, the second heat-sensitive medium layer 120 and the fourth medium layer 150 in the absorption plate 10, the hole structure on the beam structure 11 may penetrate through the first medium layer 13 and the second medium layer 15 in the beam structure 11 where the first electrode layer 14 is not disposed, or the hole structure on the beam structure 11 penetrates through the first medium layer 13, the electrode layer 14 and the second medium layer 15 in the beam structure 11.

With reference to fig. 2 and 3, at least one hermetic release isolation layer 3 may be included above the CMOS measurement circuitry 1, and the hermetic release isolation layer 3 is used to protect the CMOS measurement circuitry 1 from the process during the release etching process for fabricating the CMOS infrared sensing structure 2. Optionally, the close release isolation layer 3 is located at an interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 and/or in the CMOS infrared sensing structure 2, that is, the close release isolation layer 3 may be located at an interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2, or the close release isolation layer 3 is located in the CMOS infrared sensing structure 2, or the close release isolation layer 3 is located at an interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 and is provided with the close release isolation layer 3, and the close release isolation layer 3 is used for protecting the CMOS measurement circuit system 1 from erosion when a sacrificial layer is released by a corrosion process, and the close release isolation layer 3 at least includes a dielectric layer, and a dielectric material constituting the close release isolation layer 3 includes at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, silicon, amorphous carbon, or aluminum oxide.

Fig. 2 and 3 exemplarily set the hermetic release isolation layer 3 in the CMOS infrared sensing structure 2, the hermetic release isolation layer 3 may be, for example, a dielectric layer or multiple dielectric layers above the metal interconnection layer of the reflective layer 4, where the hermetic release isolation layer 3 is exemplarily shown as a dielectric layer, in which case the material constituting the hermetic release isolation layer 3 may include at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium, amorphous carbon, or aluminum oxide, and the thickness of the hermetic release isolation layer 3 is smaller than that of the sacrificial layer. The resonant cavity of the infrared focal plane detector is realized by releasing the vacuum cavity after the silicon oxide sacrificial layer, the reflecting layer 4 is used as the reflecting layer of the resonant cavity, the sacrificial layer is positioned between the reflecting layer 4 and the suspended microbridge structure 40, and when at least one layer of closed release isolating layer 3 positioned on the reflecting layer 4 is arranged to select silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium silicon, germanium, silicon germanium alloy, amorphous carbon or aluminum oxide and other materials as one part of the resonant cavity, the reflecting effect of the reflecting layer 4 is not influenced, the height of the resonant cavity can be reduced, the thickness of the sacrificial layer is further reduced, and the release difficulty of the sacrificial layer formed by silicon oxide is reduced. In addition, the sealing release isolation layer 3 and the first columnar structure 61 are arranged to form a sealing structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the CMOS measurement circuit system 1 is protected.

Fig. 11 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure. On the basis of the above embodiment, fig. 11 also provides that the hermetic release isolation layer 3 is located in the CMOS infrared sensing structure 2, the hermetic release isolation layer 3 may be, for example, one or more dielectric layers located above the metal interconnection layer of the reflective layer 4, here, the hermetic release isolation layer 3 is exemplarily shown to be one dielectric layer, and the hermetic release isolation layer 3 covers the first pillar structure 61, at this time, the material constituting the hermetic release isolation layer 3 may include at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium, amorphous carbon, or aluminum oxide, and the thickness of the hermetic release isolation layer 3 is also smaller than that of the sacrificial layer. Through setting up the first columnar structure 61 of airtight release insulating layer 3 cladding, can utilize airtight release insulating layer 3 as the support of first columnar structure 61 department on the one hand, improve first columnar structure 61's stability, guarantee first columnar structure 61 and unsettled microbridge structure 40 and support base 42's electricity and be connected. On the other hand, the airtight release insulating layer 3 covering the first columnar structure 61 can reduce the contact between the first columnar structure 61 and the external environment, reduce the contact resistance between the first columnar structure 61 and the external environment, further reduce the noise of the infrared focal plane detector pixel, improve the detection sensitivity of the infrared detection sensor, and prevent the electrical breakdown of the exposed metal of the first columnar structure 61. Similarly, the resonant cavity of the infrared focal plane detector is realized by releasing the vacuum cavity after the silicon oxide sacrificial layer, the reflective layer 4 is used as the reflective layer of the resonant cavity, the sacrificial layer is positioned between the reflective layer 4 and the suspended microbridge structure 40, and when at least one layer of airtight release isolation layer 3 positioned on the reflective layer 4 is arranged to select silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium, amorphous carbon or aluminum oxide and other materials as a part of the resonant cavity, the reflection effect of the reflective layer 4 is not affected, the height of the resonant cavity can be reduced, the thickness of the sacrificial layer is further reduced, and the release difficulty of the sacrificial layer formed by silicon oxide is reduced. In addition, the sealing release isolation layer 3 and the first columnar structure 61 are arranged to form a sealing structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the protection of the CMOS measurement circuit system 1 is realized.

Fig. 12 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure. Unlike the infrared focal plane detector having the structure shown in the above-mentioned embodiment, in the infrared focal plane detector having the structure shown in fig. 12, the hermetic release insulating layer 3 is located at the interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2, for example, the hermetic release insulating layer 3 is located between the reflective layer 4 and the CMOS measurement circuit system 1, that is, the hermetic release insulating layer 3 is located below the metal interconnection layer of the reflective layer 4, and the supporting base 42 is electrically connected to the CMOS measurement circuit system 1 through a through hole penetrating through the hermetic release insulating layer 3. Specifically, because the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are both formed by using a CMOS process, after the CMOS measurement circuit system 1 is formed, a wafer including the CMOS measurement circuit system 1 is transferred to a next process to form the CMOS infrared sensing structure 2, and since silicon oxide is a most commonly used dielectric material in the CMOS process, and silicon oxide is mostly used as an insulating layer between metal layers on a CMOS circuit, if no insulating layer is used as a barrier when silicon oxide with a thickness of about 2um is corroded, the circuit will be seriously affected, and in order to ensure that the silicon oxide medium on the CMOS measurement circuit system is not corroded when the silicon oxide of a sacrificial layer is released, a closed release insulating layer 3 is provided at an interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 according to the embodiment of the present disclosure. After the CMOS measuring circuit system 1 is prepared and formed, a closed release isolation layer 3 is prepared and formed on the CMOS measuring circuit system 1, the CMOS measuring circuit system 1 is protected by the closed release isolation layer 3, in order to ensure the electric connection between the support base 42 and the CMOS measuring circuit system 1, after the closed release isolation layer 3 is prepared and formed, a through hole is formed in the area of the closed release isolation layer 3 corresponding to the support base 42 by adopting an etching process, and the support base 42 is electrically connected with the CMOS measuring circuit system 1 through the through hole. In addition, the closed release isolation layer 3 and the support base 42 are arranged to form a closed structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the CMOS measurement circuit system 1 is protected.

Illustratively, the material constituting hermetic release barrier layer 3 may include at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium, amorphous carbon, or aluminum oxide. Specifically, silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium, amorphous carbon, or aluminum oxide are all CMOS process corrosion-resistant materials, i.e., these materials are not corroded by the sacrificial layer release agent, so the hermetic release barrier layer 3 can be used to protect the CMOS measurement circuit system 1 from corrosion when the sacrificial layer is released by the corrosion process. In addition, the closed release isolation layer 3 covers the CMOS measurement circuit system 1, and the closed release isolation layer 3 can also be used for protecting the CMOS measurement circuit system 1 from being influenced by the process in the release etching process for manufacturing the CMOS infrared sensing structure 2. In addition, when being provided with the airtight isolated layer 3 that releases of at least one deck on reflection stratum 4, the material that the setting constitutes airtight isolated layer 3 that releases includes carborundum, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium silicon, germanium silicon, at least one in amorphous carbon or the aluminium oxide, when setting up airtight isolated layer 3 that releases and improving first columnar structure 61 stability, airtight isolated layer 3 that releases can hardly influence the reflection course in the resonant cavity, can avoid airtight isolated layer 3 that releases to influence the reflection course of resonant cavity, and then avoid airtight isolated layer 3 that releases to the influence of infrared focal plane detector detectivity.

With reference to fig. 1 to fig. 12, a CMOS manufacturing process of the CMOS infrared sensing structure 2 includes a Metal interconnection process, a via process, an IMD (Inter Metal Dielectric) process, and an RDL (redistribution layer) process, the CMOS infrared sensing structure 2 includes at least three Metal interconnection layers, at least three Dielectric layers, and a plurality of interconnection vias, the Dielectric layers include at least two sacrificial layers and a heat sensitive Dielectric layer, the Metal interconnection layers include at least a reflective layer 4 and two electrode layers, the two electrode layers are a first electrode layer 14 and a second electrode layer 140, the heat sensitive Dielectric layer includes a thermal sensitive material having a temperature coefficient of resistance greater than a predetermined value, the temperature coefficient of resistance may be, for example, greater than or equal to 0.015/K, the thermal sensitive Dielectric layer is formed of a thermal sensitive material having a temperature coefficient greater than the predetermined value, the thermal sensitive Dielectric layer is configured to convert a temperature change corresponding to infrared radiation absorbed by the thermal sensitive Dielectric layer into a resistance change, and further convert an infrared target signal into a signal capable of being electrically read through the CMOS measurement circuit system 1. In addition, the heat-sensitive dielectric layer comprises a heat-sensitive material with the resistance temperature coefficient larger than a set value, the resistance temperature coefficient can be larger than or equal to 0.015/K, and the detection sensitivity of the infrared focal plane detector can be improved.

Specifically, the metal interconnection process is used to realize electrical connection between the upper and lower metal interconnection layers, for example, to realize electrical connection between the first columnar structure 61 and the support pedestal 42, the via process is used to form an interconnection via for connecting the upper and lower metal interconnection layers, for example, to form an interconnection via for connecting the first columnar structure 61 and the support pedestal 42, the IMD process is used to realize isolation, that is, electrical insulation, between the upper and lower metal interconnection layers, for example, to realize electrical insulation between the electrode layers in the absorber plate 10 and the beam structure 11 and the reflector plate 41, the RDL process is a redistribution layer process, that is, a process in which a layer of metal is re-laid above the top metal layer of the circuit and is electrically connected to a metal column on the top metal layer of the circuit, for example, a tungsten column, and the RDL process can be used to re-fabricate the reflective layer 4 in the infrared focal plane detector on the top metal layer of the CMOS measurement circuit system 1, and the support pedestal 42 on the reflective layer 4 is electrically connected to the top metal layer of the CMOS measurement circuit system 1. In addition, as shown in fig. 2, the CMOS manufacturing process of the CMOS measurement circuit system 1 may also include a metal interconnection process and a via process, the CMOS measurement circuit system 1 includes metal interconnection layers 101, dielectric layers 102 and a silicon substrate 103 at the bottom, which are arranged at intervals, and the upper and lower metal interconnection layers 101 are electrically connected through vias 104.

With reference to fig. 1 to 12, the CMOS infrared sensing structure 2 includes a resonant cavity formed by a reflective layer 4 and a heat sensitive medium layer, and a suspended microbridge structure 40 for controlling heat transfer, the CMOS measurement circuit system 1 is configured to measure and process an array resistance value formed by one or more CMOS infrared sensing structures 2, and convert an infrared signal into an image electrical signal, the infrared focal plane detector includes a plurality of infrared focal plane detector pixels arranged in an array, and each infrared focal plane detector pixel includes one CMOS infrared sensing structure 2. Specifically, a resonant cavity may be formed by, for example, a cavity between the reflective layer 4 and the heat-sensitive medium layer in the absorption plate 10, and infrared light is reflected back and forth in the resonant cavity through the absorption plate 10 to improve the detection sensitivity of the infrared focal plane detector.

Fig. 13 is a schematic structural diagram of a CMOS measurement circuit system according to an embodiment of the present disclosure. With reference to fig. 1 to 13, the cmos measurement circuit system 1 includes a bias voltage generation circuit 7, a column-level analog front-end circuit 8 and a row-level circuit 9, an input end of the bias voltage generation circuit 7 is connected to an output end of the row-level circuit 9, an input end of the column-level analog front-end circuit 8 is connected to an output end of the bias voltage generation circuit 7, the row-level circuit 9 includes a row-level mirror image element Rsm and a row selection switch K1, and the column-level analog front-end circuit 8 includes a blind image element RD; the row-level circuit 9 is distributed in each pixel, selects a signal to be processed according to a row strobe signal of the timing sequence generating circuit, and outputs a current signal to the column-level analog front-end circuit 8 under the action of the bias generating circuit 7 to perform current-voltage conversion output; the row stage circuit 9 outputs a third bias voltage VRsm to the bias generation circuit 7 when being controlled by the row selection switch K1 to be gated, the bias generation circuit 7 outputs a first bias voltage V1 and a second bias voltage V2 according to an input constant voltage and the third bias voltage VRsm, and the column stage analog front-end circuit 8 obtains two currents according to the first bias voltage V1 and the second bias voltage V2, performs transimpedance amplification on a difference between the two generated currents, and outputs the amplified current as an output voltage.

Specifically, the row-level circuit 9 includes a row-level mirror image element Rsm and a row selection switch K1, and the row-level circuit 9 is configured to generate a third bias voltage VRsm according to a gating state of the row selection switch K1. Illustratively, the row-level image elements Rsm may be subjected to a shading process, so that the row-level image elements Rsm are subjected to a fixed radiation of a shading sheet having a temperature constantly equal to the substrate temperature, the row selection switch K1 may be implemented by a transistor, the row selection switch K1 is closed, and the row-level image elements Rsm are connected to the bias generation circuit 7, that is, the row-level circuit 9 outputs the third bias voltage VRsm to the bias generation circuit 7 when being controlled by the row selection switch K1 to be turned on. The bias generating circuit 7 may include a first bias generating circuit 71 and a second bias generating circuit 72, the first bias generating circuit 71 being configured to generate a first bias voltage V1 according to an input constant voltage, which may be, for example, a positive power supply signal with a constant voltage. The second bias generating circuit 72 may include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 controlling the gate driving sub-circuits 722 to generate the corresponding second bias voltages V2, respectively, according to the third bias voltage VRsm.

The column-level analog front-end circuit 8 includes a plurality of column control sub-circuits 81, the column control sub-circuits 81 are disposed in correspondence with the gate driving sub-circuits 722, and exemplarily, the column control sub-circuits 81 may be disposed in one-to-one correspondence with the gate driving sub-circuits 722, and the gate driving sub-circuits 722 are configured to provide the second bias voltage V2 to the corresponding column control sub-circuits 81 according to their own gate states. Illustratively, it may be set that when the gate driving sub-circuit 722 is gated, the gate driving sub-circuit 722 supplies the second bias voltage V2 to the corresponding column control sub-circuit 81; when the gate driving sub-circuit 722 is not gated, the gate driving sub-circuit 722 stops supplying the second bias voltage V2 to the corresponding column control sub-circuit 81.

The column-level analog front-end circuit 8 comprises an effective pixel RS and a blind pixel RD, the column control sub-circuit is used for generating a first current I1 according to a first bias voltage V1 and the blind pixel RD, generating a second current I2 according to a second bias voltage V2 and the effective pixel RS, performing transimpedance amplification on a difference value of the first current I1 and the second current I2 and outputting the difference value, and the row-level image pixel Rsm and the effective pixel RS have the same temperature drift amount under the same environment temperature.

Illustratively, the row-level image elements Rsm are thermally insulated from the CMOS measurement circuitry 1 and are shaded, and the row-level image elements Rsm are subjected to a fixed radiation from a shade sheet having a temperature constantly equal to the substrate temperature. The absorption plate 10 of the active pixel RS is thermally insulated from the CMOS measurement circuitry 1 and the active pixel RS receives external radiation. The absorption plates 10 of the row-level mirror image elements Rsm and the effective elements RS are thermally insulated from the CMOS measurement circuitry 1, so that the row-level mirror image elements Rsm and the effective elements RS both have a self-heating effect.

When the row selection switch K1 is used for gating the corresponding row-level mirror image element Rsm, the resistance value of both the row-level mirror image element Rsm and the effective pixel RS changes due to joule heat, but when the row-level mirror image element Rsm and the effective pixel RS are subjected to the same fixed radiation, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective pixel RS are the same, the temperature coefficients of the row-level mirror image element Rsm and the temperature coefficient of the effective pixel RS are also the same, the temperature drift amounts of the row-level mirror image element Rsm and the effective pixel RS at the same environmental temperature are the same, the change of the row-level mirror image element Rsm and the effective pixel RS at the same environmental temperature are synchronized, the resistance value change of the row-level mirror image element Rsm and the effective pixel RS due to the self-heating effect is effectively compensated, and the stable output of the CMOS measurement circuit system 1 is realized.

In addition, the second bias generating circuit 72 is arranged to include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 is configured to control the gate driving sub-circuits 722 to generate corresponding second bias voltages V2 respectively according to the row control signal, so that each row of pixels has one path to drive the whole row of pixels of the row individually, the requirement for the second bias voltage V2 is reduced, that is, the driving capability of the bias generating circuit 7 is improved, and the CMOS measurement circuit system 1 is advantageously used to drive a larger-scale infrared focal plane detector pixel array. In addition, the specific detailed operation principle of the CMOS measurement circuit system 1 is well known to those skilled in the art and will not be described herein.

Alternatively, the CMOS infrared sensing structure 2 may be disposed on an upper layer of a metal interconnection layer of the CMOS measurement circuitry 1 or fabricated on the same layer. Specifically, the metal interconnection layer of the CMOS measurement circuitry 1 may be a top metal layer in the CMOS measurement circuitry 1, and in conjunction with fig. 1 to 12, the CMOS infrared sensing structure 2 may be fabricated on the top metal interconnection layer of the CMOS measurement circuitry 1, and the CMOS infrared sensing structure 2 is electrically connected to the CMOS measurement circuitry 1 through a supporting base 42 on the top metal interconnection layer of the CMOS measurement circuitry 1, so as to transmit the electrical signal converted by the infrared signal to the CMOS measurement circuitry 1.

Fig. 14 is a schematic cross-sectional view of another infrared focal plane detector provided in the embodiments of the present disclosure. As shown in fig. 14, the CMOS infrared sensing structure 2 may also be prepared on the same layer as the metal interconnection layer of the CMOS measurement circuitry 1, that is, the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2 are arranged on the same layer, for example, as shown in fig. 14, the CMOS infrared sensing structure 2 may be arranged on one side of the CMOS measurement circuitry 1, and the top of the CMOS measurement circuitry 1 may also be provided with a hermetic release isolation layer 3 to protect the CMOS measurement circuitry 1.

Optionally, in conjunction with fig. 1 to 14, the sacrificial layer is used to form the CMOS infrared sensing structure 2 into a hollow structure, the material constituting the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process. For example, the post-CMOS process may etch the sacrificial layer using at least one of gases having corrosive properties to silicon oxide, such as gaseous hydrogen fluoride, carbon tetrafluoride, and trifluoromethane. Specifically, sacrificial layers (not shown in fig. 1 to 14) are respectively arranged between the reflection layer 4 and the suspended micro-bridge structure 40 and between the beam structure 11 and the absorption plate 10, when the closed release isolation layer 3 is arranged on the reflection layer 4, the sacrificial layers are arranged between the closed release isolation layer 3 and the suspended micro-bridge structure 40, the sacrificial layers are made of silicon oxide, so as to be compatible with a CMOS process, and a post-CMOS process can be adopted, namely, the post-CMOS process corrodes the sacrificial layers to release the sacrificial layers in a final infrared detection chip product.

Optionally, the absorption plate 10 is configured to absorb an infrared target signal and convert the infrared target signal into an electrical signal, the absorption plate 10 includes a metal interconnection layer and at least one layer of a thermal sensitive medium layer, the metal interconnection layer in the absorption plate 10 is a second electrode layer 140 in the absorption plate 10 and is configured to transmit the electrical signal converted from the infrared signal, the second electrode layer 140 in the absorption plate 10 includes two patterned electrode structures, the two patterned electrode structures output a positive electrical signal and a ground electrical signal respectively, and the positive electrical signal and the ground electrical signal are transmitted to the corresponding support base 42 through a different second pillar structure 62, a different beam structure 11, and a different first pillar structure 61 and are further transmitted to the CMOS measurement circuit system 1. The beam structure 11 comprises at least a metal interconnection layer, the metal interconnection layer in the beam structure 11 is the first electrode layer 14 in the beam structure 11, and the first electrode layer 14 in the beam structure 11 and the second electrode layer 140 in the absorber plate 10 are electrically connected.

The first columnar structure 61 is connected with the corresponding beam structure 11 and the CMOS measurement circuit system 1 by using a metal interconnection process and a through hole process, and with reference to fig. 2 to 14, the upper side of the first columnar structure 61 needs to be electrically connected with the first electrode layer 14 in the beam structure 11 through a through hole penetrating through a sacrificial layer between the reflective layer 4 and the beam structure 11, the lower side of the first columnar structure 6 needs to be electrically connected with the corresponding support base 42 through a through hole penetrating through a dielectric layer on the support base 42, and thus the first electrode layer 14 in the beam structure 11 is electrically connected with the corresponding support base 42 through the corresponding first columnar structure 61. The second columnar structures 62 connect the corresponding absorber plates 10 and the corresponding beam structures 11 through a metal interconnection process and a via process, as shown in fig. 2, the upper portions of the second columnar structures 62 need to be electrically connected to the second electrode layers 140 in the absorber plates 10 through vias penetrating through the sacrificial layers between the absorber plates 10 and the beam structures 11, and the lower portions of the second columnar structures 62 need to be electrically connected to the first electrode layers 14 in the beam structures 11 through vias penetrating through the dielectric layers covering the first electrode layers 14 in the beam structures 11. As shown in fig. 3, the upper side of the second pillar structures 62 needs to be electrically connected to the first electrode layer 14 in the beam structure 11 through via holes penetrating through the sacrificial layer between the absorber plate 10 and the beam structure 11, and the lower side of the second pillar structures 62 needs to be electrically connected to the second electrode layer 140 in the absorber plate 10 through via holes penetrating through the dielectric layer covering the second electrode layer 140 in the absorber plate 10. The reflective plate 41 is used for reflecting infrared signals and forms a resonant cavity with the heat-sensitive medium layer, that is, the reflective plate 41 is used for reflecting infrared signals and forms a resonant cavity with the heat-sensitive medium layer, and the reflective layer 4 includes at least one metal interconnection layer, which is used for forming the supporting base 42 and also used for forming the reflective plate 41.

Optionally, the first pillar structure includes a solid structure, the material constituting the solid structure includes at least one of tungsten, copper or aluminum, and in conjunction with fig. 2, fig. 3, fig. 11 and fig. 14, a sidewall of the solid structure 601 of the first pillar structure 61 may be covered with at least one dielectric layer 602 and the solid structure 601 is disposed in contact with one dielectric layer 602, fig. 2, fig. 3, fig. 11 and fig. 14 exemplarily set a sidewall of the solid structure 601 of the first pillar structure 61 is covered with one dielectric layer 602 and the solid structure 601 is disposed in contact with the dielectric layer 602, the material constituting the solid structure 601 of the first pillar structure 61 includes at least one of tungsten, copper or aluminum, and the material constituting the dielectric layer 602 may include at least one of silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminum oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium, germanium oxide, graphene, copper or platinum. Specifically, at least one dielectric layer 602 of the solid structure 601 covering the first columnar structure 61 can play a role in electrical insulation, and when the dielectric layer 602 is used for protecting the solid structure 601 from being corroded by external materials, the dielectric layer 602 can serve as an auxiliary supporting structure of the first columnar structure 61, and the auxiliary supporting structure and the solid structure 601 jointly support the suspended micro-bridge structure 40, so that the mechanical stability of the first columnar structure 61 is improved, and the structural stability of the infrared sensor is improved. In addition, the material forming the dielectric layer 602 may include at least one of silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminum oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium oxide, silicon, germanium, silicon germanium oxide, graphene, copper, or platinum, and none of the foregoing materials is corroded by gas-phase hydrogen fluoride, carbon tetrafluoride, or trifluoromethane, so that the dielectric layer 602 covering the solid structure 601 is not corroded when the sacrificial layer is corroded by gas-phase hydrogen fluoride, carbon tetrafluoride, and trifluoromethane in the subsequent process steps. Illustratively, as shown in fig. 2, fig. 3, fig. 11, and fig. 14, the dielectric layer 602 coating the solid structure 601 may be set as the first dielectric layer 13 in the beam structure 11, the dielectric layer coating the solid structure 601 may also be a separately manufactured dielectric layer, or the dielectric layer coating the solid structure 601 may also be set as the second dielectric layer 15 in the beam structure 11.

Fig. 15 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure. Fig. 15 only exemplarily shows the first columnar structure 61 and a part of the beam structure 11, the structure above the beam structure 11 is not shown, and unlike the infrared focal plane detector of the structures shown in fig. 2, fig. 3, fig. 11, and fig. 14, the infrared focal plane detector of the structure shown in fig. 15 is configured such that the sidewall of the solid structure 601 of the first columnar structure 61 is disposed in contact with a sacrificial layer (not shown in fig. 15), which is a sacrificial layer between the beam structure 11 and the CMOS measurement circuit system 1, and the material constituting the solid structure 601 includes at least one of tungsten, copper, or aluminum, that is, the first columnar structure 61 only includes a solid tungsten pillar, or a copper pillar, or an aluminum pillar, and the sidewall of the solid structure 601 is disposed in contact with the sacrificial layer, so that the manufacturing process of the first columnar structure 61 is simpler and easier to implement, which is beneficial to reducing the difficulty in manufacturing the entire infrared focal plane detector.

Fig. 16 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure. Fig. 16 also only exemplarily shows the first pillar-shaped structure 61 and a part of the beam structure 11, the structure above the beam structure 11 is not shown, and unlike the infrared focal plane detector of the structures shown in fig. 2, 3, 11, 14 and 15, the infrared focal plane detector of the structure shown in fig. 16 has the sidewall of the solid structure 601 and the surface of the solid structure 601 adjacent to the CMOS measurement circuitry 1 coated with at least one adhesive layer 603, fig. 16 exemplarily provides the sidewall of the solid structure 601 and the surface of the solid structure 601 adjacent to the CMOS measurement circuitry 1 coated with one adhesive layer 603, the sidewall of the adhesion layer 603 on the outermost periphery in the first columnar structure 61, which is far away from the solid structure 601, is coated with a dielectric layer 604, the material forming the solid structure 601 includes at least one of tungsten, copper or aluminum, the material forming the adhesion layer 603 includes at least one of titanium, titanium nitride, tantalum or tantalum nitride, and the material forming the dielectric layer 604 includes at least one of silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminum oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium, germanium silicon germanium, silicon germanium oxide, graphene, copper or platinum.

Specifically, adhesion layer 603 is used for strengthening the connection performance between first columnar structure 61 and the support base 42, including intensifier mechanical connection performance, promote structural stability, also include intensifier electricity connection performance, reduce contact resistance, reduce the loss among the signal transmission process, infrared detection performance of infrared focal plane detector has been promoted, and still surround solid structure 601's side through setting up adhesion layer 603, can increase adhesion layer 603 and solid structure 601's area of contact, be equivalent to the transmission path of widening the signal of telecommunication, the transmission resistance of first columnar structure 61 has been reduced, thereby further reduced signal transmission loss, infrared detection performance of infrared focal plane detector has been promoted. In addition, the material forming the adhesion layer 603 includes at least one of titanium, titanium nitride, tantalum, or tantalum nitride, and the adhesion layer 603 is formed by using at least one of the foregoing four conductive materials, so that the requirement of enhancing the mechanical and electrical connection performance between the supporting base 42 and the first columnar structure 61 by using the adhesion layer 603 can be satisfied, and the requirement of preparing the adhesion layer 603 by using a CMOS process, that is, the requirement of integrating the CMOS process, can be satisfied.

In addition, the adhesion layer 603 on the outermost periphery in the first columnar structure 61 is further coated with a dielectric layer 604 from the side wall of the solid structure 601, the adhesion layer 603 is used for enhancing the connection performance between the first columnar structure 61 and the supporting base 42, and the dielectric layer 604 coating the side wall of the adhesion layer 603 plays a role of insulation protection, and the dielectric layer 604 can be used for playing a role of auxiliary support for the first columnar structure 61, so that the structural stability and the infrared detection performance of the infrared focal plane detector are improved. Similarly, the material forming the dielectric layer 604 may include at least one of silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminum oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium oxide, silicon, germanium, silicon germanium oxide, graphene, copper, or platinum, which are not corroded by the gas phase hydrogen fluoride, carbon tetrafluoride, or trifluoromethane, and thus the dielectric layer 604 covering the adhesion layer 603 is not corroded when the sacrificial layer is corroded by the gas phase hydrogen fluoride, carbon tetrafluoride, and trifluoromethane in the subsequent process steps. For example, as shown in fig. 16, the adhesion layer 603 covering the solid structure 601 may be provided as the first electrode layer 14 in the beam structure 11, the dielectric layer 604 covering the adhesion layer 603 is the first dielectric layer 13 in the beam structure 11, and the adhesion layer 603 covering the solid structure 601 and/or the dielectric layer covering the adhesion layer 603 may also be a separately fabricated film layer, or the dielectric layer covering the adhesion layer 603 may also be provided as the second dielectric layer 15 in the beam structure 11.

Optionally, the second columnar structure includes a solid structure, the material forming the solid structure includes at least one of tungsten, copper, or aluminum, as shown in fig. 2, a sidewall of the solid structure 605 of the second columnar structure 62 may be coated with at least one dielectric layer 606, and the solid structure 605 is disposed in contact with one dielectric layer 606, fig. 2 exemplarily illustrates that a sidewall of the solid structure 605 of the second columnar structure 62 is coated with one dielectric layer 606 and the solid structure 605 is disposed in contact with the dielectric layer 606, the material forming the solid structure 605 of the second columnar structure 62 includes at least one of tungsten, copper, or aluminum, the material forming the dielectric layer 606 may include at least one of silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminum oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium oxide, silicon germanium, germanium oxide, graphene, copper, or platinum, the dielectric layer 606 may be the third dielectric layer 130, and the film layer arrangement manner of the second columnar structure 62 shown in fig. 2 is similar to the film layer arrangement manner of the first columnar structure 61 shown in fig. 2, and specific working principle and effect thereof are no longer repeated. In addition, similar design of the film layer of the second columnar structure 62 can be performed with reference to the first columnar structure 61 in the structures shown in fig. 15 and 16, that is, the second columnar structure 62 can be provided to include a solid structure, the material constituting the solid structure includes at least one of tungsten, copper or aluminum, and the sidewall of the solid structure of the second columnar structure 62 is provided in contact with the sacrificial layer; or the sidewall of the solid structure of the second columnar structure 62 and the surface of the solid structure close to the CMOS measurement circuit system are coated with at least one adhesion layer, the sidewall of the outermost adhesion layer in the second columnar structure 62, which is far from the solid structure, is coated with a dielectric layer, the material forming the adhesion layer includes at least one of titanium, titanium nitride, tantalum or tantalum nitride, the material forming the dielectric layer includes at least one of silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminum oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium oxide, silicon, germanium, silicon germanium oxide, graphene, copper or platinum, which is described in detail in correspondence with the structure shown in fig. 2, the adhesion layer corresponding to the second columnar structure 62 may be the second electrode layer 140, the dielectric layer corresponding to the second columnar structure 62 may be the third dielectric layer 130 or the fourth dielectric layer 150, the adhesion layer corresponding to the structure shown in fig. 3 may be the first electrode layer 14, the dielectric layer corresponding to the second columnar structure 62 may be the first dielectric layer 13 or the second dielectric layer 15, which is not illustrated here.

Fig. 17 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure, and fig. 18 is a schematic cross-sectional structure diagram of another infrared focal plane detector pixel provided in the embodiment of the present disclosure. Fig. 17 and 18 show only the first columnar structure 61 and a part of the beam structure 11 by way of example, and the structure above the beam structure 11 is not shown. With reference to fig. 17 and fig. 18, the infrared focal plane detector may further include a first reinforcing structure 161, where the first reinforcing structure 161 is disposed at a position corresponding to the first columnar structure 61 and located at a side of the first columnar structure 61 away from the CMOS measurement circuit system 1, the first reinforcing structure 161 is configured to enhance connection stability between the first columnar structure 61 and the beam structure 11, and the first reinforcing structure 161 includes a block-shaped weighted structure. Specifically, the first reinforcing structure 161 is arranged to effectively enhance the mechanical stability between the first columnar structure 61 and the beam structure 11, so as to improve the structural stability of the infrared focal plane detector pixel and the infrared focal plane detector including the infrared focal plane detector pixel.

As shown in fig. 17, it may be provided that the weighted mass structure constituting the first reinforcing structure 161 is located on a side of the beam structure 11 away from the CMOS measurement circuitry 1 and the weighted mass structure constituting the first reinforcing structure 161 is disposed in contact with the beam structure 11. Specifically, the weighted block structure forming the first reinforcing structure 161 is disposed on one side of the beam structure 11 away from the CMOS measurement circuit system 1, and the weighted block structure forming the first reinforcing structure 161 is disposed in contact with the beam structure 11, which is equivalent to adding a cover plate at a position of the beam structure 11 corresponding to the first columnar structure 61, and pressing the beam structure by using the self weight of the first reinforcing structure 161, so as to enhance the mechanical strength between the beam structure 11 and the first columnar structure 61, and improve the structural stability of the infrared focal plane detector. As shown in fig. 18, a through hole may be formed in the beam structure 11 corresponding to the position of the first columnar structure 61, the through hole exposes at least a portion of the first columnar structure 61, the weighting block structure forming the first reinforcing structure 161 includes a first portion filling the through hole and a second portion located outside the through hole, and an orthographic projection of the second portion covers an orthographic projection of the first portion. Specifically, the beam structure 11 forms a hollow area corresponding to the position of the first columnar structure 61, that is, a through hole is formed, a second portion of the weighting block structure forming the first reinforcing structure 161 outside the through hole is integrally formed with a first portion of the weighting block structure inside the through hole, the first portion is filled or embedded into the through hole and is in contact with the first columnar structure 61, an orthographic projection of the second portion covers an orthographic projection of the first portion, that is, the area of the second portion is larger than that of the first portion. In the infrared focal plane detector pixel, the first reinforcing structure 161 is equivalent to a rivet structure composed of a first part and a second part, the bottom surface of the first part is in contact with the top surface of the columnar structure, the side surface of the first part is also in contact with the side surface of a hollow area formed by the beam structure, and the lower surface of the second part is in contact with the outer surface of the through hole. Therefore, when the first reinforcing structure 161 is pressed against the beam structure 11 by the gravity of the first reinforcing structure 161, the contact area between the first reinforcing structure 161 and the first columnar structure 61 and the beam structure 11 is increased, the mechanical strength between the beam structure 11 and the first columnar structure 61 is further increased, and the structural stability of the infrared focal plane detector is improved.

Illustratively, the material that may be provided to constitute the weighted bulk structure of the first reinforcing structure 161 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, silicon carbonitride, silicon oxide, silicon, germanium, silicon germanium, aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, or nickel-silicon alloy. Specifically, the first reinforcing structure 161 may be a single-layer structure deposited by a medium or a metal, or may be a multilayer structure formed by stacking two, three, or more single-layer structures, where amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, silicon carbonitride, silicon, germanium, silicon germanium, aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, and nickel-silicon alloy are not corroded by gas-phase hydrogen fluoride, carbon tetrafluoride, or trifluoromethane, so that the first reinforcing structure 161 is not affected during the process of corroding the sacrificial layer with gas-phase hydrogen fluoride, carbon tetrafluoride, or trifluoromethane to release the sacrificial layer, thereby improving the structural stability of the infrared focal plane detector. In addition, when the material constituting the reinforcing structure 16 includes silicon oxide, since silicon oxide may be corroded by gas-phase hydrogen fluoride, carbon tetrafluoride, or trifluoromethane, it is preferable that the reinforcing structure 16 is disposed in a closed space surrounded by the first dielectric layer 13 and the second dielectric layer 15.

Optionally, the infrared focal plane detector may further include a second reinforcing structure, the second reinforcing structure is disposed corresponding to the position of the second columnar structure 62 and located on a side of the second columnar structure 62 away from the CMOS measurement circuit system 1, and the second reinforcing structure includes a weighted block structure. Exemplarily, the second reinforcing structure provided corresponding to the second columnar structure 62 may be provided with reference to the first reinforcing structure 162 corresponding to the first columnar structure 61 in the structures shown in fig. 17 and 18, for example, the structure shown in fig. 2 may be provided such that the weighted block structure constituting the second reinforcing structure is located on the side of the absorber plate 10 away from the CMOS measurement circuit system 1 and the weighted block structure constituting the second reinforcing structure is provided in contact with the absorber plate 10, in analogy to fig. 17; alternatively, in analogy with fig. 18, the absorber plate 10 is provided with a through hole corresponding to the position of the second columnar structure 62, the through hole exposes at least part of the second columnar structure 62, the weighted block-shaped structure forming the second reinforcing structure comprises a first part filling the through hole and a second part located outside the through hole, and the orthographic projection of the second part covers the orthographic projection of the first part. Corresponding to the structure shown in fig. 3, it is possible to arrange the weighted block structure constituting the second reinforcing structure at a side of the beam structure 11 away from the CMOS measurement circuitry 1 and to arrange the weighted block structure constituting the second reinforcing structure in contact with the beam structure 11, in analogy to fig. 17; or, in analogy to fig. 18, the beam structure 11 is provided with a through hole corresponding to the position of the second columnar structure 62, the through hole exposes at least part of the second columnar structure 62, the weighted block structure forming the second reinforcing structure includes a first part filling the through hole and a second part located outside the through hole, and the orthographic projection of the second part covers the orthographic projection of the first part, which is not illustrated any more. In addition, the reinforcement principle of the second reinforcement structure is similar to that of the first reinforcement structure 161 shown in fig. 17 and 18, and will not be described herein again, and for the structure shown in fig. 2, the second reinforcement structure is used to enhance the mechanical stability between the second columnar structure 62 and the absorbent panel 10, and for the structure shown in fig. 3, the second reinforcement structure is used to enhance the mechanical stability between the second columnar structure 62 and the beam structure 11.

Optionally, in conjunction with fig. 1 to 18, at least one patterned metal interconnection layer may be disposed between the reflective layer 4 and the suspended microbridge structure 40, the patterned metal interconnection layer is located above or below the hermetic release barrier layer 3 and is electrically insulated from the reflective layer 4, and the patterned metal interconnection layer is used for adjusting a resonant mode of the infrared focal plane detector. Specifically, a Bragg reflector (Bragg reflector) is an optical device for enhancing reflection of light with different wavelengths by utilizing constructive interference of reflected light with different interfaces, and is composed of a plurality of 1/4 wavelength reflectors to realize efficient reflection of incident light with a plurality of wavelengths, in the embodiment of the disclosure, at least one patterned metal interconnection layer is arranged between the reflection layer 4 and the suspended microbridge structure 40, at least one patterned metal interconnection layer, the reflection layer 4 and the absorption plate 10 form a structure similar to the Bragg reflector, and the arrangement of the at least one patterned metal interconnection layer is equivalent to changing the thickness of an integral resonant cavity medium formed by the reflection layer 4 and a heat sensitive medium layer in the absorption plate 10, so that a plurality of resonant cavities with different medium thicknesses can be formed by an infrared focal plane detector pixel, the infrared focal plane detector pixel can select light with different wavelengths to perform enhanced reflection adjustment, and then the resonant mode of the infrared focal plane detector is adjusted by utilizing the at least one patterned metal interconnection layer, thereby improving and widening the infrared absorption rate of the infrared focal plane detector, increasing the infrared absorption spectrum band of the infrared focal plane detector.

Illustratively, at least one patterned metal interconnect layer may be disposed on a side of the hermetic release barrier 3 away from the CMOS measurement circuitry 1 and/or at least one patterned metal interconnect layer may be disposed on a side of the hermetic release barrier 3 adjacent to the CMOS measurement circuitry 1. Illustratively, the patterned metal interconnection layer may include a plurality of metal repeating units arranged in an array, each metal repeating unit may include at least one of an L-shaped patterned structure, a circular structure, a sector-shaped structure, an elliptical structure, a circular ring structure, an open ring structure, or a polygonal structure arranged at two opposite corners, or the patterned metal interconnection layer may include a plurality of patterned hollow structures arranged in an array, and the patterned hollow structures may include at least one of a circular hollow structure, an open ring-shaped hollow structure, or a polygonal hollow structure.

Fig. 19 is a schematic cross-sectional view of another infrared focal plane detector provided in the embodiments of the present disclosure. On the basis of the above embodiment, as shown in fig. 19, the first dielectric layer 13 and/or the second dielectric layer 15 between the oppositely disposed beam structures 11 may be disposed to form a patterned film structure, where the oppositely disposed beam structures 11 are the beam structures 11 located at the left and right sides in fig. 1 or the beam structures 11 located at the upper and lower sides in fig. 1, and the patterned film structure includes a plurality of stripe patterns, and the stripe patterns in the patterned film structure are symmetrically disposed with respect to the beam structures 11. Taking the first dielectric layer 13 as an example, fig. 20 is a schematic top view structure diagram of the first dielectric layer according to an embodiment of the disclosure. Referring to fig. 19 and 20, the first dielectric layer 13 between the oppositely disposed beam structures 11 may be disposed to form a patterned film structure 90 as shown in fig. 20, where the patterned film structure 90 is located in the region A1 in fig. 19, the patterned film structure 90 includes a plurality of stripe patterns 91, and the stripe patterns 91 in the patterned film structure 90 are symmetrically disposed with respect to the beam structures 11, that is, the stripe patterns 91 in the patterned film structure 90 are symmetrically disposed with respect to the beam structures 11 on the left and right sides in fig. 20. Therefore, the patterned film structure 90 is formed by arranging the first dielectric layer 13 and/or the second dielectric layer 15 between the beam structures 11 which are arranged oppositely, the patterned film structure 90 comprises a plurality of strip-shaped patterns 91, and the strip-shaped patterns 91 in the patterned film structure 90 are symmetrically arranged relative to the beam structures 11, so that the mechanical stability of the patterned film structure 90 is effectively improved, and the mechanical stability of the whole infrared focal plane detector is further improved. It should be noted that the pattern in the patterned film structure 90 according to the embodiment of the disclosure is not limited to the pattern form shown in fig. 20, for example, the patterned film structure 90 may further include more stripe patterns to form a grid structure, and the like, and the embodiment of the disclosure does not limit the specific pattern in the patterned film structure 90, so as to ensure that the stripe patterns in the patterned film structure 90 are symmetrical with respect to the beam structure 11, and the patterns in the patterned film structure 90 formed by the first dielectric layer 13 and the second dielectric layer 15 may be the same or different.

Alternatively, the infrared focal plane detector may be configured based on a 3nm, 7nm, 10nm, 14nm, 22nm, 28nm, 32nm, 45nm, 65nm, 90nm, 130nm, 150nm, 180nm, 250nm or 350nm CMOS process, where the aforementioned dimensions represent process nodes of the integrated circuit, i.e., feature dimensions during the processing of the integrated circuit. Alternatively, the metal wiring material constituting the metal interconnection layer in the infrared focal plane detector may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt, and for example, the material constituting the reflective layer 4 may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt. In addition, the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by using a CMOS process, and the CMOS infrared sensing structure 2 is directly prepared on the CMOS measurement circuit system 1, so that the radial side lengths of the first columnar structure 61 and the second columnar structure 62 can be greater than or equal to 0.5um and less than or equal to 3um, the width of the beam structure 11, that is, the width of a single line in the beam structure 11 is less than or equal to 0.3um, and the height of the resonant cavity is less than or equal to 2.5um.

It is noted that, in this document, relational terms such as "first" and "second," and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An infrared focal plane detector, comprising:

the CMOS manufacturing process of the CMOS infrared sensing structure comprises a metal interconnection process, a through hole process, an IMD (in-mold decoration) process and an RDL (remote description language) process, wherein the CMOS infrared sensing structure comprises at least three metal interconnection layers, at least three dielectric layers and a plurality of interconnection through holes, the three metal interconnection layers comprise a reflecting layer and two electrode layers, and the three dielectric layers comprise two sacrificial layers and one heat-sensitive dielectric layer; the thermal sensitive medium layer is used for converting temperature change corresponding to infrared radiation absorbed by the thermal sensitive medium layer into resistance change, and further converting an infrared target signal into a signal capable of realizing electric reading through the CMOS measuring circuit system;

along the direction far away from the CMOS measuring circuit system, the beam structure sequentially comprises a first dielectric layer, a first electrode layer and a second dielectric layer, the first dielectric layer and/or the second dielectric layer between the oppositely arranged beam structures form a patterned film layer structure, the patterned film layer structure comprises a plurality of strip-shaped patterns, and the patterns in the patterned film layer structure are symmetrically arranged relative to the beam structure;

the column-level analog front-end circuit obtains two paths of currents according to the first bias voltage and the second bias voltage, performs transimpedance amplification on the difference of the two paths of generated currents, and outputs the amplified currents as output voltage.

2. The infrared focal plane detector of claim 1, wherein the CMOS infrared sensing structure is fabricated on top of or on the same layer as a metal interconnect layer of the CMOS measurement circuitry.

3. The infrared focal plane detector of claim 1, wherein the sacrificial layer is used to make the CMOS infrared sensing structure form a hollowed-out structure, the material of the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process.

4. The infrared focal plane detector of claim 1, wherein the reflective layer is configured to reflect infrared signals and form the resonant cavity with the thermal sensitive dielectric layer, the reflective layer comprises at least one metal interconnection layer, the first pillar structure connects the beam structure and the CMOS measurement circuitry using the metal interconnection process and the via process, and the second pillar structure connects the absorber plate and the beam structure using the metal interconnection process and the via process;

the absorption plate sequentially comprises the third dielectric layer, the second electrode layer and the fourth dielectric layer along the direction far away from the CMOS measuring circuit system; the material for forming the first dielectric layer comprises at least one of amorphous silicon, amorphous germanium-silicon, amorphous carbon or aluminum oxide, the material for forming the second dielectric layer comprises at least one of amorphous silicon, amorphous germanium-silicon, amorphous carbon or aluminum oxide, the material for forming the third dielectric layer comprises at least one of materials with the resistance temperature coefficient larger than a set value and prepared from amorphous silicon, amorphous germanium-silicon or amorphous carbon, and the material for forming the fourth dielectric layer comprises at least one of materials with the resistance temperature coefficient larger than the set value and prepared from amorphous silicon, amorphous germanium-silicon or amorphous carbon; alternatively, the first and second electrodes may be,

along the direction far away from the CMOS measuring circuit system, the absorption plate sequentially comprises the third dielectric layer, the second electrode layer, the heat-sensitive dielectric layer and the fourth dielectric layer or the absorption plate sequentially comprises the third dielectric layer, the heat-sensitive dielectric layer, the second electrode layer and the fourth dielectric layer; the material forming the first dielectric layer comprises at least one of amorphous silicon, amorphous germanium-silicon, amorphous carbon or aluminum oxide, the material forming the second dielectric layer comprises at least one of amorphous silicon, amorphous germanium-silicon, amorphous carbon or aluminum oxide, the material forming the third dielectric layer comprises at least one of amorphous silicon, amorphous germanium-silicon, amorphous carbon or aluminum oxide, the material forming the fourth dielectric layer comprises at least one of amorphous silicon, amorphous germanium-silicon, amorphous carbon or aluminum oxide, and the material forming the heat-sensitive dielectric layer comprises at least one of materials prepared from titanium oxide, vanadium oxide, silicon, germanium-silicon, germanium-oxygen-silicon, graphene, strontium barium titanate thin film, copper or platinum, wherein the resistance temperature coefficient of the material forming the heat-sensitive dielectric layer is larger than a set value;

5. The infrared focal plane detector of claim 4, wherein the first cylindrical structure comprises a solid structure composed of a material comprising at least one of tungsten, copper, or aluminum;

the side wall of the solid structure is coated with at least one dielectric layer, the solid structure is arranged in contact with the dielectric layer, and the material for forming the dielectric layer comprises at least one of silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminum oxide, titanium oxide, vanadium oxide, silicon, germanium, silicon germanium oxide, graphene, copper or platinum; alternatively, the first and second electrodes may be,

solid construction's lateral wall and solid construction closes on CMOS measures circuit system's surface cladding has at least one deck adhesion coating, to outlying in the first columnar structure the adhesion coating is kept away from solid construction's lateral wall cladding has the dielectric layer, constitutes the material of adhesion coating includes at least one among titanium, titanium nitride, tantalum or the tantalum nitride, constitutes the material of dielectric layer includes at least one among silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminium oxide, titanium oxide, vanadium oxide, silicon, germanium, silicon germanium, germanium oxygen silicon, graphite alkene, copper or platinum.

6. The infrared focal plane detector of claim 4, wherein the second cylindrical structure comprises a solid structure composed of a material comprising at least one of tungsten, copper, or aluminum;

solid construction's lateral wall and solid construction closes on CMOS measures circuit system's surface cladding has at least one deck adhesion layer, outermost periphery in the second columnar structure adhesion layer is kept away from solid construction's lateral wall cladding has the dielectric layer, constitutes the material of adhesion layer includes at least one of titanium, titanium nitride, tantalum or tantalum nitride, constitutes the material of dielectric layer includes at least one in silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminium oxide, titanium oxide, vanadium oxide, silicon, germanium, silicon germanium, germanium oxygen silicon, graphite alkene, copper or the platinum.

7. The infrared focal plane detector of claim 4, wherein the absorber plate has at least one hole structure formed thereon, the hole structure penetrating at least through the medium layer in the absorber plate; and/or at least one hole-shaped structure is formed on the beam structure, and the hole-shaped structure at least penetrates through the dielectric layer in the beam structure.

8. The infrared focal plane detector of claim 1, further comprising a first reinforcing structure, wherein the first reinforcing structure is disposed corresponding to a position of the first columnar structure and located on a side of the first columnar structure away from the CMOS measurement circuitry, the first reinforcing structure is configured to enhance connection stability between the first columnar structure and the beam structure, and the first reinforcing structure comprises a weighted block structure;

the weighting block structure is positioned on one side of the beam structure far away from the CMOS measuring circuit system and is in contact with the beam structure; or a through hole is formed in the position, corresponding to the first columnar structure, of the beam structure, at least part of the first columnar structure is exposed out of the through hole, the weighting block structure comprises a first part and a second part, the first part is filled in the through hole, the second part is located outside the through hole, and the orthographic projection of the second part covers the orthographic projection of the first part.

9. The infrared focal plane detector of claim 1, further comprising a second reinforcing structure, wherein the second reinforcing structure is disposed at a position corresponding to the second columnar structure and at a side of the second columnar structure away from the CMOS measurement circuitry, and the second reinforcing structure comprises a weighted block structure;

10. The infrared focal plane detector of claim 1, wherein the hermetic release isolation layer is located at an interface between the CMOS measurement circuitry and the CMOS infrared sensing structure and/or in the CMOS infrared sensing structure;

the closed release isolation layer is positioned on the reflection layer and is in contact with the reflection layer, the closed release isolation layer comprises at least one dielectric layer, and the material forming the closed release isolation layer comprises at least one of silicon carbide, silicon carbonitride, silicon nitride, silicon, germanium, silicon germanium, amorphous carbon or aluminum oxide.