CN110006538A

CN110006538A - A kind of no TEC un-cooled infrared focal plane array reading circuit

Info

Publication number: CN110006538A
Application number: CN201910213758.6A
Authority: CN
Inventors: 施薛优; 陈光毅
Original assignee: Beijing Anku Zhixin Technology Co Ltd
Current assignee: Beijing Anku Zhixin Technology Co Ltd
Priority date: 2019-03-20
Filing date: 2019-03-20
Publication date: 2019-07-12
Anticipated expiration: 2039-03-20
Also published as: CN110006538B

Abstract

The present invention discloses a kind of no TEC un-cooled infrared focal plane array reading circuit, is related to un-cooled infrared focal plane array technical field.The reading circuit includes bias generating circuit, column grade analog front circuit and row grade circuit；Row grade circuit, including row class mirror-image pixel are selected switch control by row, can export third bias voltage；Bias generating circuit, with row grade circuit connection, input terminal connects the output end of row grade circuit；It is generated according to the constant pressure of input and third bias voltage and exports the first bias voltage and the second bias voltage；Column grade analog front circuit, including blind element；Column grade analog front circuit is connect with bias generating circuit, and input terminal connects the output end of bias generating circuit, obtains two-way electric current, and carry out generated two-way difference between currents across resistance amplification and as voltage output.Using technical solution of the present invention, makes circuit that there is the stabilization output point not influenced by underlayer temperature and self-heating effect, enhance the stability of circuit.

Description

Non-refrigeration infrared focal plane array reading circuit without TEC

Technical Field

The invention relates to the technical field of uncooled infrared focal plane arrays, in particular to a read-out circuit of an uncooled infrared focal plane array without a TEC (thermoelectric cooler).

Background

The read-out circuit is one of key components of an uncooled infrared focal plane array (IRFPA), and has the main functions of preprocessing (such as integration, amplification, filtering, sampling/holding and the like) weak signals sensed by an infrared detector and performing parallel/serial conversion on array signals.

In the prior art, a conventional up-down differential current sensing structure circuit shown in fig. 1 of the specification can eliminate the substrate temperature effect and amplify signals in one step, and offset correction can be performed by adjusting Veb and Vfid bias voltages; the disadvantages are mainly: 1. the noise of the front-end bias voltage is directly amplified, so that the requirement on the bias voltage noise is high; 2. due to the self-heating effect, the resistance values of the pixel blind pixels are unequal, and the output bias point cannot be automatically determined; 3. the circuit gain of the circuit is greatly changed along with the temperature of the substrate, so that the possible loss of a dynamic range and the failure of offset correction under different substrate temperatures are caused;

therefore, in the conventional reading circuit, due to the influence of process deviation, self-heating effect and substrate temperature, the fluctuation of data to be read is large, and some unnecessary noise is introduced to seriously influence the reading quality and the stability of the circuit.

Disclosure of Invention

In order to solve the problems in the prior art, the embodiment of the invention provides a non-refrigeration infrared focal plane array reading circuit without a TEC.

The embodiment of the application provides a TEC-free uncooled infrared focal plane array readout circuit, which comprises a bias voltage generation circuit, a column-level analog front-end circuit and a row-level circuit; wherein,

the row-level circuit comprises a row-level mirror image element (rssm) and a row selection switch (RSEL)) (ii) a When the row level circuit is selected by the Row Switch (RSEL)) When controlled to be gated, a third bias voltage (V) is output to the bias voltage generation circuit_Rsm)；

The input end of the bias voltage generating circuit is connected with the output end of the row level circuit; according to input constant voltage (V)_b) And a third bias voltage (V)_Rsm) Generating and outputting a first bias voltage (Veb) and a second bias voltage (V)_fid)；

The column-level analog front-end circuit comprises a blind cell (Rd); the input end of the column-level analog front-end circuit is connected with the output end of the bias voltage generating circuit according to a first bias voltage (Veb) and a second bias voltage (V)_fid) Two currents are obtained, and the difference (I) between the two generated currents is calculated_diff) Is trans-resistance amplified and used as output voltage (V)_agc) And (6) outputting.

Preferably, the bias voltage generating circuit includes at least a first bias voltage generating sub-circuit and a second bias voltage generating sub-circuit outputting a first bias voltage (Veb) and a second bias voltage (V), respectively_fid)。

In some embodiments, when constant voltage (V)_b) When the voltage is input, the grid voltage of a PMOS tube in the first bias voltage generation sub-circuit is used as a first bias voltage (Veb) and is output to the column-level analog front-end circuit;

the second bias voltage generation sub-circuit generates a second bias voltage according to a third bias voltage (V)_Rsm) Generating a second bias voltage (V)_fid) Applying a second bias voltage (V) to the source follower structure circuit in the second bias generating sub-circuit_fid) Copied and output to the column-level analog front-end circuit.

Preferably, the first bias voltage generating sub-circuit is connected with the second bias voltage generating sub-circuit, the row-level circuit and the column-level analog front-end circuit; at least comprises a first mirror image circuit, a second mirror image circuit, a first circuitOperational amplifier (OPA1), first mirror blind pixel (R)_dm0) A second mirror image blind pixel (R)_dm1) And a power supply (Vsk);

the first mirror image circuit is respectively connected with the second mirror image circuit, the first operational amplifier (OPA1) and the first mirror image blind pixel (R)_dm0) A second mirror image blind pixel (R)_dm1) And (4) connecting.

Preferably, the first mirror circuit comprises a first PMOS transistor (MP1) and a second PMOS transistor (MP2), and the gate of the first PMOS transistor (MP1) is connected to the gate of the second PMOS transistor (MP 2); the second mirror image circuit comprises a first NMOS transistor (MN1) and a second NMOS transistor (MN2), wherein the grid electrode of the first NMOS transistor (MN1) is connected with the grid electrode of the second NMOS transistor (MN 2);

first mirror image blind pixel (R)_dm0) First terminal, second mirror image blind pixel (R)_dm1) Are connected to a power supply (Vsk); the source and drain of the first PMOS transistor (MP1) are respectively connected with the first mirror image blind pixel R_dm0The second end of the first NMOS tube (MN1) and the drain electrode of the first NMOS tube are connected; the source and drain of the second PMOS transistor (MP2) are respectively connected with the second mirror image blind pixel (R)_dm1) The second end of the first transistor is connected with the row level circuit; the drain electrode of the second NMOS tube (MN2) is connected with the second bias voltage generating sub-circuit; the source electrode of the first NMOS transistor (MN1) and the source electrode of the second NMOS transistor (MN2) are grounded;

the negative input end, the positive input end and the output end of the first operational amplifier (OPA1) are respectively connected with the source electrode and the constant voltage (V) of the first PMOS tube (MP1)_b) And the grid electrode of the first PMOS tube (MP 1).

Preferably, in the first bias generation sub-circuit, when a constant voltage is input, the gate voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) in the first mirror circuit are output to the column-stage analog front-end circuit as a first bias voltage (Veb).

Preferably, the first bias voltage generating sub-circuit further comprises a decoupling capacitor (C1); a first terminal and a second terminal of the decoupling capacitor (C1) are connected to a power supply (Vsk) and a first mirror circuit, respectively.

Preferably, the second bias voltage generating sub-circuit is connected with the first bias voltage generating sub-circuit, the row-level circuit and the column-level analog front-end circuit; at least comprises a first source following structure circuit, a second source following structure circuit, a third NMOS tube (MN3) and a second operational amplifier (OPA 2);

the grid and the source of the third NMOS tube (MN3) are respectively connected with the first source follower structure circuit and the first bias voltage generating sub-circuit; the second source following structure circuit is connected with the first source following structure circuit; the negative input end, the positive input end and the output end of the second operational amplifier (OPA2) are respectively connected with the source electrode of the third NMOS tube (MN3), the row-level circuit and the first source follower structure circuit.

Preferably, the first source follower structure circuit comprises a first current source (Ib3) and a third PMOS transistor (MP 3); the second source follower structure circuit comprises a second current source (Ib4) and a fourth PMOS tube (MP 4);

the source electrode of the third PMOS tube (MP3) is connected to the first current source (Ib3), and the source electrode of the fourth PMOS tube (MP4) is connected to the second current source (Ib 4); the source electrode of the third PMOS tube (MP3) is connected with the gate electrode of the third NMOS tube (MN 3); the output end of the second operational amplifier (OPA2) is connected with the grid electrode of the third PMOS tube (MP3) and the grid electrode of the third PMOS tube (MP3) is connected with the grid electrode of the fourth PMOS tube (MP 4).

Preferably, the second bias generating sub-circuit generates the third bias voltage (V) according to the output of the row stage circuit_Rsm) Obtaining the source voltage of the third PMOS tube (MP3), copying the source voltage of the third PMOS tube (MP3) to the source of the fourth PMOS tube (MP4) through the first source following structure circuit and the second source following structure circuit and using the copied source voltage as a second bias voltage (V)_fid) And the output is output to the column-level analog front-end circuit.

Preferably, the column-level analog front-end circuit at least comprises a pixel-level sub-circuit, a power supply (Vsk), a blind cell (Rd), a fifth PMOS transistor (MP0), a fourth NMOS transistor (MN0), and an automatic gain calibration sub-circuit; the grid of the fifth PMOS tube (MP0) and the grid of the fourth NMOS tube (MN0) are both connected with the bias voltage generating circuit, and are respectively used as the input end of the column-level analog front-end circuit to receive a first bias voltage (Veb) and a second bias voltage (V)_fid)；

The first end and the second end of the blind element (Rd) are respectively connected with a power supply (Vsk) and a source electrode of a fifth PMOS (MP 0); the drain and the source of the fourth NMOS transistor (MN0) are respectively connected with the drain and the pixel level sub-circuit of the fifth PMOS transistor (MP 0); wherein the pixel level sub-circuit comprises a picture element (Rs).

Preferably, the automatic gain calibration sub-circuit comprises at least a third operational amplifier (OPA0), a transimpedance (Rg) and a capacitance (Cc);

the negative input end of the third operational amplifier (OPA0) is connected with the drain electrode of the fifth PMOS tube (MP 0); the first end of the capacitor (Cc) and the first end of the transimpedance (Rg) are both connected with the negative input end of the third operational amplifier (OPA 0); the second end of the capacitor (Cc) and the second end of the transimpedance (Rg) are both connected with the output end of the third operational amplifier (OPA 0); wherein the third operational amplifier (OPA0) outputs an output voltage (V)_agc)。

In other embodiments, the first bias generating sub-circuit is configured to generate a constant voltage (V)_b) When the voltage is input, the grid voltage of an NMOS tube contained in the first mirror image circuit is used as a first bias voltage (Veb) and is output to the column-level analog front-end circuit;

the second bias voltage generation sub-circuit generates a third bias voltage (V) according to the output of the row stage circuit_Rsm) Obtaining the grid voltage of the third PMOS tube (MP3) as a second bias voltage (V)_fid) And the output is output to the column-level analog front-end circuit.

Preferably, the first bias voltage generating sub-circuit is connected with the second bias voltage generating sub-circuit, the row-level circuit and the column-level analog front-end circuit; at least comprises a first mirror image circuit, a second mirror image circuit, a first operational amplifier (OPA1), a second operational amplifier (OPA2), a first mirror image blind pixel (R)_dm0) And a second mirror image blind pixel (R)_dm1)；

The first mirror image circuit is connected with the second mirror image circuit, the second bias voltage generating sub-circuit and the row level circuit; first mirror image blind pixel (R)_dm0) First terminal, second mirror image blind pixel (R)_dm1) The first ends of the first and secondA mirror circuit connection; the first operational amplifier (OPA1) and the second operational amplifier (OPA2) are connected to the first mirror circuit and the second mirror circuit, respectively.

Preferably, the first mirror circuit comprises a first NMOS transistor (MN1) and a second NMOS transistor (MN2), and the gate of the first NMOS transistor (MN1) is connected with the gate of the second NMOS transistor (MN 2); the negative input terminal, the positive input terminal and the output terminal of the first operational amplifier (OPA1) are respectively connected with the source electrode and the constant voltage (V) of the first NMOS transistor (MN1)_b) The grid electrode of the first NMOS tube (MN1) is connected;

the second mirror image circuit comprises a third NMOS transistor (MN3) and a fourth NMOS transistor (MN4), and the grid electrode of the third NMOS transistor (MN3) is connected with the grid electrode of the fourth NMOS transistor (MN 4); the negative input end, the positive input end and the output end of the second operational amplifier (OPA2) are respectively connected with the source electrode of the third NMOS tube (MN3), the common-mode voltage Vcm and the grid electrode of the third NMOS tube (MN 3); the drain of the third NMOS transistor (MN3) and the drain of the fourth NMOS transistor (MN4) are respectively connected to the second bias generation sub-circuit and the column circuit.

Preferably, in the first bias generating sub-circuit, when the voltage is constant (V)_b) When the voltage is input, the first mirror circuit comprises the grid voltage of a first NMOS tube (MN1) and a second NMOS tube (MN2) as a first bias voltage (Veb), and the first bias voltage is output to the column-level analog front-end circuit.

Preferably, the second bias voltage generating sub-circuit is connected with the first bias voltage generating sub-circuit, the row-level circuit and the column-level analog front-end circuit; the power supply circuit at least comprises a third mirror image circuit, a third PMOS tube (MP3), a fourth PMOS tube (MP4), a third operational amplifier (OPA3), a fourth operational amplifier (OPA4) and a common-mode power supply (Vdet);

the third mirror image circuit comprises a first PMOS tube (MP1) and a second PMOS tube (MP2), and the grid electrode of the first PMOS tube (MP1) is connected with the grid electrode of the second PMOS tube (MP 2); the source electrode of the first PMOS tube (MP1) and the source electrode of the second PMOS tube (MP2) are both connected with a common mode power supply (Vdet), and the drain electrode of the first PMOS tube (MP1) is connected with the first bias voltage generating sub-circuit; the source electrode and the drain electrode of the third PMOS tube (MP3) are respectively connected with the drain electrode of the second PMOS tube (MP2) and the source electrode of the fourth PMOS tube (MP 4); the positive input end, the negative input end and the output end of the third operational amplifier (OPA3) are respectively connected with the column-level circuit, the source electrode of the third PMOS tube (MP3) and the grid electrode of the third PMOS tube (MP 3); the positive input end, the negative input end and the output end of the fourth operational amplifier (OPA4) are respectively connected with the common-mode voltage Vcm, the source electrode of the fourth PMOS transistor (MP4) and the gate electrode of the fourth PMOS transistor (MP 4).

Preferably, the second bias generating sub-circuit generates the third bias voltage (V) according to the output of the row stage circuit_Rsm) Obtaining the grid voltage of the third PMOS tube (MP3) as a second bias voltage (V)_fid) And the output is output to the column-level analog front-end circuit.

Preferably, the column-level analog front-end circuit comprises a pixel-level sub-circuit, a common-mode power supply (Vdet), a blind pixel (Rd), a fifth PMOS transistor (MP0), a fourth NMOS transistor (MN0), and an automatic gain calibration sub-circuit;

the source and the drain of the fifth PMOS tube (MP0) are respectively connected with the pixel-level sub-circuit and the drain of the fourth NMOS tube (MN 0); the first end of the blind element (Rd) is connected with the source electrode of a fifth NMOS (N-channel metal oxide semiconductor) tube (MN0), and the second end of the blind element (Rd) is grounded; the automatic gain calibration sub-circuit is connected with the drain electrode of the fifth PMOS tube (MP 0);

the gate of the fifth PMOS transistor (MP0) and the gate of the fifth NMOS transistor (MN0) are both connected to the bias voltage generating circuit, and respectively serve as the input terminal of the column-level analog front-end circuit to receive the first bias voltage (Veb) and the second bias voltage (V)_fid)。

Preferably, the column-level analog front-end circuit generates a first current according to the received first bias voltage (Veb) and the blind cell (Rd); the column-level analog front-end circuit is based on the received second bias voltage (V)_fid) And a pixel (Rs) included in the column-level analog front-end circuit generates a second current; obtaining the difference (I) between the two currents according to the first current and the second current_diff)。

The invention has the beneficial effects that: the invention discloses a TEC-free uncooled infrared focal plane array reading circuit which generates a first bias voltage (Veb) and a second bias voltage (V)_fid) Can make electricityThe circuit has a stable output point which is not influenced by the temperature of the substrate and the self-heating effect, the introduced noise is less, the wider working temperature range is ensured, and the stability of the circuit is enhanced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a circuit of a conventional lower differential current sensing architecture;

FIG. 2 is a block diagram of a reading point circuit of a non-refrigerated infrared focal plane array without TEC according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a reading point circuit of a TEC-free uncooled infrared focal plane array according to a second embodiment of the present invention;

FIG. 4 is a schematic diagram of a conventional second bias voltage generating circuit according to a second embodiment of the present invention;

FIG. 5 is a schematic diagram of a conventional second bias voltage generating circuit according to a second embodiment of the present invention;

fig. 6 is a schematic circuit diagram of a reading point circuit of an uncooled infrared focal plane array without TEC disclosed in the third embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example one

As shown in the circuit block diagram of fig. 2, the non-TEC uncooled infrared focal plane array readout circuit is disclosed, which includes a bias voltage generation circuit 2, a column-level analog front-end circuit 3, and a row-level circuit 1; the bias voltage generating circuit 2 is respectively connected with the column-level analog front-end circuit 3 and the row-level circuit 1;

the row-level circuit 1 comprises row-level mirror image pixels and a row selection switch; the row level circuit 1 is controlled by a row selection switch and can output a third bias voltage;

the input end of the bias generation circuit 2 is connected with the output end of the row stage circuit 1 and is used for generating and outputting a first bias voltage and a second bias voltage together with a third bias voltage when a constant voltage is input;

the input end of the column-level analog front-end circuit 3 is connected to the output end of the bias voltage generation circuit 2 to obtain two paths of same current, and the difference between the two paths of generated current is trans-impedance amplified and is used as voltage output.

Specifically, the bias voltage generating circuit 2 at least includes a first bias voltage generating sub-circuit and a second bias voltage generating sub-circuit, which respectively output the first bias voltage Veb and the second bias voltage V_fid。

More specifically, the first bias voltage generating sub-circuit is connected to the second bias voltage generating sub-circuit, the row stage circuit 1 and the column stage analog front end circuit 3; at least comprises a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, a second NMOS tube MN2, a first operational amplifier OPA1 and a first mirror image blind pixel R_dm0A second mirror image blind pixel R_dm1And a power supply Vsk;

the first mirror image blind pixel R_dm0First end of (1), the second mirror image blind pixel R_dm1Are each connected to the supply source Vsk; the source and the drain of the first PMOS tube MP1 are respectively connected with the first mirror image blind pixel R_dm0The second end of the first NMOS transistor MN1 is connected with the drain electrode of the first NMOS transistor MN 1; the source and the drain of the second PMOS tube MP2 are respectively connected with the second mirror image blind pixel R_dm1The second end of the first transistor is connected with the row level circuit 1; the drain electrode of the second NMOS transistor MN2 is connected with the second bias voltage generating sub-circuit; the source electrode of the first NMOS transistor MN1 and the source electrode of the second NMOS transistor MN2 are grounded; the grid electrode of the first PMOS tube MP1 is connected with the grid electrode of the second PMOS tube MP 2; the grid electrode of the first NMOS transistor MN1 is connected with the grid electrode of the second NMOS transistor MN 2;

the negative input end, the positive input end and the output end of the first operational amplifier OPA1 are respectively connected to the source of the first PMOS transistor MP1, the constant voltage Vb and the gate of the first PMOS transistor MP 1.

Further, in the first bias generation sub-circuit, when the constant voltage is input, the gate voltages of the first PMOS transistor MP1 and the second PMOS transistor MP2 are output to the column-level analog front-end circuit 3 as the first bias voltage Veb.

Further, the first bias voltage generating sub-circuit further includes a decoupling capacitor C1; the first end and the second end of the decoupling capacitor C1 are respectively connected to the power supply Vsk and the gate of the second PMOS transistor MP 2.

More specifically, the second bias voltage generating sub-circuit is connected to the first bias voltage generating sub-circuit, the row stage circuit 1 and the column stage analog front end circuit 3; the power supply at least comprises a first source following structure, a second source following structure, a third NMOS transistor MN3, a second operational amplifier OPA2 and a power supply Vsk;

the gate, the source and the drain of the third NMOS transistor MN3 are respectively connected to the first source follower structure, the first bias generation sub-circuit and the power supply Vsk; the second source follower structure is connected with the first source follower structure; the negative input end, the positive input end and the output end of the second operational amplifier OPA2 are respectively connected with the source of the third NMOS transistor MN3, the row level circuit 1 and the first source follower structure.

Further, the first source follower structure comprises a first current source Ib3 and a third PMOS transistor MP 3; the second source following structure comprises a second current source Ib4 and a fourth PMOS tube MP 4;

the source of the third PMOS transistor MP3 is connected to the first current source Ib3, and the source of the fourth PMOS transistor MP4 is connected to the second current source Ib 4; the source electrode of the third PMOS transistor MP3 is connected with the gate electrode of the third NMOS transistor MN 3; the output end of the second operational amplifier OPA2 is connected to the gate of the third PMOS transistor MP3 and the gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP 4.

Further, the second bias voltage generating sub-circuit obtains the source voltage of the third PMOS transistor MP3 according to the third bias voltage outputted from the row stage circuit 1, copies the source voltage of the third PMOS transistor MP3 to the source of the fourth PMOS transistor MP4 via the first source follower structure and the second source follower structure, and uses the copied voltage as the second bias voltage V_fidAnd outputs the signal to the column-stage analog front-end circuit 3.

Specifically, the column-level analog front-end circuit 3 includes a pixel-level sub-circuit, a power supply Vsk, a blind cell Rd, a fifth PMOS transistor MP0, a fourth NMOS transistor MN0, and an automatic gain calibration sub-circuit; the grid electrode of the fifth PMOS pipe MP0 and the grid electrode of the fourth NMOS pipe MN0 are both connected with the bias voltage generating circuit 2; the gate of the fifth PMOS transistor MP0 and the gate of the fourth NMOS transistor MN0 are respectively used as the input end of the column-level analog front-end circuit 3 to receive the first bias voltage and the second bias voltage.

A first end and a second end of the blind element Rd are respectively connected with the power supply Vsk and a source electrode of the fifth PMOS transistor MP 0; the drain and the source of the fourth NMOS transistor MN0 are respectively connected to the drain of the fifth PMOS transistor MP0 and the pixel level sub-circuit; wherein the pixel level sub-circuit comprises a pixel element Rs.

Further, the automatic gain calibration sub-circuit comprises at least a third operational amplifier OPA0, a transimpedance Rg and a capacitance Cc;

the negative input end of the third operational amplifier OPA0 is connected with the drain electrode of the fifth PMOS pipe MP 0; a first end of the capacitor Cc and a first end of the transimpedance Rg are both connected to a negative input terminal of the third operational amplifier OPA 0; a second end of the capacitor Cc and a second end of the transimpedance Rg are both connected to an output end of the third operational amplifier OPA 0; wherein the third operational amplifier OPA0 outputs Vagc.

Specifically, the column-level analog front-end circuit 3 generates a first current according to the received first bias voltage and the blind cell Rd; the column-level analog front-end circuit 3 generates a second current according to the received second bias voltage and the pixel Rs;

the difference between the two currents is the current difference between the first current and the second current.

More specifically, the first bias voltage generating sub-circuit is connected to the second bias voltage generating sub-circuit, the row stage circuit 1 and the column stage analog front end circuit 3; may comprise a first mirror circuit, a second mirror circuit, a first operational amplifier OPA1, a second operational amplifier OPA2, a first mirror blind pixel R_dm0And a second mirror image blind pixel R_dm1；

The first mirror image circuit is connected with the second mirror image circuit, the second bias voltage generating sub-circuit and the row level circuit 1; the first mirror image blind pixel R_dm0First end of (1), the second mirror image blind pixel R_dm1The first ends of the first and second mirror circuits are connected with the first mirror circuit; the first operational amplifier OPA1 and the second operational amplifier OPA2 are connected to the first mirror circuit and the second mirror circuit, respectively.

Further, the first mirror circuit comprises a first NMOS transistor MN1 and a second NMOS transistor MN2, and the gate of the first NMOS transistor MN1 is connected with the gate of the second NMOS transistor MN 2; a negative input end, a positive input end and an output end of the first operational amplifier OPA1 are respectively connected with the source electrode of the first NMOS transistor MN1, the constant voltage Vb and the gate electrode of the first NMOS transistor MN 1;

the second mirror circuit comprises a third NMOS transistor MN3 and a fourth NMOS transistor MN4, and the gate of the third NMOS transistor MN3 is connected with the gate of the fourth NMOS transistor MN 4; the negative input end, the positive input end and the output end of the second operational amplifier OPA2 are all connected with the source electrode of the third NMOS transistor MN3, the common-mode voltage Vcm and the gate electrode of the third NMOS transistor MN 3; the drain of the third NMOS transistor MN3 and the drain of the fourth NMOS transistor MN4 are respectively connected to the second bias generation sub-circuit and the column stage circuit 1.

Further, in the first bias generation sub-circuit, when the constant voltage is input, the gate voltage of the NMOS transistor included in the first mirror circuit is output to the column-level analog front-end circuit 3 as the first bias voltage Veb.

More specifically, the second bias voltage generating sub-circuit is connected to the first bias voltage generating sub-circuit, the row stage circuit 1 and the column stage analog front end circuit 3; the power supply circuit at least comprises a third mirror image circuit, a third PMOS tube MP3, a fourth PMOS tube MP4, a third operational amplifier OPA3, a fourth operational amplifier OPA4 and a common-mode power supply Vdet;

the third mirror circuit comprises a first PMOS transistor MP1 and a second PMOS transistor MP2, and the grid electrode of the first PMOS transistor MP1 is connected with the grid electrode of the second PMOS transistor MP 2; the source electrode of the first PMOS transistor MP1 and the source electrode of the second PMOS transistor MP2 are both connected to the common mode power supply Vdet, and the drain electrode of the first PMOS transistor MP1 is connected to the first bias voltage generating sub-circuit; the source and the drain of the third PMOS transistor MP3 are respectively connected to the drain of the second PMOS transistor MP2 and the source of the fourth PMOS transistor MP 4; a positive input end, a negative input end and an output end of the third operational amplifier OPA3 are respectively connected to the column circuit 1, the source of the third PMOS transistor MP3 and the gate of the third PMOS transistor MP 3; a positive input end, a negative input end, and an output end of the fourth operational amplifier OPA4 are respectively connected to the common mode voltage Vcm, the source of the fourth PMOS transistor MP4, and the gate of the fourth PMOS transistor MP 4.

Further, the second bias voltage generating sub-circuit obtains a gate voltage of the third PMOS transistor MP3 according to a third bias voltage output by the row stage circuit 1, and outputs the gate voltage as the second bias voltage to the column stage analog front end circuit 3.

Specifically, the column-level analog front-end circuit 3 includes a pixel-level sub-circuit, a common-mode power supply Vdet, a blind pixel Rd, a fifth PMOS transistor MP0, a fourth NMOS transistor MN0, and an automatic gain calibration sub-circuit;

the source and the drain of the fifth PMOS transistor MP0 are respectively connected to the pixel-level sub-circuit and the drain of the fifth NMOS transistor MN 0; the first end of the blind element Rd is connected with the source electrode of the fourth NMOS tube MN0, and the second end of the blind element Rd is grounded; the automatic gain calibration sub-circuit is connected with the drain electrode of the fifth PMOS pipe MP 0;

the gate of the fifth PMOS transistor MP0 and the gate of the fifth NMOS transistor MN0 are both connected to the bias voltage generating circuit 2, and are respectively used as the input terminal of the column-level analog front-end circuit 3 to receive the first bias voltage and the second bias voltage.

Example two

In one embodiment of the present invention, a circuit configuration schematic as shown in FIG. 3 is disclosed; comprises a bias voltage generating circuit 1, a column-level analog front-end circuit 2, a row-level circuit 3 and a pixel-level circuit 4; wherein, the bias voltage generating circuit 1 at least comprises a first bias voltage generating sub-circuit and a second bias voltage generating sub-circuit; the first bias voltage generation sub-circuit and the second bias voltage generation sub-circuit output a first bias voltage and a second bias voltage, respectively;

wherein the first bias voltage generating sub-circuit may include a first PMOS tube MP1, second PMOS tube MP2, first NMOS tube MN1, second NMOS tube MN2, first operational amplifier OPA1, second operational amplifier OPA2, first mirror image blind pixel R_dm0A second mirror image blind pixel R_dm1A decoupling capacitor C1 and a power supply Vsk; it should be noted that the first mirror image blind pixel R_dm0A second mirror image blind pixel R_dm1Has good thermal connection with the circuit substrate, and can be considered as a first mirror image blind element R_dm0A second mirror image blind pixel R_dm1The temperature of the circuit substrate is constant and equal to the temperature of the substrate, namely the temperature change of the circuit substrate can be sensed.

Specifically, the output end of the first operational amplifier OPA1 is connected to the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 respectively, and the gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP 2; the source electrode of the first PMOS pipe MP1 is connected with the negative input end of the first operational amplifier OPA 1; the positive input terminal of the first operational amplifier OPA1 is a constant voltage Vb; the power supply Vsk is respectively connected with the first mirror image blind pixels R_dm0First end, second mirror image blind pixel R_dm1Is connected with the first end of the first PMOS tube MP1, the source electrode of the first PMOS tube MP1 and the first mirror image blind pixel R_dm0Is connected with the second end of the first PMOS transistor MP2, the source electrode of the second PMOS transistor MP2 and the second mirror image blind pixel R_dm1Is connected with the second end of the first end; the drain electrode of the second PMOS transistor MP2 is connected to the row stage circuit 3; the drain electrode of the second PMOS pipe MP2 is also connected with the second bias voltage generating sub-circuit;

in this embodiment, the gate of the first PMOS transistor MP1 is output as the first bias voltage Veb.

In this embodiment, the gate of the first NMOS transistor MN1 is connected to the gate of the second NMOS transistor MN2 to form a current mirror structure;

in this embodiment, a first terminal of the decoupling capacitor C1 is connected to the power source Vsk, and a second terminal thereof is connected to the gate of the second PMOS transistor MP 2.

In the present embodiment, the second bias voltage generating sub-circuit may include a first source follower structure, a second source follower structure, a third NMOS transistor MN3, a second operational amplifier OPA2, and a capacitor C2; the first source follower structure comprises a first current source Ib3 and a third PMOS tube MP 3; the second source follower structure comprises a second current source Ib4 and a fourth PMOS tube MP 4;

specifically, the source of the third PMOS transistor MP3 is connected to the first current source Ib3, and the source of the fourth PMOS transistor MP4 is connected to the second current source Ib 4; the positive input end of the second operational amplifier OPA2 is connected with the drain of the second PMOS transistor in the first bias generation sub-circuit, the negative input end is connected with the source of the third NMOS transistor MN3, and the output end is connected with the gate of the third PMOS transistor MP 3; the grid electrode of the third NMOS transistor MN3 is connected with the source electrode of the third PMOS transistor MP 3; the first end of the capacitor C2 is connected to the gate of the third PMOS transistor MP3, and the second end is grounded.

In this embodiment, a point of the source of the fourth PMOS transistor MP4 is led out as the second bias voltage V_fidAnd (6) outputting.

In this embodiment, the column-level analog front-end circuit 2 may include a power supply Vsk, a blind cell Rd, a fifth PMOS transistor MP0, a fourth NMOS transistor MN0, and an Automatic Gain Calibration (AGC) circuit; the AGC circuit comprises a third operational amplifier OPA0, a trans-resistor Rg and a capacitor Cc.

Specifically, a first end of the blind cell Rd is connected to the power source Vsk, a second end of the blind cell Rd is connected to the source of the fifth PMOS transistor MP0, and a drain of the fifth PMOS transistor MP0 is connected to the drain of the fourth NMOS transistor MN 0.

More specifically, the negative input terminal of the third operational amplifier OPA0 in the AGC circuit is connected to the drain of the third PMOS transistor MP 0; a first end of the capacitor Cc and a first end of the transimpedance Rg are both connected to a negative input end of the third operational amplifier OPA0, and a second end of the capacitor Cc and a second end of the transimpedance Rg are both connected to an output end of the third operational amplifier OPA 0; wherein the third operational amplifier OPA0 outputs Vagc.

In the embodiment, the row-level circuit 3 comprises row-level mirror image elements Rsm and row selection switches RSEL , which are switched row by row; the two ends of the mirror image element Rsm are respectively connected with the second end of the first row selection switch and the first end of the second row selection switch; the first end of the first row selection switch is connected with the drain electrode of the second PMOS tube MP 2; the second end of the second row selection switch can be grounded;

rsm is subjected to a light shielding process to receive a fixed radiation from a light shielding plate having a temperature constantly equal to the substrate temperature.

In the present embodiment, the pixel-level circuit 4 includes a pixel Rs and a row selection switch RSEL; the two ends of the pixel element Rs are respectively connected with the second end of the third row selection switch and the first end of the fourth row selection switch; the first end of the third selection switch is connected with the source electrode of a fourth NMOS transistor MN 0; a second terminal of the fourth selection switch may be connected to ground.

The operation of the circuit in this embodiment will be briefly described.

The source terminal voltage of the first PMOS transistor MP1 is determined by the negative input terminal of the first operational amplifier OPA1 without considering mismatch caused by process error, and the voltage of the negative input terminal is clamped to be approximately equal to the positive input terminal, i.e. the voltage of the negative input terminal is clamped to be high enough for the gain of the OPA1

V_-＝V₊＝V_b……(1)

The voltage across resistor Rdm0 is V_Rdm0＝V_sk-V_b……(2)

The current flowing through Rdm0 is

The gate terminal voltages of the first PMOS transistor MP1 and the second PMOS transistor MP2, i.e., the first bias voltage Veb:

V_eb＝V_GP1,2＝V_b+|V_GSP1|……(4)

the value of Veb is obtained by the formula (4) | V_GSP1And | is the absolute value of the gate-source voltage of the first PMOS transistor MP 1.

In this embodiment, the source terminal voltage of the second PMOS transistor MP2 is the difference between the first bias voltage Veb and the gate-source voltage of the second PMOS transistor MP2, that is, the voltage difference is

V_SP2＝V_eb-|V_GSP2|＝V_b+|V_GSP1|-|V_GSP2|……(5)

In general, the current expression of a PMOS transistor in the saturation region is

Wherein, mu_P、C_oxThe carrier mobility of the PMOS tube and the grid dielectric capacitance in unit area are respectively determined by the processing technology. I V_THAnd | is the threshold voltage of the transistor, and is determined by the processing technology and the source end-body end potential of the transistor.The channel width-to-length ratio of the transistor is determined by design.

Specifically, the current flowing through MP1 is obtained according to the formula (6)

Similarly, for the currents flowing through MP2 and Rdm1, the following relationship holds:

wherein, V_SP2Is the potential of the source end of MP 2;

due to V_SP2＝V_eb-|V_GSP2|＝V_b+|V_GSP1|-|V_GSP2|……(9)

Comparing the above three formulas, it can be found that for MP1 and MP2, the ratio of μ_PC_ox、|V_TH|、V_GIs equal toOver-design such thatAndmatching while making R_dm0And R_dm1Matching, then flowing through MP1, MP2, R_dm0、R_dm1The currents are approximately equal, and the matching effect is achieved.

By the method, the currents with the approximately equal magnitude are obtained on the MP1 branch and the MP2 branch, and are

Similarly, the current in the branch where Rd and MP0 are located is also approximately equal to the current in the branches MP1 and MP2, which is

The derivation of the above equations (5) - (10) gives approximately equal current expressions at MP0, MP1, MP2, i.e., equation (10).

Since the mirror image element Rsm is in the same branch as MP2, the current on Rsm is also approximatelyThe voltage on Rsm is approximately

The positive input of the second operational amplifier OPA2 then has a voltage V_RsmIn the case of sufficient OPA2 gain, the voltage at the negative input is also approximately V due to the clamping effect of the op-amp_Rsm；

Thus, the gate terminal voltage of the NMOS transistor MN3 is

The gate terminal of the PMOS transistor MP3 has a voltage of

The gate terminal voltage of the fourth PMOS transistor MP4 is the same as the gate terminal voltage of MP3, and the source terminal voltage, i.e., the second bias voltage Vfid, is

In this embodiment, the first bias voltage Veb is used as a gate voltage of a PMOS transistor for biasing the blind cell in the column-level readout circuit, and biases the blind cell Rd, so that the blind cell Rd generates the blind cell current Id. In the case of matching Rdm0, Rdm1, MP0, MP1, MP2 sizes, the values of the currents Id generated by the above-described methods are all approximated to values

It should be noted that Rdm0 is a mirror image blind pixel, which has a good thermal connection with the circuit substrate, and it can be considered that Rdm0 temperature is always equal to the substrate temperature, so the Id value generated in this way follows the substrate temperature change, i.e. the change of the circuit substrate temperature can be sensed.

The expression (14) gives an expression of a second bias voltage Vfid, the second bias voltage Vfid Is used as a gate voltage of a fourth NMOS transistor MN0 of the pixel for biasing the pixel by the column-level analog front-end circuit 2, and the pixel Rs Is biased to generate a pixel current Is on the pixel Rs, wherein the expression of Is as follows

Substituting the formula (14) into the formula (15) to obtain

Wherein, | V_GSP3|、|V_GSP4I is the absolute value of the voltage difference between the gate sources of the MP3 and the MP4, the MP3 and the MP4 respectively form a source following structure with the first current source Ib3 and the second current source Ib4, and V can be enabled by matching the sizes of the MP3 and the MP4 and the current sizes of the first current source Ib3 and the second current source Ib4_GSP3I and V_GSP4If | is equal, then equation (16) becomes

In the above formula (17), Rsm is used as thermal insulation between the row-level mirror image element and the substrate and is subjected to light shielding treatment by fixed radiation from a light shielding sheet having a temperature constantly equal to the temperature of the substrate; rs serves as a pixel, is thermally insulated from the substrate, and receives external radiation. Both Rsm and Rs have a self-heating effect due to thermal insulation between them and the substrate. When selected, both Rsm and Rs change resistance due to joule heating, but the changes are synchronized and thus cancelled in Is.

In the present embodiment, in the column-level readout circuit, the current Idiff to be read out Is the difference between the pixel current Is and the blind pixel current Id. When the picture element Rs receives a fixed radiation (fixed signal input), the ideal output of the readout circuit should be a fixed value, i.e. neither substrate temperature variations nor self-heating effects should affect the equilibrium state of the circuit.

In the conventional structure, Vfid, Veb generally cannot follow the self-heating effect, substrate temperature change in real time; if the substrate temperature changes at the moment, the value of the blind element Rd changes along with the substrate temperature, the blind element current Id also changes along with the substrate temperature, but the Vfrid cannot sense the substrate temperature, so that the Is cannot follow the substrate temperature, and at the moment, even if the circuit Is stable in a certain fixed output state, the value of Idiff cannot be fixed actually; in addition, it should be noted that, since the temperature of the blind element Rd is constantly equal to the temperature of the substrate, the self-heating effect thereof is negligible, and Rs has the self-heating effect, the imbalance between the two due to self-heating will also cause the output of the circuit to deviate from the original stable point; that is, in the conventional structure, even if the external input is a fixed value, the output value thereof cannot be stabilized but drifts with the self-heating effect and the substrate temperature change, which certainly affects the readout quality.

In the disclosed embodiment of the present invention, when Rs and Rsm are subjected to the same fixed radiation, Rsm and Rs have the same resistance, the same temperature coefficient, and the same self-heating effect, so that Rs and Rsm cancel each other, the above equation (17) can be expressed as:

it should be noted that the formula (18) is the current of the picture element under the condition that Rs is subjected to fixed external radiation, and is represented by I_S0And (4) showing.

Wherein (18) is represented by the formula V_GSN3The voltage difference of the gate and the source of MN3 is determined by the size, the process parameters and the current flowing through the voltage difference, the current on MN3 is copied from a current mirror structure consisting of MN1 and MN2 and is approximately equal to the current on MN1, namely the voltage difference is determined by the size, the process parameters and the current flowing through the voltage differenceV_GSN0Is the voltage difference between the gate and the source of MN0, which is determined by its size, process parameters and the current flowing through it, the current on MN0 is I_S0. From the current expressions on MN0 and MN3, V matches the size of MN0 and MN3_GSN3And V_GSN0Approximately equal, the current flowing through the two MOS tubes are approximately equal, both areThen (18) becomes

In addition, I_S0Is the pixel current value when the pixel Rs is subjected to fixed external radiation; (19) formula I shows_S0Is not influenced by self-heating effect and can pass through the first mirror image blind pixel R_dm0To follow variations in substrate temperature. According to the above analysis, the blind pixel current Id isThe differential current value Idiff read at this time is:

I_diff＝I_d-I_s0＝0……(20)

it can be obtained that the output of the readout circuit can be stabilized at 0 when Rs and Rsm are subjected to the same fixed radiation, and is not affected by the substrate temperature and self-heating effect.

In the above scheme, the Rs generates the first bias voltage Veb and the second bias voltage V when receiving the fixed external radiation_fidThe stable output point which is not influenced by the substrate temperature and the self-heating effect can be output by the reading circuit; the operation of the circuit when the picture element Rs is subjected to varying external radiation is explained below.

When the pixel element Rs is subjected to variable external radiation, the current flowing through the blind element Rd is stillAnd the current flowing through the pixel Rs changes, and a differential current Idiff is generated between the two.

When Rs is subjected to varying external radiation, a change in resistance, referred to as R, occurs due to a change in temperature_S+ΔR_SBelow, theAnalysis I_sVariations of (2)

The branch where MP0 is located satisfies the following formula

V_GSN0＝V_fid-I_sR_S……(22)

Substituting formula (22) into formula (21), there are

Obtaining the derivative of the two ends of the formula (23) on Rs, wherein the other parameters except Is and Rs are not related to Rs to obtain

Obtained by the formula (24)

Wherein,the transconductance value of the MOS tube is shown.

(25) In the formula, g can be adjusted through reasonable design_mR_s＞＞1，1+g_mR_s≈g_mR_sThen, equation (25) is changed to

By combining the expressions (26) and (19), it can be obtained that the current value of Rs when the circuit 0 outputs isI_S0When Rs changes by Δ R_sWhen the current value on Rs is

I_s＝I_S0+ΔI_s……(27)

At this time, the differential sense current I_diffIs composed of

In the above formula, V_sk、V_bAre all quantities independent of substrate temperature, self-heating effects;is the ratio of the value of the resistance change of the pixel Rs to the initial value, the self-heating effect is cancelled. And the first mirror image blind pixel R_dm0Is a quantity related to the substrate temperature, hence I_diffIs to follow the substrate temperature change independent of the self-heating effect.

In this embodiment, in I_diffThe latter stage of (1) is an AGC circuit composed of a third operational amplifier OPA0, a trans-resistance Rg and a capacitor Cc, wherein the trans-resistance R_g＝N*R_dm0N is the magnification factor, R_gThe high-temperature-resistant high-temperature; then I_diffAfter passing through AGC circuit, it is converted into voltage value and output as

V_agc＝V_CM-I_diff*R_g……(30)

Wherein R is_g、R_dm0At the same time, following the temperature variation of the substrate, the results after mutual cancellation are onlyThe rest of the magnification factor N is

(32) V obtained in the formula_agcThe change in the pixel resistance can be read out and is a quantity independent of both the substrate temperature and the self-heating effect.

The conventional second bias voltage generating circuit directly generates Vfid through the output of the operational amplifier and directly drives the array load as shown in fig. 4, in which the load of a single column is given by the following equation

Wherein s ═ j ω, C_gsIs the gate-source parasitic capacitance of MOS transistor, g_mIs the transconductance of the MOS tube. The loading of the array makes the stability of the feedback loop difficult to guarantee.

One conventional solution is to add a single-stage unity-gain op-amp between the Vfid generation loop and the column-level load, isolating the feedback loop from the column-level load, as shown in fig. 5. This has the disadvantage that the operational amplifier introduces a large amount of noise and the output of the operational amplifier is connected directly to the gate of the MOS transistor of the column readout circuit, and the noise is coupled directly to the readout I_diffAnd the middle part influences the reading effect. Compared with the traditional solution, the source voltage of the third PMOS transistor MP3 in the scheme is the generated second bias voltage Vfid, but the column-level analog front-end circuit 2 is not directly driven by the voltage at this point, but a point is taken out from the feedback loop, and the voltage at this point is copied to the source of the fourth PMOS transistor MP4 by adopting a source following structure, so that the point is not in the feedback loop, the introduced noise is small, and the column-level analog front-end circuit 2 is driven by the point, which has no influence on the loop stability;

it should be noted that, in this embodiment, the row-level mirror image element Rsm is controlled by the row selection switch RSEL, as well as the image element Rs; when the row is selected to the ith row, the row-level mirror image element Rsm and the image element Rs are simultaneously gated, both have a self-heating effect, the generation of the second bias voltage Vfid is based on the voltage across the Rsm, the voltage across the Rsm is based on the current flowing through the Rsm, the current is generated by Rdm0, the substrate temperature can be sensed, and the final result is that the second bias voltage Vfid capable of sensing the substrate temperature and the self-heating effect is generated. The resulting effect is that the circuit can be self-balancing, independent of substrate temperature.

It should be further noted that the first bias voltage Veb is generated based on a negative feedback loop of the OPA1 and MP1, which is a low-speed node and does not need a large bandwidth, so that the large capacitor C1 is used to limit the bandwidth, thereby ensuring that the loop has good loop stability; by connecting the decoupling capacitor C1 to the power supply Vsk, low-pass filtering of the bias noise can be achieved while enhancing the stability of the Veb generation loop; meanwhile, the decoupling capacitor C1 may filter noise of the first bias voltage Veb to reduce bias noise;

it should be further noted that, in the column-level transimpedance gain amplification circuit, the two ends of the gain blind cell Rg are connected in parallel to the adjustable capacitor Cc. Under different substrate temperatures, the phase margin of the circuit can be adjusted, and the required establishment stabilization time of Vagc during line-to-line switching is shortened, so that the integration time of the later stage is prolonged, and the signal-to-noise ratio is greatly improved.

EXAMPLE III

In another embodiment of the present invention, a circuit configuration schematic as shown in fig. 6 is disclosed; comprises a bias voltage generating circuit 1, a column-level analog front-end circuit 2, a row-level circuit 3 and a pixel-level circuit 4; the bias voltage generating circuit 1 at least comprises a first bias voltage generating sub-circuit and a second bias voltage generating sub-circuit, wherein the first bias voltage generating sub-circuit and the second bias voltage generating sub-circuit respectively output a first bias voltage and a second bias voltage;

wherein the first bias voltage generating sub-circuit may include a first bias voltage generating sub-circuitAn NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first operational amplifier OPA1, a second operational amplifier OPA2, a first mirror image blind pixel R_dm0And a second mirror image blind pixel R_dm1(ii) a It should be noted that the first mirror image blind pixel R_dm0A second mirror image blind pixel R_dm1Has good thermal connection with the circuit substrate, and can be considered as a first mirror image blind element R_dm0A second mirror image blind pixel R_dm1The temperature of the circuit substrate is constant and equal to the temperature of the substrate, namely the temperature change of the circuit substrate can be sensed.

Specifically, the output end of the first operational amplifier OPA1 is connected to the gates of the first NMOS transistor MN1 and the second NMOS transistor MN2, respectively, and the gate of the first NMOS transistor MN1 is connected to the gate of the second NMOS transistor MN 2; the source electrode of the first NMOS transistor MN1 is connected with the negative input end of the first operational amplifier OPA 1; first mirror image blind pixel R_dm0First end, second mirror image blind pixel R_dm1Respectively connected with the source electrode of the first NMOS transistor MN1 and the source electrode of the second NMOS transistor MN2, and a first mirror image blind pixel R_dm0Second end, second mirror image blind pixel R_dm1The second ends of the first and second terminals are grounded; the output end of the second operational amplifier OPA2 is respectively connected with the gate of the third NMOS transistor MN3 and the gate of the fourth NMOS transistor MN4, and the gate of the third NMOS transistor MN3 is connected with the gate of the fourth NMOS transistor MN 4; the negative input end of the second operational amplifier OPA2 is connected with the source electrode of the third NMOS tube MN 3; the drain and the source of the third NMOS transistor MN3 are connected to the drain of the first PMOS transistor MP1 and the drain of the first NMOS transistor MN1, respectively; the source electrode of the fourth NMOS transistor MN4 is connected to the drain electrode of the second NMOS transistor MN2, and the drain electrode of the fourth NMOS transistor MN4 is connected to the pixel level circuit 4 and also connected to the second bias voltage generation sub-circuit;

in this embodiment, the gate of the first NMOS transistor MN1 is output as the first bias voltage Veb.

The grid electrode of the first NMOS tube MN1 is connected with the grid electrode of the second NMOS tube MN2 to form a current mirror structure; the grid electrode of the third NMOS tube MN3 is connected with the grid electrode of the fourth NMOS tube MN4 to form a current mirror structure;

in this embodiment, the second bias voltage generating sub-circuit may include a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a third operational amplifier OPA3, a fourth operational amplifier OPA4, and a common mode power supply Vdet;

specifically, the drain of the first PMOS transistor MP1 is connected to the drain of the third NMOS transistor MN3, and the source of the first PMOS transistor MP1 is connected to the common mode power supply Vdet; the source electrode and the drain electrode of the second PMOS tube MP2 are respectively connected with the common-mode power supply Vdet and the source electrode of the third PMOS tube MP 3; the drain electrode of the third PMOS tube MP3 is connected with the source electrode of the fourth PMOS tube MP 4; the drain of the fourth PMOS transistor MP4 is grounded; the positive input end of the third operational amplifier OPA3 is connected with the drain of the fourth NMOS transistor MN4 in the first bias generation sub-circuit, and the negative input end is connected with the source of the third PMOS transistor MP 3; the negative input end of the fourth operational amplifier OPA4 is connected with the source electrode of the fourth PMOS tube MP 4;

in this embodiment, the gate of the third PMOS transistor MP3 is used as the second bias voltage V_fidAnd (6) outputting.

The gate of the second PMOS transistor MP2 of the second bias generation sub-circuit is connected to the gate of the first PMOS transistor MP1 of the first bias generation sub-circuit, thereby forming a current mirror structure;

in the embodiment, the column-level analog front-end circuit 2 includes a blind cell Rd, a fifth PMOS transistor MP0, a fifth NMOS transistor MN0, and an Automatic Gain Calibration (AGC) circuit; the AGC circuit includes a fifth operational amplifier OPA0, a transimpedance Rg, and a capacitor Cc.

Specifically, the source of the fifth PMOS transistor MP0 is connected to the pixel stage circuit 4, the drain is connected to the drain of the fifth NMOS transistor MN0, and the gate of the fifth NMOS transistor MN0 inputs the second bias voltage V_fid(ii) a A first bias voltage Veb is input to the gate of the fifth NMOS tube MN0, the source of the fifth NMOS tube MN0 is connected with the first end of the blind cell Rd, and the second end of the blind cell Rd is grounded;

more specifically, the negative input terminal of the fifth operational amplifier OPA0 in the AGC circuit is connected to the drain of the fifth PMOS transistor MP 0; a first end of the capacitor Cc and a first end of the transimpedance Rg are both connected to the negative input end of the fifth operational amplifier OPA0, and a second end of the capacitor Cc and a second end of the transimpedance Rg are both connected to the output end of the fifth operational amplifier OPA 0; wherein the fifth operational amplifier OPA0 outputs Vagc.

In this embodiment, the row-level circuit 3 includes row-level mirror image elements Rsm and a row selection switch RSEL that are switched row by row; the two ends of the mirror image element Rsm are respectively connected with the second end of the first row selection switch and the first end of the second row selection switch; the second end of the second row selection switch is connected with the drain electrode of a fourth NMOS transistor MN 4; the first end of the first row selection switch is connected with a common-mode power supply Vdet;

In the present embodiment, the pixel-level circuit 4 includes a pixel Rs and a row selection switch RSEL; the two ends of the pixel element Rs are respectively connected with the second end of the third row selection switch and the first end of the fourth row selection switch; the first end of the third row selection switch is connected with a common-mode power supply Vdet; the second end of the fourth row selection switch is connected with the source electrode of the fifth PMOS transistor MP 0.

It should be noted that, in this embodiment, the blind pixel Rd and the first mirror image blind pixel Rdm are subjected to constant voltage bias, the pixel Rs and the mirror image Rsm are subjected to constant current bias, Rs and Rsm are placed in a high voltage domain, and Rd and Rdm are placed in a low voltage domain, so that the noise suppression capability of the common mode power supply Vdet is effectively improved, and a higher voltage Vb is not required.

The operation of the circuit in this embodiment will be briefly described.

First, a current is generated at Rdm0 based on the first operational amplifiers OPA1 and Vb without considering process mismatch and with sufficient OPA1 gain

Then, based on the first mirror image blind pixel R_dm0And a secondMirror image blind pixel R_dm1The matching of the first NMOS transistor MN1 and the second NMOS transistor MN2 obtains approximately the same current as Rdm0 at Rdm1 and the pixel Rd, and the current can follow the temperature change of the substrate:

based on the current, a voltage capable of following the temperature change of the substrate and the induction self-heating effect is generated on the row-level image element Rsm

Voltage V_RsmAs the positive input of the third operational amplifier OPA3, when the OPA3 gain is sufficient, the voltage at its negative input is approximately:

namely, the source terminal voltage of the third PMOS transistor MP3 is alsoThe gate terminal voltage of MP3 isAnd the voltage at the point is used as a second bias voltage Vfrid to bias the MP 0; in a Vfrid generation loop, branch currents of a PMOS tube MP3 and a PMOS tube MP4 are obtained by copying current images of Rdm0 branches, constant current bias of MP3 is guaranteed, and the current is proportional to current flowing through an Rsm branch; the mirror matching degree is high, and parasitic capacitance influencing the stability of a loop is prevented from being introduced due to the increase of the use of row-level shading pixels; the voltage and current on the pixel element Rs are respectively

In the case of the same fixed radiation being received by the picture element Rs and the mirror image element Rsm, the resistance values of Rsm and Rs are matched and the self-heating effects cancel each other out, i.e.

Under the condition that the sizes of the third NMOS tube MN3 and the fifth NMOS tube MN0 are matched, | V_GSP3|＝|V_GSP0I, have

As can be seen from equations (2) and (8), when Rs and Rsm receive the same fixed radiation, the circuit is in a fixed input state, that is:

I_diff＝I_s0-I_d＝0……(9)

from the equation (9), when the circuit is in the fixed input, the output is automatically stabilized regardless of the substrate temperature and the self-heating effect.

When the resistance value of Rs changes due to external radiation, the current flowing through MP0 is satisfied

The two sides of the formula (10) are derived to obtain

Wherein,the transconductance value of the MOS tube is shown.

In the formula (11), g can be adjusted by rational design_mR_s＞＞1，1+g_mR_s≈g_mR_sThen the formula (11) is changed to

Thus, the

After passing through AGC circuit, the output is

(14) In the formula,self-heating effect is counteracted, and obtained V_agcThe change in the pixel resistance can be read out and is a quantity independent of both the substrate temperature and the self-heating effect.

It should be noted that, in the technical solution disclosed in this embodiment, a constant current is generated after the first mirror blind cell Rdm0 is biased by using a constant voltage Vb, the same constant current is generated on Rdm1 and Rd by using device parameter matching, and then the voltage Vrsm is obtained on Rsm by using the constant current. Moreover, the Rd, the Rdm0 and the R Rdm1 are biased in a low-voltage domain and are generated based on Vb and a ground plane, and the noise introduced is greatly reduced because the noise of the ground plane is smaller; meanwhile, the constant voltage Vb does not need too high voltage, a boosting circuit is not needed to obtain a high Vb, and the possibility of introducing noise from the boosting circuit is avoided; in addition, because the circuit adopts a mirror image structure, noise on Vdet is a common modulus for Rs and Rsm, and the structure has good rejection capability for common mode noise on Vdet.

It should be further noted that, in the technical solution disclosed in this embodiment, the second operational amplifier OPA2 and the fourth operational amplifier OPA4 are used, which are used to clamp the drain potentials of the first NMOS transistor MN1 and the third PMOS transistor MP3 to the common-mode voltage Vcm, and the drains of the fifth NMOS transistor MN0 and the fifth PMOS transistor MP0 are also the common-mode voltage Vcm due to the clamping effect of the fifth operational amplifier OPA0 in the column-level analog front-end circuit 2, thereby ensuring that better matching degrees are provided between the first NMOS transistor MN1 and the fifth NMOS transistor MN0, and between the third PMOS transistor MP3 and the fifth PMOS transistor MP 0.

It should be further noted that the first mirror blind pixel Rdm0 is biased by Vb at a constant voltage to generate a constant current, and the constant current passes through the first PMOS transistor MP1, and a current mirror structure formed by MP1 and MP2 is copied to the MP3 and MP4 branches, so that better loop stability can be achieved.

In this embodiment, the current of the second mirror blind pixel Rdm1 branch is generated by the first bias voltage Veb to control the second NMOS transistor MN2 to generate, and as with the first mirror blind pixel Rdm0 branch, the generated constant current biases the mirror pixel Rsm to generate a bias voltage at the lower end of the mirror pixel Rsm, and now this bias voltage needs to be "copied" to the lower end of the pixel Rs to perform the same bias on the pixel, which is specifically done in this embodiment: the lower end of the mirror image element Rsm is connected to the positive input end of a third operational amplifier OPA3, the voltage of the negative input end of the third operational amplifier OPA3 is the same as that of the lower end of the mirror image element Rsm due to clamping, and the second bias voltage Vfrid is obtained by subtracting | Vgsp3| from the voltage value after MP 3; the voltage value at the lower end of the pixel Rs is Vfrid + | Vgsp0|, under the condition that MP3 and MP0 are matched, | Vgsp3| and | Vgsp0| can be mutually offset, and the voltage at the lower end of the Rs is the voltage at the lower end of the mirror image pixel Rsm and is constant current bias; for the second bias voltage Vfod loop, a current mirror structure is adopted to copy a constant current generated by a blind element Rd, and the constant current is not directly connected to the lower end of a mirror image element Rsm to generate the second bias voltage Vfod, because the mirror image element Rsm shields light, a parasitic capacitor influencing stability may be introduced; by adopting the method disclosed in the embodiment, the mirror image matching degree is high, and parasitic capacitance influencing the stability of the loop circuit is prevented from being introduced due to the fact that row-level shading pixels are additionally used.

In the embodiment, the design of the voltage domain reduces the introduced power supply noise and avoids the introduction of new noise due to the need of a high bias voltage Vb; in the loop generating the second bias voltage Vpid, the structure of the scheme is adopted, so that good loop stability can be realized.

It should be emphasized that, in the current mirror structures mentioned in the second and third embodiments, the default analysis is that the current mirror structure circuit has only one column, but actually, multiple columns may be connected in parallel in the current mirror structure, for example, in the third embodiment, the mirror image element Rsm, the fourth NMOS transistor MN4, and the second NMOS transistor MN2 may be connected in parallel by multiple columns, and the branches of the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 may be connected in parallel by multiple columns; in the second embodiment, the MP2 branches can also be connected in parallel in multiple rows; the matching degree of the device can be further improved, and the noise of the mirror circuit can be reduced, but the cost is increased. How to choose between performance and power consumption depends on the designer's needs, but is within the scope of this scheme statement.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A non-TEC uncooled infrared focal plane array readout circuit is characterized by comprising a bias voltage generation circuit, a column-level analog front-end circuit and a row-level circuit; wherein,

the row-level circuit comprises a row-level mirror image element (rssm) and a row selection switch (RSEL)) (ii) a When the row level circuit is switched by the row selection switch (RSEL)) When controlled to be gated, a third bias voltage (V) is output to the bias voltage generation circuit_Rsm)；

The input end of the bias voltage generating circuit is connected with the output end of the row level circuit; according to the inputConstant pressure (V) of inlet_b) And the third bias voltage (V)_Rsm) Generating and outputting a first bias voltage (Veb) and a second bias voltage (V)_fid)；

The column-level analog front-end circuit comprises blind pixels (Rd); the input end of the column-level analog front-end circuit is connected with the output end of the bias voltage generating circuit and is based on the first bias voltage (Veb) and the second bias voltage (V)_fid) Two currents are obtained, and the difference (I) between the two generated currents is calculated_diff) Is trans-resistance amplified and used as output voltage (V)_agc) And (6) outputting.

2. The circuit of claim 1, wherein the bias voltage generating circuit comprises at least a first bias voltage generating sub-circuit and a second bias voltage generating sub-circuit, respectively outputting the first bias voltage (Veb) and the second bias voltage (vb)_fid)。

3. A circuit according to claim 2, characterized in that when said constant voltage (V) is applied_b) When the voltage is input, the grid voltage of a PMOS tube in the first bias voltage generation sub-circuit is taken as the first bias voltage (Veb) and is output to the column-level analog front-end circuit;

the second bias voltage generating sub-circuit generates a second bias voltage according to the third bias voltage (V)_Rsm) Generating a second bias voltage (V)_fid) The second bias voltage (V) is applied by a source follower structure circuit in the second bias voltage generating sub-circuit_fid) Copied and output to the column-level analog front-end circuit.

4. The circuit of claim 2, wherein the first bias voltage generating sub-circuit is coupled to the second bias voltage generating sub-circuit, the row stage circuit, and the column stage analog front end circuit; at least comprises a first mirror image circuit, a second mirror image circuit, a first operational amplifier (OPA1), a first mirror image blind pixel (R)_dm0) A second mirror image blind pixel (R)_dm1) And a power supply (Vsk);

the first mirrorAn image circuit is connected with the second image circuit, the first operational amplifier (OPA1) and the first image blind pixel (R)_dm0) A second mirror image blind pixel (R)_dm1) And (4) connecting.

5. The circuit of claim 4, wherein the first mirror circuit comprises a first PMOS transistor (MP1) and a second PMOS transistor (MP2), and a gate of the first PMOS transistor (MP1) is connected to a gate of the second PMOS transistor (MP 2); the second mirror image circuit comprises a first NMOS transistor (MN1) and a second NMOS transistor (MN2), wherein the gate of the first NMOS transistor (MN1) is connected with the gate of the second NMOS transistor (MN 2);

the first mirror image blind pixel (R)_dm0) The first end of (1), the second mirror image blind pixel (R)_dm1) Are each connected to the power supply (Vsk); the source and the drain of the first PMOS tube (MP1) are respectively connected with the first mirror image blind pixel R_dm0The drain electrode of the first NMOS tube (MN 1); the source and the drain of the second PMOS tube (MP2) are respectively connected with the second mirror image blind pixel (R)_dm1) The second terminal of (a) is connected with the row level circuit; the drain electrode of the second NMOS tube (MN2) is connected with the second bias voltage generation sub-circuit; the source electrode of the first NMOS transistor (MN1) and the source electrode of the second NMOS transistor (MN2) are grounded;

6. The circuit of claim 5, wherein in the first bias generation sub-circuit, when the constant voltage is input, a gate voltage of a first PMOS transistor (MP1) and a gate voltage of a second PMOS transistor (MP2) in the first mirror circuit are output to the column-level analog front-end circuit as the first bias voltage (Veb).

7. The circuit of claim 4, wherein the first bias voltage generating sub-circuit further comprises a decoupling capacitor (C1); the first end and the second end of the decoupling capacitor (C1) are respectively connected with the power supply (Vsk) and the first mirror image circuit.

8. The circuit of claim 2, wherein the second bias voltage generating sub-circuit is coupled to the first bias voltage generating sub-circuit, the row stage circuit, and the column stage analog front end circuit; at least comprises a first source following structure circuit, a second source following structure circuit, a third NMOS tube (MN3) and a second operational amplifier (OPA 2);

the grid electrode and the source electrode of the third NMOS tube (MN3) are respectively connected with the first source follower structure circuit and the first bias voltage generating sub-circuit; the second source following structure circuit is connected with the first source following structure circuit; the negative input end, the positive input end and the output end of the second operational amplifier (OPA2) are respectively connected with the source electrode of the third NMOS tube (MN3), the row-level circuit and the first source following structure circuit.

9. The circuit of claim 8, wherein the first source follower configuration circuit comprises a first current source (Ib3) and a third PMOS transistor (MP 3); the second source follower structure circuit comprises a second current source (Ib4) and a fourth PMOS tube (MP 4);

the source of the third PMOS transistor (MP3) is connected to the first current source (Ib3), and the source of the fourth PMOS transistor (MP4) is connected to the second current source (Ib 4); the source electrode of the third PMOS pipe (MP3) is connected with the gate electrode of the third NMOS pipe (MN 3); the output end of the second operational amplifier (OPA2) is connected with the grid electrode of the third PMOS tube (MP3) and the grid electrode of the third PMOS tube (MP3) is connected with the grid electrode of the fourth PMOS tube (MP 4).

10. The circuit of claim 9, wherein the second bias generation sub-circuit generates the third bias voltage (V) according to the output of the row stage circuit_Rsm) Obtaining a source voltage of the third PMOS transistor (MP3) through the first sourceThe follower structure circuit and the second source follower structure circuit copy the source voltage of the third PMOS transistor (MP3) to the source of the fourth PMOS transistor (MP4) as the second bias voltage (V)_fid) And the output is output to the column-level analog front-end circuit.

11. The circuit of claim 2, wherein the column-level analog front-end circuit comprises at least a pixel-level sub-circuit, a power supply (Vsk), a blind cell (Rd), a fifth PMOS transistor (MP0), a fourth NMOS transistor (MN0), and an automatic gain calibration sub-circuit; the grid electrode of the fifth PMOS tube (MP0) and the grid electrode of the fourth NMOS tube (MN0) are both connected with the bias voltage generating circuit and respectively used as the input end of the column-level analog front-end circuit to receive the first bias voltage (Veb) and the second bias voltage (V0)_fid)；

The first end and the second end of the blind element (Rd) are respectively connected with the power supply (Vsk) and the source electrode of the fifth PMOS tube (MP 0); the drain and the source of the fourth NMOS transistor (MN0) are respectively connected with the drain of the fifth PMOS transistor (MP0) and the pixel-level sub-circuit; wherein the pixel level sub-circuit comprises a picture element (Rs).

12. The circuit of claim 11, wherein the automatic gain calibration subcircuit comprises at least a third operational amplifier (OPA0), a transimpedance (Rg) and a capacitance (Cc);

the negative input end of the third operational amplifier (OPA0) is connected with the drain electrode of the fifth PMOS tube (MP 0); a first end of the capacitor (Cc) and a first end of the transimpedance (Rg) are both connected to a negative input of the third operational amplifier (OPA 0); a second terminal of the capacitor (Cc) and a second terminal of the transimpedance (Rg) are both connected to an output terminal of the third operational amplifier (OPA 0); wherein the third operational amplifier (OPA0) outputs an output voltage (V)_agc)。

13. The circuit of claim 2, wherein in the first bias generating sub-circuit, when the constant voltage (V) is applied_b) When the voltage is input, the grid voltage of an NMOS tube contained in the first mirror image circuit is used as the first bias voltage (Veb) and is output to the column-level analog front-end circuit;

the second bias voltage generation sub-circuit generates a third bias voltage (V) according to the output of the row stage circuit_Rsm) Obtaining the gate voltage of a third PMOS transistor (MP3) as the second bias voltage (V)_fid) And the output is output to the column-level analog front-end circuit.

14. The circuit of claim 2, wherein the first bias voltage generating sub-circuit is coupled to the second bias voltage generating sub-circuit, the row stage circuit, and the column stage analog front end circuit; at least comprises a first mirror image circuit, a second mirror image circuit, a first operational amplifier (OPA1), a second operational amplifier (OPA2), a first mirror image blind pixel (R)_dm0) And a second mirror image blind pixel (R)_dm1)；

The first mirror image circuit is connected with the second mirror image circuit, the second bias voltage generating sub-circuit and the row level circuit; the first mirror image blind pixel (R)_dm0) The first end of (1), the second mirror image blind pixel (R)_dm1) The first ends of the first and second mirror circuits are connected with the first mirror circuit; the first operational amplifier (OPA1) and the second operational amplifier (OPA2) are respectively connected with the first mirror circuit and the second mirror circuit.

15. The circuit of claim 14, wherein the first mirror circuit comprises a first NMOS transistor (MN1) and a second NMOS transistor (MN2) and the gate of the first NMOS transistor (MN1) is connected to the gate of the second NMOS transistor (MN 2); the negative input end, the positive input end and the output end of the first operational amplifier (OPA1) are respectively connected with the source electrode and the constant voltage (V) of the first NMOS tube (MN1)_b) The grid electrode of the first NMOS tube (MN 1);

the second mirror image circuit comprises a third NMOS transistor (MN3) and a fourth NMOS transistor (MN4), and the grid electrode of the third NMOS transistor (MN3) is connected with the grid electrode of the fourth NMOS transistor (MN 4); the negative input end, the positive input end and the output end of the second operational amplifier (OPA2) are respectively connected with the source electrode of the third NMOS transistor (MN3), the common-mode voltage Vcm and the gate electrode of the third NMOS transistor (MN 3); the drain electrode of the third NMOS tube (MN3) and the drain electrode of the fourth NMOS tube (MN4) are respectively connected with the second bias voltage generating sub-circuit and the row stage circuit.

16. The circuit of claim 15, wherein in the first bias generating sub-circuit, when the constant voltage (V) is applied_b) When the first mirror image circuit is input, the first mirror image circuit comprises a first NMOS tube (MN1) and a second NMOS tube (MN2) grid voltage as the first bias voltage (Veb), and the first bias voltage is output to the column-level analog front-end circuit.

17. The circuit of claim 2, wherein the second bias voltage generating sub-circuit is coupled to the first bias voltage generating sub-circuit, the row stage circuit, and the column stage analog front end circuit; the power supply circuit at least comprises a third mirror image circuit, a third PMOS tube (MP3), a fourth PMOS tube (MP4), a third operational amplifier (OPA3), a fourth operational amplifier (OPA4) and a common-mode power supply (Vdet);

the third mirror circuit comprises a first PMOS tube (MP1) and a second PMOS tube (MP2), and the grid electrode of the first PMOS tube (MP1) is connected with the grid electrode of the second PMOS tube (MP 2); the source electrode of the first PMOS tube (MP1) and the source electrode of the second PMOS tube (MP2) are both connected with the common-mode power supply (Vdet), and the drain electrode of the first PMOS tube (MP1) is connected with the first bias voltage generation sub-circuit; the source electrode and the drain electrode of the third PMOS tube (MP3) are respectively connected with the drain electrode of the second PMOS tube (MP2) and the source electrode of the fourth PMOS tube (MP 4); a positive input end, a negative input end and an output end of the third operational amplifier (OPA3) are respectively connected with the row-level circuit, a source electrode of the third PMOS tube (MP3) and a grid electrode of the third PMOS tube (MP 3); the positive input end, the negative input end and the output end of the fourth operational amplifier (OPA4) are respectively connected with a common mode voltage Vcm, the source electrode of the fourth PMOS transistor (MP4) and the gate electrode of the fourth PMOS transistor (MP 4).

18. The circuit of claim 17, wherein the second bias voltage generating sub-circuit generates the third bias voltage (V) according to the output of the row stage circuit_Rsm) Obtaining the gate voltage of the third PMOS transistor (MP3) as the second bias voltage (V)_fid) And the output is output to the column-level analog front-end circuit.

19. The circuit of claim 1, wherein the column-level analog front-end circuit comprises a pixel-level sub-circuit, a common-mode power supply (Vdet), a blind cell (Rd), a fifth PMOS transistor (MP0), a fourth NMOS transistor (MN0), and an automatic gain calibration sub-circuit;

the source electrode and the drain electrode of the fifth PMOS tube (MP0) are respectively connected with the pixel-level sub-circuit and the drain electrode of the fourth NMOS tube (MN 0); the first end of the blind element (Rd) is connected with the source electrode of the fifth NMOS tube (MN0), and the second end of the blind element (Rd) is grounded; the automatic gain calibration sub-circuit is connected with the drain electrode of the fifth PMOS tube (MP 0);

the grid electrode of the fifth PMOS tube (MP0) and the grid electrode of the fifth NMOS tube (MN0) are both connected with the bias voltage generating circuit and respectively used as the input end of the column-level analog front-end circuit to receive the first bias voltage (Veb) and the second bias voltage (V0)_fid)。

20. The circuit of claim 1, wherein the column-level analog front-end circuit generates a first current according to the received first bias voltage (Veb) and the blind cell (Rd); the column-level analog front-end circuit is based on the received second bias voltage (V)_fid) And a pixel (Rs) included in the column-level analog front-end circuit generates a second current; obtaining the difference (I) between the two currents according to the first current and the second current_diff)。