CN113439336A

CN113439336A - Three-dimensional phase change memory device and forming method thereof

Info

Publication number: CN113439336A
Application number: CN202180001535.9A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2021-05-18
Filing date: 2021-05-18
Publication date: 2021-09-24
Anticipated expiration: 2041-05-18
Also published as: WO2022241635A1; CN113439336B

Abstract

A three-dimensional (3D) memory device, comprising: a stacked layer structure including a plurality of word line layers and a plurality of dielectric layers which are staggered; and a plurality of Phase Change Memory (PCM) strings. Each of the PCM strings extends through the stacked layer structure in a first direction and includes: an isolation structure extending through the stacked layer structure in a first direction; and a plurality of PCM string portions separated by isolation structures. Each PCM string portion includes a local bitline, a selector layer that interfaces with the local bitline, and a plurality of PCM structures between the selector layer and a plurality of wordline layers.

Description

Three-dimensional phase change memory device and forming method thereof

Background

The present disclosure relates to a Phase Change Memory (PCM) device and a method of manufacturing the same.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. As a result, the memory density for planar memory cells approaches an upper limit.

Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, PCMs may utilize the difference between the resistivities of the amorphous and crystalline phases in a phase change material based on electrothermal heating and quenching of the phase change material. PCM array cells may be vertically stacked in 3D to form a 3D PCM.

Disclosure of Invention

In one aspect, a three-dimensional (3D) memory device includes: a stacked layer structure including a plurality of word line layers and a plurality of dielectric layers which are staggered; and a plurality of Phase Change Memory (PCM) strings, each of the PCM strings extending through the stacked layer structure in a first direction and including: an isolation structure extending through the stacked layer structure in a first direction; and a plurality of PCM string portions separated by isolation structures, each PCM string portion including a local bitline, a selector layer interfacing the local bitline, and a plurality of PCM structures between the selector layer and the plurality of wordline layers.

In another aspect, a three-dimensional (3D) memory device includes: a stacked layer structure including a plurality of word line layers and a plurality of dielectric layers which are staggered; and a plurality of Phase Change Memory (PCM) strings, each of the PCM strings extending through the stacked layer structure in a first direction and including: local bit lines extending in a first direction; a selector layer, the selector layer external to the local bit line; a plurality of isolation structures extending in a first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and a plurality of PCM structures between the selector layer and the plurality of wordline layers in the second direction, each of the plurality of PCM structures between two of the plurality of isolation structures in the second direction.

In another aspect, a system comprises: a three-dimensional (3D) memory device configured to store data, the 3D memory device comprising: a stacked layer structure including a plurality of word line layers and a plurality of dielectric layers which are staggered; and a plurality of Phase Change Memory (PCM) strings, each of the PCM strings extending through the stacked layer structure in a first direction and including: an isolation structure extending through the stacked layer structure in a first direction; and a plurality of PCM string portions separated by isolation structures, each PCM string portion comprising a local bitline, a selector layer interfacing the local bitline, and a plurality of PCM structures between the selector layer and the plurality of wordline layers; and a memory controller coupled to the 3D memory device and configured to control operation of the plurality of PCM cells through the local bit lines and the plurality of word lines.

In another aspect, a system comprises: a three-dimensional (3D) memory device configured to store data, the 3D memory device comprising: a stacked layer structure including a plurality of word line layers and a plurality of dielectric layers which are staggered; and a plurality of Phase Change Memory (PCM) strings, each of the PCM strings extending through the stacked layer structure in a first direction and including: local bit lines extending in a first direction; a selector layer, the selector layer external to the local bit line; a plurality of isolation structures extending in a first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and a plurality of PCM structures between the selector layer and the plurality of wordline layers in the second direction, each of the plurality of PCM structures between two of the plurality of isolation structures in the second direction; and a memory controller coupled to the 3D memory device and configured to control operation of the plurality of PCM cells through the local bit lines and the plurality of word lines.

In yet another aspect, a method for forming a three-dimensional (3D) memory device includes: forming a stacked layer structure on a substrate, the stacked layer structure including a plurality of conductive layers and a plurality of dielectric layers which are interleaved; and forming a Phase Change Memory (PCM) string extending through the stacked layer structure in a first direction, wherein the PCM string comprises: an isolation structure extending through the stacked layer structure in a first direction; a plurality of PCM string portions separated by isolation structures, each PCM string portion comprising: a local bit line structure extending in a first direction; a selector layer, which is externally connected with the corresponding local bit line; and a plurality of PCM structures between the selector layer and the plurality of conductive layers, respectively.

In yet another aspect, a method for forming a three-dimensional (3D) memory device includes: forming a stacked layer structure on a substrate, the stacked layer structure including a plurality of conductive layers and a plurality of dielectric layers which are interleaved; and forming a plurality of Phase Change Memory (PCM) strings extending through the stacked layer structure in a first direction, each PCM string comprising: local bit lines extending in a first direction; a selector layer, the selector layer external to the local bit line; a plurality of isolation structures extending in a first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and a plurality of PCM structures between the selector layer and the plurality of conductive layers in the second direction, the plurality of PCM structures being between two of the plurality of isolation structures in the second direction.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

FIG. 1 shows a perspective view of a 3D cross point (XPoint) memory device.

Fig. 2A illustrates a plan view of a cross-section of an example 3D PCM device according to some aspects of the present disclosure.

Fig. 2B illustrates a plan view of a cross-section of an example 3D PCM device according to some aspects of the present disclosure.

Fig. 2C illustrates a side view of a cross-section of an example 3D PCM device according to some aspects of the present disclosure.

Fig. 2D illustrates a partially enlarged plan view of a cross-section of an example 3D PCM device according to some aspects of the present disclosure.

Fig. 3A illustrates a plan view of a cross-section of another example 3D PCM device according to some aspects of the present disclosure.

Fig. 3B illustrates a side view of a cross-section of another example 3D PCM device according to some aspects of the present disclosure.

Fig. 3C illustrates a side view of a cross-section of another example 3D PCM device according to some aspects of the present disclosure.

Fig. 4A-4E illustrate PCM cell array layouts of various example 3D PCM devices according to various aspects of the present disclosure.

Fig. 5A-5H illustrate an example fabrication process for forming a 3D PCM device according to some aspects of the present disclosure.

Fig. 6A-6D illustrate plan views of cross-sections of an exemplary fabrication process for forming a 3D PCM device, according to some aspects of the present disclosure.

Fig. 6E-6H illustrate side views of cross-sections of an exemplary fabrication process for forming a 3D PCM device, according to some aspects of the present disclosure.

Fig. 7A illustrates a flow diagram of an example method for forming a 3D PCM device according to some aspects of the present disclosure.

Fig. 7B illustrates a flow diagram of another exemplary method for forming a 3D PCM device according to some aspects of the present disclosure.

Fig. 8 illustrates a block diagram of an example system with a 3D memory device, in accordance with some aspects of the present disclosure.

FIG. 9A illustrates a diagram of an example memory card with a 3D memory device, according to some aspects of the present disclosure.

Fig. 9B illustrates a diagram of an example Solid State Drive (SSD) with 3D memory devices, according to some aspects of the disclosure.

The present disclosure will be described with reference to the accompanying drawings.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements may be used without departing from the scope of the present disclosure. Furthermore, the present disclosure may also be used in various other applications. The functional and structural features as described in this disclosure may be combined, adjusted and modified with each other, and in a manner not specifically depicted in the drawings, so that such combinations, adjustments and modifications are within the scope of the present disclosure.

In general, terms may be understood at least in part from the context of their use. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a" or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on the context.

It should be readily understood that the meaning of "on …", "above …" and "above …" in this disclosure should be interpreted in the broadest manner such that "on …" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween, and "above …" or "above …" means not only "above something" or "above something", but may also include the meaning of "above something" or "above something" with no intervening features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations in use or operation of the device in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 80 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material upon which a subsequent layer of material is added. Such a substrate may itself be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of a continuous structure, uniform or non-uniform, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes at or between the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (in which interconnect lines, and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term "3D memory device" refers to a semiconductor device having memory cells that may be vertically arranged on a laterally oriented substrate such that the number of memory cells may be increased proportionally in a vertical direction relative to the substrate. As used herein, the term "vertical" means perpendicular to the lateral surface of the substrate.

PCMs may utilize the difference between the resistivity of amorphous and crystalline phases in a phase change material (e.g., a chalcogenide alloy) based on electrothermal heating and quenching of the phase change material. Phase change material in a PCM cell may be located between two electrodes and a current may be applied to repeatedly switch the material (or at least a portion thereof that blocks the current path) between the two phases to store data. PCM cells may be vertically stacked in 3D to form a 3D PCM.

The 3D PCM includes a 3D cross-point (XPoint) memory that stores data based on a change in resistance of a bulk material property (e.g., in a high resistance state or a low resistance state) in conjunction with a stackable cross-point data access array that is bit addressable. For example, FIG. 1 shows a perspective view of a 3D XPoint memory device 100. According to some embodiments, 3D XPoint memory device 100 has a transistorless crosspoint architecture that positions memory cells at the intersections of vertical conductors. 3D XPoint memory device 100 includes a plurality of parallel lower bit lines 102 in the same plane and a plurality of parallel upper bit lines 104 above lower bit lines 102 in the same plane. 3D XPoint memory device 100 also includes a plurality of parallel word lines 106 vertically between lower bit lines 102 and upper bit lines 104 in the same plane. As shown in fig. 1, each lower bit line 102 and each upper bit line 104 extend laterally along a bit line direction in plan view (parallel to the wafer plane), and each word line 106 extends laterally in a word line direction in plan view. Each wordline 106 is perpendicular to each lower bitline 102 and each upper bitline 104.

It should be noted that the x-axis and y-axis are included in fig. 1 to show two orthogonal directions in the plane of the wafer. The x-direction is the word line direction and the y-direction is the bit line direction. It should be noted that the z-axis is also included in FIG. 1 to further illustrate the spatial relationship of the components in 3D XPoint memory device 100. The substrate (not shown) of 3D XPoint memory device 100 includes two lateral surfaces that extend laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the back side opposite the front side of the wafer. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, when a substrate is positioned in the lowest plane of a semiconductor device (e.g., 3D XPoint memory device 100) in the z-direction (the vertical direction perpendicular to the x-y plane), whether one component (e.g., layer or device) of the semiconductor device is "on," "above," or "below" another component (e.g., layer or device) is determined in the z-direction relative to the substrate of the semiconductor device. The same concepts used to describe spatial relationships apply throughout this disclosure.

As shown in FIG. 1, 3D XPoint memory device 100 includes a plurality of memory cells 108, each memory cell 108 disposed at an intersection of a lower bitline 102 or an upper bitline 104 and a corresponding wordline 106. Each memory cell 108 has a vertical square pillar shape. Each memory cell 108 includes at least a vertically stacked PCM element 110 and a selector 112. Each memory cell 108 stores a single bit of data and can be written to and read by varying the voltage applied to the corresponding selector 112 (which replaces the need for a transistor). Each memory cell 108 is individually accessed by currents applied through top and bottom conductors (e.g., the respective word line 106 and the lower or upper bit line 102, 104) in contact with each memory cell 108. The memory cells 108 in the 3D XPoint memory device 100 are arranged in a memory array.

To form 3D XPoint memory device 100, bottom memory cells 108 in a bottom cell stack between lower bit lines 102 and word lines 106 are first formed by patterning both lower bit lines 102 and word lines 106 to define bottom pillar memory cells 108, followed by top cell stack deposition and upper bit lines 104 patterning to define top pillar memory cells 108. Each stack is formed using two self-aligned double patterning (SADP) processes. Further scaling will add more stacked layers on top to reduce manufacturing costs. However, due to the high cost associated with the additional SADP process for each stacked layer formation, the cost benefit will be reduced.

To address one or more of the above issues, the present disclosure introduces a novel architecture for 3D PCM devices with lower manufacturing costs. In the architectures disclosed herein, the lateral word lines may all be formed together, e.g., by replacing the sacrificial layer, and the local bit lines may all be formed perpendicular to the word lines, with global bit lines connecting the local bit lines in different regions. The PCM structure may be formed in a recess of a wordline, while the selector layer may be deposited as a continuous layer due to its insulator properties. As a result, in the architectures disclosed herein, SADP processes may be eliminated and misalignment between different cell stack layers may be avoided. Furthermore, no additional lithography process is required to scale up the word lines vertically. Thus, the 3D PCM devices disclosed herein may provide more flexible scaling and cost reduction compared to conventional 3D XPoint memory devices. Last but not least, the local bit lines and the PCM memory cells can be separated into two or four by forming isolation structures in the holes to separate the memory cells. Thus, the 3D PCM device disclosed herein may store more bits per memory cell.

Fig. 2A illustrates a plan view of a cross-section of an example 3D PCM device 200 according to some aspects of the present disclosure. As shown in fig. 2A, the 3D PCM device 200 may include an array of PCM strings 220 and one or more slot structures 205. Each PCM string 220 includes an isolation structure 214 that separates the PCM string 220 into a plurality of PCM string portions (e.g., into two PCM string portions, such as PCM string portions 2201 and 2202). In some embodiments, the isolation structure 214 is formed in the middle of the PCM string 220 and separates the PCM string 220 into two semicircular shapes in a plan view. It should be understood that the shape of the PCM string portion in plan view is not limited to a semicircle, and may be any other shape. Further, the isolation structure 214 is not limited to be formed in the middle of the PCM string 220, and may be formed at the side of the PCM string 220 or at any position. Nor is it limited to including only one isolation structure 214 in each PCM string 220 and multiple isolation structures may be formed in each PCM string 220. In some implementations, the isolation structures 214 of the 3D PCM device 200 extend laterally in the y-direction. The slot structure 205 may extend laterally in the x-direction to divide the 3d PCM device 200 into a plurality of regions, e.g., blocks, fingers, pages, etc., in the y-direction, each of the plurality of regions including a plurality of PCM strings 220. Each region may correspond to a minimum unit for a memory operation (e.g., read, program (write), or erase in different examples) of the 3D PCM device 200. In some embodiments, the word lines of the 3D PCM device 200 extend laterally in the x-direction and the bit lines of the 3D PCM device 200 extend laterally in the y-direction perpendicular to the x-direction. That is, in the present disclosure, the x-direction may correspond to a word line direction, and the y-direction may correspond to a bit line direction.

Fig. 2B illustrates a plan view of a cross-section of another example 3D PCM device 250 according to some aspects of the present disclosure. As shown in fig. 2B, the 3D PCM device 250 may include an array of PCM strings 240 and one or more slot structures 255. Each PCM string 240 includes an isolation structure 245 that separates the PCM string 240 into a plurality of PCM string portions (e.g., into four PCM string portions, such as

PCM string portions

2401, 2402, 2403 and 2404). In some embodiments, the isolation structure 245 is cross-shaped and is formed in the middle of the PCM string 240 to separate the PCM string 240 into four fan shapes in a plan view. It should be understood that the shape of the PCM string portion in plan view is not limited to a sector shape, and may be any other shape. In addition, the isolation structure 245 is not limited to be formed in the middle of the PCM string 240, and may be formed at a side of the PCM string 240 or any position. Nor is it limited to including only one isolation structure 245 in each PCM string 240 and multiple isolation structures may be formed in each PCM string 240. In some embodiments, isolation structures 245 of 3D PCM device 250 extend laterally in the y-direction and the x-direction. The slot structure 255 may extend laterally in the x-direction to divide the 3D PCM device 250 into a plurality of regions, e.g., blocks, fingers, pages, etc., in the y-direction, each of the plurality of regions including a plurality of PCM strings 240. Each region may correspond to a minimum unit for a memory operation (e.g., read, program (write), or erase in different examples) of the 3D PCM device 250. In some embodiments, the word lines of the 3D PCM device 250 extend laterally in the x-direction and the bit lines of the 3D PCM device 250 extend laterally in the y-direction perpendicular to the x-direction. That is, in the present disclosure, the x-direction may correspond to a word line direction, and the y-direction may correspond to a bit line direction.

Fig. 2C illustrates a side view of a cross-section of an example 3D PCM device 200 according to some aspects of the present disclosure. In some embodiments, the 3D PCM device 200 is an example of the 3D PCM device 200 in fig. 2A, and a cross-section of the 3D PCM device 200 is along an AA plane of the 3D PCM device 200 in fig. 2A. It should be noted that the disclosed structure in the example 3D PCM device 200 of fig. 2C may also be implemented in the example 3D PCM device 250 of fig. 2B, with appropriate adjustments. As shown in fig. 2C, the 3D PCM device 200 may include a substrate 202, and the substrate 202 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some implementations, the substrate 202 is a thinned substrate (e.g., a semiconductor layer) that is thinned by grinding, wet/dry etching, Chemical Mechanical Polishing (CMP), or any combination thereof. In some embodiments, the substrate 202 may be removed by a lift-off process, and the 3D PCM device 200 may be adhered to another permanent substrate (not shown) by a wafer bonding process.

In some embodiments, one or more peripheral devices (not shown) are formed on substrate 202 and/or in substrate 202. The peripheral devices may include any suitable digital, analog, and/or mixed signal peripheral circuitry for facilitating operation of the 3D PCM device 200. For example, the peripheral devices may include one or more of data buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references, or any active or passive component of a circuit (e.g., a transistor, diode, resistor, or capacitor).

As shown in fig. 2C, the 3D PCM device 200 may also include a memory array device, e.g., an array of PCM strings 220, formed on the substrate 202. As used herein, when a substrate (e.g., substrate 202) is positioned in a z-direction (vertical direction) in a lowest plane of a semiconductor device (e.g., 3D PCM device 200), whether one component (e.g., layer or device) of the semiconductor device is "on," "above," or "below" another component (e.g., layer or device) is determined in the z-direction relative to the substrate of the semiconductor device. The same concepts used to describe spatial relationships apply throughout this disclosure.

In some implementations, each PCM string 220 may include multiple PCM string portions (e.g., two PCM string portions 2201 and 2202). Each

PCM string portion

2201 or 2202 may include a plurality of vertically stacked PCM cells 211. That is, the PCM cells 211 of the 3D PCM device 200 are vertically stacked and provided in each PCM string portion of the PCM string 220. In some embodiments, multiple PCM string portions (e.g., two PCM string portions 2201 and 2202) are separated by isolation structure 214. As shown in fig. 2C, the PCM string 220 may extend in the z-direction (vertical direction) through interleaved conductive layers 226 and dielectric layers 208 (also referred to herein as a "conductive/dielectric layer pair"). The interleaved conductive layers 226 and dielectric layers 208 are also referred to herein as a stacked layer structure 224. The number of conductive/dielectric layer pairs in the stacked layer structure 224 may set the number of PCM cells 211 in the 3d PCM device 200. Isolation structure 214 may comprise any suitable material, such as silicon oxide, silicon nitride, silicon oxynitride, or other insulating material. The conductive layers 226 and the dielectric layers 208 in the stacked layered structure 224 may alternate in the vertical direction. In other words, each conductive layer 226 may be bordered on two sides by two dielectric layers 208, and each dielectric layer 208 may be bordered on two sides by two conductive layers 226, in addition to the layers at the top and bottom of the stacked layered structure 224. The conductive layers 226 may all have the same thickness or have different thicknesses. Similarly, the dielectric layers 208 may all have the same thickness or have different thicknesses. The conductive layer 226 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon (polysilicon), doped silicon, silicide, or any combination thereof. The dielectric layer 208 may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in fig. 2C, each conductive layer 226 may extend laterally (e.g., in the x-direction/wordline direction) and include one or more wordlines of the 3D PCM device 200. Thus, the conductive layer 226 is also referred to herein as a word line layer 226. That is, the stacked layer structure 224 may include interleaved word line layers 226 and dielectric layers 208. In some embodiments, the 3D PCM device 200 includes a plurality of slot structures (not shown in fig. 2C, e.g., 205 in fig. 2A), each of which is filled with one or more dielectric materials and extends through the stacked layer structure 224 in the z-direction to separate each word line layer 226 into a plurality of word lines. That is, each word line layer 226 may include a plurality of word lines separated by a slot structure (e.g., 205 in fig. 2A), such that each region may include a respective one of the word lines. According to some embodiments, as shown in fig. 2C, word line layers 226 (and word lines therein) are parallel to each other and to the top surface of substrate 202. In some embodiments, edges of the wordline layer 226 are staggered at one or more sides of the 3D PCM device 200 to define one or more stair step structures (not shown) for landing on wordline contacts.

As shown in fig. 2C, each PCM string 220 may extend vertically through the stacked layered structure 224 above the substrate 202. In some embodiments, the PCM string 220 includes a hole in which the local bit line 231 and the selector layer 218 are formed. The local bit lines 231 may include a conductive material including, but not limited to, W, Co, Cu, Al, doped polysilicon, silicide, or any combination thereof. In one example, the local bit line 231 may include a metal, e.g., W. Thus, the 3D PCM device 200 may include an array of parallel local bitlines 231, each local bitline 231 extending vertically in the z-direction. Unlike 3D XPoint memory device 100 in which bitline 102/104 and wordline 106 all extend laterally and are parallel to each other, in 3D PCM device 200, local bitline 231 is perpendicular to the wordlines in wordline layer 226. As shown in fig. 2C, the 3D PCM device 200 may further include a plurality of global bitlines 233 in contact with the corresponding local bitlines 231.

As shown in fig. 2C, the selector layer 218 may be a continuous layer formed along the sidewalls and bottom surface of the holes of the PCM string 220. That is, in some embodiments, the selector layer 218 circumscribes the local bit line 231. The portion of the selector layer 218 on the bottom surface of the pores of the PCM strings 220 may also separate the local bit lines 231 from the substrate 202 to provide insulation. In addition, selector layer 218 may include a threshold switching material that exhibits resistive switching behavior upon application of an external bias voltage above a threshold voltage. In some embodiments, the threshold switching material comprises an Ovonic Threshold Switching (OTS) material, such as zinc telluride (ZnTe), germanium telluride (GeTe), niobium oxide (NbO), or arsenic silicon telluride (SiAsTe), that exhibits field-dependent volatile resistive switching behavior (also known as the "OTS phenomenon") upon application of an external bias voltage above a threshold voltage. In some embodiments, the threshold switch material comprises a metal wire threshold switch (MFTS) material, e.g., a metal ion reservoir for supplying metal ions such as silver (Ag), copper (Cu), silver sulfide (AgS), copper sulfide (CuS), silver selenide (AgSe), copper selenide (CuSe) in contact with a solid electrolyte such as germanium selenide (GeSe), germanium sulfide (GeS), silver selenide (AgSe), silver sulfide (AgS), or copper telluride (CuTe).

In some embodiments, each PCM string 220 further includes a plurality of PCM structures 212 laterally between the selector layer 218 and the word line layer 226 in the x-direction and/or the y-direction, respectively. According to some embodiments, as shown in fig. 2C, each PCM structure 212 is recessed from sidewalls of a hole of the PCM string 220 into a respective wordline layer 226. In some embodiments, PCM structures 212 are also separated in the z-direction by dielectric layers 208, such as word line layers 226. As shown in fig. 2C, the separate PCM structure 212 may be in contact with the continuous selector layer 218 in each PCM string portion 2201.

In some embodiments, as shown in fig. 2C, the portion of the selector layer 218 in contact with the PCM structure 212 may be considered in this disclosure as a selector 213 of the PCM cell 211. That is, the selector layer 218 may include a plurality of selectors 213 respectively in contact with the PCM structure 212. Each selector 213 may be part of a continuous selector layer 218. Each PCM structure 212 may be formed between a respective word line of the word line layer 226 and a respective selector 213 in the x-direction and/or the y-direction.

As described above, each PCM string 220 may include a plurality of PCM cells 211 stacked in the z-direction. In some embodiments, each PCM cell 211 includes a PCM structure 212 and a selector 213 in contact with the PCM structure 212 (i.e., the portion of the selector layer 218 in contact with the respective PCM structure 212). According to some embodiments, as shown in fig. 2C, each PCM cell 211 of a PCM string 220 is disposed at an intersection of a local bit line 231 of the PCM string 220 and a corresponding word line of the word line layer 226. In some embodiments, as shown in fig. 2C, each PCM structure 212 includes a PCM element 216 in contact with a respective selector 213 in the selector layer 218 and a respective wordline in the wordline layer 226. The PCM element 216 may include a phase change material. The phase change material may include a chalcogenide-based alloy (chalcogenide glass), such as a germanium antimony telluride (GeSbTe or GST) alloy or any other suitable phase change material. The PCM element 216 may utilize the difference between the resistivity of the amorphous and crystalline phases in the phase change material based on electrothermal heating and quenching of the phase change material. A current may be applied to repeatedly switch the phase change material of PCM element 216 (or at least a portion thereof that blocks the current path) between the two phases to store data. A single data bit may be stored in each PCM cell 211 and may be written or read by varying the voltage applied to the corresponding selector 213.

As shown in fig. 2C, the 3D PCM device 200 may further include a global bitline 233 extending in the y-direction (e.g., bitline direction) and contacting the plurality of local bitlines 231. That is, global bit line 233 may be perpendicular to local bit line 231, but parallel to the word lines in word line layer 226. The global bit lines 233 may comprise a conductive material including, but not limited to, W, Co, Cu, Al, doped polysilicon, silicide, or any combination thereof. In one example, global bit line 233 may include a metal, e.g., W. In some embodiments, each 3D PCM device 200 may include two global bit lines 233 in contact with two local bit lines 231 of two respective

PCM string portions

2201 and 2202. By separating one PCM string 220 into two

PCM string portions

2201 and 2202 with isolation structures 214, more bits can be stored in each PCM string 220.

Fig. 2D is a plan view of a cross-section of an example 3D PCM device 200 according to some aspects of the present disclosure. Fig. 2D may be a plan view of a cross section of the 3D PCM device 200 along the BB plane in fig. 2C. According to some embodiments, each PCM structure 212 is combined with an isolation structure 214 to circumscribe a selector layer 218, as shown in fig. 2D. Each PCM structure 212 may also be formed between a respective wordline of the isolation structures 214, the selector layer 218, and the wordline layer 226 in the x-direction and/or the y-direction. That is, each PCM structure 212 is interposed between a respective word line of the word line layer 226, the selector layer 218, and the isolation structure 214 in the x-direction and/or the y-direction. Further, as shown in fig. 2D, the cross section of the local bit line 231 has a semicircular shape. The cross-section of the selector layer 218 may have a semi-circular shape that circumscribes the semi-circular shape of the local bit line 231. The cross-section of the PCM structure 212 in combination with the isolation structure 214 and the local bit line 231 may circumscribe the semi-toroidal shape of the selector layer 218.

Fig. 3A illustrates a plan view of a cross-section of an example 3D PCM device 300 according to some aspects of the present disclosure. As shown in fig. 3A, the 3D PCM device 300 may include an array of PCM strings 320 and one or more slot structures 305. In some embodiments, isolation structures 336 are formed on both sides of the PCM string 320 and in line with the slot structures 305 in the x-direction. It should be understood that the isolation structures 336 are not limited to being formed on two opposite sides of the PCM string 320 as shown in fig. 3A, and may be formed on any side of the PCM string 320. Nor is it limited to including only two isolation structures 336 in each PCM string 320 and multiple isolation structures may be included in each PCM string 320. The slot structure 305 may extend laterally in the x-direction to divide the 3D PCM device 300 into a plurality of regions, e.g., blocks, fingers, pages, etc., in the y-direction, each of the plurality of regions including a plurality of PCM strings 320. Each PCM string may comprise a plurality of PCM string portions or a plurality of PCM cells. Each region may correspond to a minimum unit for a memory operation (e.g., read, program (write), or erase in different examples) of the 3D PCM device 300. As a result, the 3D PCM device 300 may not require an additional slit structure to define the region. In some embodiments, the slot structure 305 may be used to replace the sacrificial layer with a word line layer by a process that includes removing the sacrificial layer with an etching process through the slot structure and depositing the word line layer. In some embodiments, the word lines of the 3D PCM device 300 extend laterally in the x-direction and the global bit lines of the 3D PCM device 300 extend laterally in the y-direction perpendicular to the x-direction. That is, in the present disclosure, the x-direction may correspond to a word line direction and the y-direction may correspond to a global bit line direction.

Fig. 3B illustrates a side view of a cross-section of an example 3D PCM device 300 according to some aspects of the present disclosure. In some embodiments, the 3D PCM device 300 is an example of the 3D PCM device 300 in fig. 3A, and a cross-section of the 3D PCM device 300 is along the AA plane of the 3D PCM device 300 in fig. 3A. As shown in fig. 3B, the 3D PCM device 300 may include a substrate 302, and the substrate 302 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some implementations, the substrate 302 is a thinned substrate (e.g., a semiconductor layer) that is thinned by grinding, wet/dry etching, Chemical Mechanical Polishing (CMP), or any combination thereof. In some embodiments, the substrate 302 may be removed by a lift-off process and the 3DPCM device 300 may be adhered to another permanent substrate (not shown) by a wafer bonding process.

In some embodiments, one or more peripheral devices (not shown) are formed on substrate 302 and/or in substrate 302. The peripheral devices may include any suitable digital, analog, and/or mixed signal peripheral circuitry for facilitating operation of the 3D PCM device 300. For example, the peripheral devices may include one or more of data buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references, or any active or passive component of a circuit (e.g., a transistor, diode, resistor, or capacitor).

As shown in fig. 3A, the 3D PCM device 300 may also include a memory array device, e.g., an array of PCM strings 320, formed on the substrate 302. As used herein, when a substrate (e.g., substrate 302) is positioned in a z-direction (vertical direction) in a lowest plane of a semiconductor device (e.g., 3D PCM device 300), whether one component (e.g., layer or device) of the semiconductor device is "on," "above," or "below" another component (e.g., layer or device) is determined in the z-direction relative to the substrate of the semiconductor device. The same concepts used to describe spatial relationships apply throughout this disclosure.

In some embodiments, the PCM cells 311 of the 3D PCM device 300 are vertically stacked and provided in each PCM string 320. That is, each PCM string 320 may include a plurality of vertically stacked PCM cells 311. As shown in fig. 3B, the PCM string 320 may extend in the z-direction (vertical direction) through interleaved conductive layers 326 and dielectric layers 308 (also referred to herein as a "conductive/dielectric layer pair"). The interleaved conductive layers 326 and dielectric layers 308 are also referred to herein as a stacked layer structure 324. The number of conductive/dielectric layer pairs in the stacked layered structure 324 may set the number of PCM cells 311 in the 3D PCM device 300. The conductive layers 326 and the dielectric layers 308 in the stacked layered structure 324 may alternate in the vertical direction. In other words, each conductive layer 326 may be bordered on two sides by two dielectric layers 308, and each dielectric layer 308 may be bordered on two sides by two conductive layers 326, except for the layers at the top and bottom of the stacked layered structure 324. The conductive layers 326 may all have the same thickness or have different thicknesses. Similarly, the dielectric layers 308 may all have the same thickness or have different thicknesses. Conductive layer 326 may comprise a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon (polysilicon), doped silicon, silicide, or any combination thereof. The dielectric layer 308 may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

Each conductive layer 326 may extend laterally (e.g., in the x-direction/wordline direction) and include one or more wordlines of the 3D PCM device 300. Thus, conductive layer 326 is also referred to herein as word line layer 326. That is, the stacked layer structure 324 may include interleaved word line layers 326 and dielectric layers 308. In some embodiments, the 3D PCM device 300 includes a plurality of slot structures (not shown in fig. 3B, e.g., 305 in fig. 3A), each of which is filled with one or more dielectric materials and extends through the stacked layer structure 324 in the z-direction. That is, each word line layer 326 may include a plurality of word lines separated by a slot structure (e.g., 305 in fig. 3A) in the x-direction/global bit line direction, such that each region may include a respective one of the word lines. According to some embodiments, as shown in fig. 3B, word line layers 326 (and word lines therein) are parallel to each other and to the top surface of substrate 302. In some embodiments, the edges of the wordline layer 326 are staggered at one or more sides of the 3D PCM device 300 to define one or more stair step structures (not shown) for landing on wordline contacts.

As shown in fig. 3B, each PCM string 320 may extend vertically through the stacked layered structure 324 above the substrate 302. In some embodiments, the PCM string 320 includes a hole in which the local bit line 331 and the selector layer 318 are formed. The local bit lines 331 may include conductive materials including, but not limited to, W, Co, Cu, Al, doped polysilicon, silicide, or any combination thereof. In one example, local bit line 331 may include a metal, e.g., W. Thus, the 3D PCM device 300 may include an array of parallel local bit lines 331, each local bit line 331 extending vertically in the z-direction. Unlike 3D XPoint memory device 100 in which bitline 102/104 and wordline 106 all extend laterally and are parallel to each other, in 3D PCM device 300, local bitline 331 is perpendicular to the wordlines in wordline layer 326. As shown in FIG. 3B, the 3D PCM device 300 may also include a plurality of global bitlines 333 in contact with corresponding local bitlines 331.

As shown in fig. 3B, the selector layer 318 may be a continuous layer formed along the sidewalls and bottom surface of the aperture. That is, in some embodiments, the selector layer 318 circumscribes the local bit line 331. The portion of the selector layer 318 on the bottom surface of the hole may also separate the local bit line 331 from the substrate 302 to provide isolation. According to some embodiments, in plan view, the cross-section of the local bit line 331 has a circular shape, and the cross-section of the selector layer 318 has a ring shape circumscribing the circular shape of the local bit line 331. Further, in plan view, selector layer 318 may include a threshold switching material that exhibits resistive switching behavior upon application of an external bias voltage above a threshold voltage. In some embodiments, the threshold switching material comprises an Ovonic Threshold Switching (OTS) material, such as zinc telluride (ZnTe), germanium telluride (GeTe), niobium oxide (NbO), or arsenic silicon telluride (SiAsTe), that exhibits field-dependent volatile resistive switching behavior (also known as the "OTS phenomenon") upon application of an external bias voltage above a threshold voltage. In some embodiments, the threshold switch material comprises a metal wire threshold switch (MFTS) material, e.g., a metal ion reservoir for supplying metal ions such as silver (Ag), copper (Cu), silver sulfide (AgS), copper sulfide (CuS), silver selenide (AgSe), copper selenide (CuSe) in contact with a solid electrolyte such as germanium selenide (GeSe), germanium sulfide (GeS), silver selenide (AgSe), silver sulfide (AgS), or copper telluride (CuTe).

In some embodiments, each PCM string 320 further includes a plurality of PCM structures 312 laterally between the selector layer 318, the word line layer 326, and the isolation structures 336, respectively, in the x-direction and/or the y-direction. According to some embodiments, as shown in fig. 3B, each PCM structure 312 is recessed from the sidewalls of the hole of the PCM string 320 into a respective wordline layer 326. In some embodiments, such as word line layer 326, PCM structures 312 are also separated in the z-direction by dielectric layers 308. As shown in fig. 3B, the separate PCM structures 312 may be in contact with a continuous selector layer 318 in each PCM string. According to some embodiments, each PCM structure 312 shown in fig. 3B in combination with the isolation structure 336 shown in fig. 3A circumscribes the selector layer 318 shown in fig. 3B. For example, in plan view, a cross-section of the selector layer 318 may have a ring shape, and a cross-section of the PCM structure 312 in combination with the isolation structure 336 may also form a ring shape that circumscribes the ring shape of the selector layer 318. In the present disclosure, the portion of the selector layer 318 in contact with the PCM structure 312 may be considered as the selector 313 of the PCM cell 311. That is, the selector layer 318 may include a plurality of selectors 313 respectively in contact with the PCM structure 312. Each selector 313 may be part of a continuous selector layer 318. Each PCM structure 312 may be formed between a respective word line of the word line layer 326 and a respective selector 313 in the x-direction and/or the y-direction. Each PCM structure 312 may also be formed between two isolation structures 336 in the x-direction and/or the y-direction. That is, each PCM structure 312 surrounds a respective wordline of the wordline layer 326, a respective selector of the selector layer 318, and two isolation structures 336 in a lateral direction. And each PCM structure 312 surrounds between the dielectric layers 308 in the vertical direction. In some embodiments, isolation structures 336 may comprise any suitable material, such as silicon oxide, silicon nitride, silicon oxynitride, or other insulating material.

As described above, each PCM string 320 may include a plurality of PCM cells 311 stacked in the z-direction. In some embodiments, each PCM cell 311 comprises two PCM cell portions (not shown), each PCM cell portion having a PCM structure 312 and a selector 313 in contact with the PCM structure 312 (i.e. the portion of the selector layer 318 in contact with the respective PCM structure 312). As shown in fig. 3B, each PCM cell portion of PCM cells 311 is disposed at an intersection of a local bit line 331 of a PCM string 320 and a corresponding word line of a word line layer 326. According to some embodiments, as shown in fig. 3C, each PCM cell portion of the PCM cell 311 is also disposed at the intersection of two isolation structures 336. In some embodiments, as shown in fig. 3B, each PCM structure 312 includes a PCM element 316 in contact with a respective selector 313 in the selector layer 318 and a respective word line in the word line layer 326. The PCM element 316 may include a phase change material. The phase change material may include a chalcogenide-based alloy (chalcogenide glass), such as a germanium antimony telluride (GeSbTe or GST) alloy or any other suitable phase change material. The PCM element 316 may utilize the difference between the resistivity of the amorphous and crystalline phases in the phase change material based on electrothermal heating and quenching of the phase change material. A current may be applied to repeatedly switch the phase change material of the PCM element 316 (or at least a portion thereof that blocks the current path) between the two phases to store data. A single data bit may be stored in each PCM cell portion of PCM cells 311 and the single data bit may be written or read by varying the voltage applied to the corresponding selector 313. That is, in some embodiments, each PCM cell 311 may store two bits.

As shown in fig. 3B, the 3D PCM device 300 may further include a global bitline 333 extending in the y-direction (e.g., bitline direction) and in contact with the plurality of local bitlines 331. That is, global bit lines 333 may be perpendicular to local bit lines 331, but parallel to the word lines in word line layer 326. Global bitlines 333 can comprise a conductive material including, but not limited to, W, Co, Cu, Al, doped polysilicon, suicide, or any combination thereof. In one example, global bit line 333 may include a metal, e.g., W. In some embodiments, each 3D PCM device 300 may include one global bitline 333 in contact with one local bitline 331 of a corresponding PCM string 320.

Fig. 3C illustrates a side view of a cross-section of an example 3D PCM device 300 according to some aspects of the present disclosure. In some embodiments, the 3D PCM device 300 is an example of the 3D PCM device 300 in fig. 3A, and a cross-section of the 3D PCM device 300 is along a BB plane of the 3D PCM device 300 in fig. 3A. From a side view of this cross-section along the BB plane, isolation structures 336 are coupled to sidewalls of selector layer 318. The selector layer 318 circumscribes the local bit line 331. In plan view, the two isolation structures 336 separate each PCM cell 311 into two PCM cell portions in a lateral direction. By separating one PCM cell 311 into two PCM cell portions with isolation structures 336, more bits can be stored in each PCM string 320.

Fig. 8 illustrates a block diagram of an example system 800 with a 3D memory device, in accordance with some aspects of the present disclosure. System 800 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, Virtual Reality (VR) device, Augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in fig. 8, the system 800 may include a host 808 and a storage system 802, the storage system 802 having one or more 3D memory devices 804 and a memory controller 806. The host 808 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. The host 808 may be configured to send data to the 3D memory device 804 or receive data from the 3D memory device 804.

The 3D memory device 804 may be any 3D memory device disclosed herein, such as the

3D PCM devices

200 and 300 shown in fig. 2A-3C. Consistent with the scope of the present disclosure, a novel architecture of the

3d pwm devices

200 and 300 is provided to reduce manufacturing costs and achieve higher memory densities. As a result, the 3D PCM device disclosed herein may provide more flexible scaling and cost reduction compared to conventional 3D XPoint memory devices.

According to some embodiments, a memory controller 806 (also referred to as controller circuitry) is coupled to the 3D memory device 804 and a host 808 and is configured to control the 3D memory device 804. For example, memory controller 806 may be configured to control the operation of PCM cells 211 through local bit lines 231 and word lines of word line layer 226. The memory controller 806 may manage data stored in the 3D memory device 804 and communicate with a host 808. In some implementations, the memory controller 806 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and so forth. In some implementations, the memory controller 806 is designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that is used as a data store and enterprise storage array for mobile devices such as smart phones, tablet computers, laptop computers, and the like. The memory controller 806 may be configured to control operations of the 3D memory device 804, such as read, erase, and program operations. The memory controller 806 may also be configured to manage various functions with respect to data stored or to be stored in the 3D memory device 804 including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some implementations, the memory controller 806 is also configured to process Error Correction Codes (ECC) with respect to data read from the 3D memory device 804 or written to the 3D memory device 804. The memory controller 806 may also perform any other suitable functions, such as formatting the 3D memory device 804. The memory controller 806 may communicate with external devices (e.g., the host 808) according to a particular communication protocol. For example, the memory controller 806 may communicate with external devices via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.

The memory controller 806 and the one or more 3D memory devices 804 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 802 may be implemented and packaged into different types of end electronic products. In one example as shown in fig. 9A, the memory controller 806 and the single 3D memory device 804 may be integrated into a memory card 902. The memory card 902 may include a PC card (PCMCIA, personal computer memory card International Association), CF card, Smart Media (SM) card, memory stick, MultiMedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microsD, SDHC), UFS, and the like. The memory card 902 may also include a memory card connector 904 that electrically couples the memory card 902 with a host (e.g., host 808 in FIG. 8). In another example as shown in fig. 9B, a memory controller 806 and a plurality of 3D memory devices 804 may be integrated into an SSD 906. SSD 906 may also include an SSD connector 908 that electrically couples SSD 906 with a host (e.g., host 808 in fig. 8). In some implementations, the storage capacity and/or operating speed of SSD 906 is greater than the storage capacity and/or operating speed of memory card 902.

Fig. 4A-4E illustrate PCM cell array layouts of various example

3D PCM devices

450, 451, 452, 453, and 454 according to various aspects of the present disclosure. As shown in fig. 4A, the 3D PCM device 450 may include a plurality of PCM strings 402 (corresponding to the PCM strings 220 in fig. 2A) and a plurality of slot structures 405 (e.g., corresponding to the slot structures 205 in fig. 2A), each slot structure 405 extending in an x-direction (e.g., a wordline direction) to divide the 3D PCM device 450 into a plurality of fingers 406 (also referred to as pages). As described above, each slot structure 405 may also extend in the z-direction to divide each word line layer 226 into separate word lines. In other words, each word line in a respective finger 406 may be individually addressed and controlled by, for example, applying a respective word line voltage. In some embodiments, the plurality of PCM strings 402 may be placed in a staggered arrangement, rather than in an in-line arrangement. This will increase the memory density of the 3D PCM device 450 or have thermal considerations including heat dissipation at critical points, thereby enhancing performance and reliability.

As shown in fig. 4A, the 3D PCM device 450 may also include a plurality of global bitlines 408 (corresponding to the global bitlines 233 in fig. 2C), each global bitline 408 extending in a y-direction (e.g., a bitline direction). In some embodiments as shown in FIG. 4A, each global bitline 408 is electrically connected to multiple PCM strings 402 in different fingers 406; in each finger 406, the PCM string 402 may be electrically connected to two global bit lines 408, rather than one global bit line 408, because the isolation structures 414 separate the PCM string into two PCM string portions (e.g., corresponding to

PCM string portions

2201 and 2202 in fig. 2C). The global bit line 408 may contact a local bit line 410 (e.g., corresponding to local bit line 231 in fig. 2C) via a contact 412. According to some embodiments, each local bit line 410 in one finger 406 is electrically connected to another local bit line 410 in a different finger 406 (but not in the same finger 406) through a respective global bit line 408. In some embodiments, each local bit line 410 in the same finger 406 is electrically connected to a different global bit line 408. As a result, the number of global bitlines 408 may be twice the number of PCM strings 402 in each finger 406. This doubles the bits that 3D PCM device 450 can store in one PCM string 402. Similar to the word lines, each global bit line 408 may be individually addressed and controlled, for example, by applying a corresponding bit line voltage.

In some implementations, to select a particular PCM cell (in the dashed circle in fig. 4A) in any suitable memory operation (e.g., read, write, or erase), the selected global bit line 408, which is electrically connected to the selected PCM cell, is biased at a bit line voltage of Vhh, while the unselected global bit line 408 is biased at a bit line voltage of 0V. As a result, the local bit lines 410 in the different fingers 406 that are in contact with the selected global bit line 408 may also be biased at Vhh. On the other hand, according to some embodiments, the selected word line electrically connected to the selected PCM cell is biased at a word line voltage of Vll, while the unselected word lines in a different word line layer (e.g., at a different level in the z-direction) or the unselected word lines in the same word line layer (e.g., at the same level as the selected word line) but in a different finger 406 are biased at a word line voltage of 0V. As a result, between the selected word line and the selected global bit line 408, only one PCM cell (in the dashed circle in FIG. 4A) is biased at a voltage of Vhh + Vll, and thus the PCM cell becomes the selected PCM cell. In contrast, other PCM cells are biased at Vhh, Vll, or 0V and are therefore unselected.

It should be appreciated that the number of PCM strings 402 and the number of global bitlines 408 in each finger 406 may vary in different examples. For example, as shown in fig. 4A, each finger 406 may include 5 PCM strings 402 electrically connected to 10 global bit lines 408, and each PCM string 402 may overlap two global bit lines 408.

In another example as shown in fig. 4B, the 3D PCM device 451 may include 10 PCM strings 402 in each finger 406, the 10 PCM strings 402 are electrically connected to 20 global bit lines 408, respectively, and each PCM string 402 may overlap with three global bit lines 408. Two of the global bitlines 408 are connected to two respective contacts 412 of each PCM string 402, while one of the global bitlines 408 is formed over an isolation structure 414. It should be noted that isolation structures 414 may be slightly displaced to enable the contact pitch to be reduced.

In another example shown in fig. 4C, the 3D PCM device 452 includes a first isolation structure 414 and a second isolation structure 416 perpendicular to the first isolation structure 414 in a second direction. The first isolation structure 414 and the second isolation structure 416 separate the PCM string 402 into four PCM string portions. Each PCM string portion is electrically connected to one global bit line 408 via a contact 412. In this example, each finger 406 may include 5 PCM strings 402, the 5 PCM strings 402 include 20 PCM string portions electrically connected to 20 global bit lines 408, and each PCM string 402 may overlap four global bit lines 408. According to some embodiments, each local bit line 410 in one finger 406 is electrically connected to another local bit line 410 in a different finger 406 (but not in the same finger 406) through a respective global bit line 408. In some embodiments, each local bit line 410 in the same finger 406 is electrically connected to a different global bit line 408. As a result, the number of global bitlines 408 can be four times the number of PCM strings 402 in each finger 406. That is, since the PCM string 402 is divided into four PCM string portions, this doubles the number of bits that the 3D PCM device 450 can store in one PCM string 402 by four times.

In yet another example shown in fig. 4D, each 3D PCM device 453 includes a first isolation structure 474 and a second isolation structure 476 perpendicular to the first isolation structure 474 in the second direction. The first and

second isolation structures

474 and 476 separate each PCM string 462 into four PCM string portions. Each PCM string portion is electrically connected to one global bit line 468 via contact point 472. In some embodiments, the second isolation structure 476 extending in a first direction (e.g., the x-direction) forms a common isolation structure that overlaps the plurality of PCM strings 462 in the first direction. In the example of fig. 4D, a slot structure is not necessarily required since two adjacent common isolation structures 476 have formed fingers 466. Two adjacent common spacer structures 476 define the area of the fingers 466, which is one of the functions provided by the slot structure. And the plurality of PCM string portions are separated by a first isolation structure 474 and a common isolation structure 476. In this example, each finger 466 may include two half PCM strings 462 (i.e., five half PCM strings 462), the two half PCM strings 462 including 10 PCM string portions electrically connected to 10 global bit lines 468. According to some embodiments, each local bit line 470 in one finger 466 is electrically connected to another local bit line 470 in a different finger 466 (rather than in the same finger 466) through a respective global bit line 468. Since the PCM string 462 is divided into four PCM string portions, this doubles the number of bits that the 3D PCM device 453 can store in one PCM string 462 by four times. Similar to the word lines, each global bit line 468 may be individually addressed and controlled, for example, by applying a corresponding bit line voltage.

In yet another example shown in fig. 4E, the 3D PCM device 454 includes a slot structure 485 that extends in a first direction (e.g., the x-direction) and is perpendicular to the global bitline 488. The slot structure 485 separates the PCM string 482 into two PCM string portions. Each PCM string portion is electrically connected to one global bitline 488 via a contact point 492. In this example, each finger 486 may include two half PCM strings 482 (i.e., five half PCM strings 482) electrically connected to 5 global bitlines 488, and each PCM string 482 may overlap one global bitline 488. According to some embodiments, each local bit line 490 in one finger 486 is electrically connected to another local bit line 490 in a different finger 486 (rather than in the same finger 486) by a respective global bit line 488. In some embodiments, each local bit line 490 in the same finger 486 is electrically connected to a different global bit line 488. The architecture replaces the isolation structure with a slot structure to separate the PCM string 482 into two PCM string portions. As a result, the number of global bitlines 488 can be the same as the number of PCM strings 482 in each finger 486, while no isolation structures are required.

Fig. 5A-5H illustrate an exemplary fabrication process for forming a 3D PCM device according to some embodiments of the present disclosure. Fig. 7A illustrates a flow diagram of an example method 700 for forming a 3D PCM device according to some embodiments of the present disclosure. Examples of the 3D PCM device depicted in fig. 5A-5H and fig. 7A include the 3D PCM device 200 depicted in fig. 2A-2D. Fig. 5A to 5H and fig. 7A will be described together. It should be understood that the operations shown in method 700 are not exhaustive, and that other operations may be performed before, after, or in between any of the operations shown. Further, some operations may be performed concurrently, or in a different order than shown in fig. 7A.

In some embodiments, to form a 3D memory device, a stacked layer structure including a plurality of conductive layers and a plurality of dielectric layers interleaved is formed on a substrate. A PCM string is formed extending in a vertical direction through the stacked layered structure. Each PCM string may comprise two PCM string portions separated by an isolation structure. Each PCM string portion may include a plurality of vertically stacked PCM cells. From a side view of a cross-section of the 3D memory device, each PCM string comprises an isolation structure, two selector layers circumscribing the isolation structure, two local bit lines circumscribing the selector layers, two selector layers circumscribing the local bit lines, and a plurality of PCM structures between the selector layers and the plurality of conductive layers, respectively, in a lateral direction.

Referring to fig. 7A, the method 700 begins at operation 702, where an isolation structure is deposited on a substrate in operation 702. As shown in fig. 5A, isolation structures 514 are formed on substrate 502. In some embodiments, the isolation structures 514 may be deposited in a stacked layer shape and then etched by a photolithography process to form a pillar shape. In some embodiments, isolation structures 514 may be deposited using one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, any other suitable deposition process, or any combination thereof.

The method 700 proceeds to operation 704 where a plurality of sacrificial layers and a plurality of dielectric layers are alternately deposited on the substrate and around the isolation structure, as shown in fig. 7A. As shown in fig. 5A, dielectric layers 508 and sacrificial layers 506 are alternately deposited on substrate 502 and around isolation structures 514 to form sacrificial stack 504. Dielectric layer 508 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high-k) dielectric, and sacrificial layer 506 may comprise any suitable material different from dielectric layer 508. In one example, each dielectric layer 508 may comprise a silicon oxide layer, and each sacrificial layer 506 may comprise a silicon nitride layer. In another example, each dielectric layer 508 may comprise a silicon nitride layer, and each sacrificial layer 506 may comprise a polysilicon layer. Sacrificial stack layer 504 may be formed using one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, any other suitable deposition process, or any combination thereof.

Although not shown, a stepped structure may be formed on an edge of the sacrificial stack layer 504. The stair-step structure may be formed by performing a plurality of so-called "trim-etch" cycles on each pair of dielectric layers 508 and sacrificial layers 506 of sacrificial stack layer 504 towards substrate 502. Sacrificial stack layer 504 may have one or more beveled edges of dielectric layer 508 and sacrificial layer 506 in a stepped structure due to repeated trim-etch cycles applied to pairs of dielectric layer 508 and sacrificial layer 506.

The method 700 proceeds to operation 706, as shown in fig. 7A, where in operation 706, holes are etched that extend in a vertical direction through the plurality of sacrificial layers and the plurality of dielectric layers and expose the isolation structures. As shown in fig. 5B, each hole 510 is an opening that extends vertically through the interleaved dielectric layers 508 and sacrificial layers 506 of sacrificial stack layer 504, the opening stopping at substrate 502, while leaving isolation structures 514 in hole 510 and exposed after the etching process. In some embodiments, the plurality of apertures 510 are formed such that each aperture 510 becomes a location for forming a separate PCM string in a subsequent process. In some embodiments, as shown in fig. 2A, the isolation structures 214 protrude from the apertures in plan view. That is, the length of isolation structure 214 (i.e., corresponding to isolation structure 514) is longer than the diameter of aperture 510. In this way, the protruding portion of the isolation structure 214 into the stacked layered structure 224 may separate the PCM element 216 into two PCM element portions. In some embodiments, the fabrication process for forming the holes 510 includes wet etching and/or dry etching, e.g., deep rie (drie). According to some embodiments, the etching of the channel hole continues until stopped by the substrate 502. It should be appreciated that one or more of the apertures 510 may extend further into the substrate 502 to some extent, depending on the particular etch selectivity.

The method 700 proceeds to operation 708, as shown in fig. 7A, where portions of each of the plurality of sacrificial layers are replaced with respective ones of the plurality of PCM structures by apertures in operation 708. In some embodiments, to replace portions of each sacrificial layer with a corresponding PCM structure, the plurality of sacrificial layers are etched back through the apertures to form a plurality of recesses, and a plurality of PCM elements are formed in the plurality of recesses through the apertures, respectively. To form the plurality of PCM elements, a PCM layer may be deposited in the plurality of recesses along sidewalls of the hole, and the PCM layer may be etched back to remove portions of the PCM layer along the sidewalls of the hole. The PCM element may include a phase change material.

As shown in fig. 5C, portions of each sacrificial layer 506 are replaced with respective PCM elements 512 through the apertures 510. Sacrificial layer 506 may be etched back using dry etching and/or wet etching to form the recess. A wet etchant having a high selectivity (e.g., greater than 5) to sacrificial layer 506 relative to dielectric layer 508, substrate 502, and isolation structures 514 may be applied into holes 510 to etch sacrificial layer 506. The etch rate and/or etch time may be controlled to partially etch sacrificial layer 506 to form the recess. In some embodiments, a PCM layer (e.g., a phase change material layer (e.g., a chalcogenide-based alloy)) is then deposited through the aperture 510 into the recess and along the sidewalls of the aperture 510 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, any other suitable deposition process, or any combination thereof. The PCM layer may then be etched back using dry etching and/or wet etching to remove portions of the PCM layer along the sidewalls of the holes 510. As a result, the remaining portion of the PCM layer in the recess may become a separate PCM element 512 in the recess, which replaces a portion of the sacrificial layer 506.

The method 700 proceeds to operation 710, as shown in fig. 7A, where in operation 710 a selector layer is deposited along sidewalls and a bottom surface of the hole and sidewalls of the isolation structure. The selector layer may include a threshold switching material. As shown in fig. 5D, the selector layer 518 is deposited along the sidewalls and bottom surface of the hole 510 and the sidewalls of the isolation structure 514 such that the selector layer 518 is in contact with the recessed PCM element 512. The selector layer 518 may be formed by depositing a layer of threshold switch material into the aperture 510 using one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof). Deposition may be performed using conformal deposition techniques (e.g., CVD or ALD) to partially fill the hole 510 along the sidewalls and bottom surface of the hole 510. In one example, a layer of OTS material (e.g., ZnTe, GeTe, NbO, or siaitee) may be deposited as the selector layer 518. In another example, a metal ion reservoir layer comprising Ag, Cu, AgS, CuS, AgSe, CuSe, or any combination thereof and a solid electrolyte layer comprising GeSe, GeS, AgSe, AgS, CuTe, or any combination thereof may be deposited as the selector layer 518.

The method 700 proceeds to operation 712 where, as shown in fig. 7A, a local bit line layer 520' is deposited over the selector layer in the hole in operation 712. As shown in fig. 5E, a local bit line layer 520' is deposited over the selector layer 518 in the hole 510.

The method 700 proceeds to operation 714 where, as shown in fig. 7A, local bit lines 520 are formed by performing a Chemical Mechanical Polishing (CMP) process on a surface of the local bit line layer 520' in operation 714. As shown in fig. 5F, a local bit line layer 520 is formed over the selector layer 518 in the hole 510. In some embodiments, since the isolation structure 514 separates the aperture 510 into two aperture portions, two local bit lines 520 are deposited respectively over two respective selector layers in the two aperture portions. A conductive material (e.g., W) may be deposited over selector layer 518 to fill holes 510 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, any other suitable deposition process, or any combination thereof, followed by a CMP process to form local bit lines 520.

The method 700 proceeds to operation 716, as shown in fig. 7A, where in operation 716, the slot structure extending in a vertical direction through the plurality of sacrificial layers and the plurality of dielectric layers is etched. Similar to hole 510, a slot structure (not shown) may be formed vertically through interleaved sacrificial layers 506 and dielectric layers 508 of sacrificial stack layer 504 using dry etching and/or wet etching (e.g., DRIE).

The method 700 proceeds to operation 718, as shown in fig. 7A, in operation 718, the plurality of sacrificial layers are respectively replaced with a plurality of conductive layers through the slit structure. As shown in fig. 5G, sacrificial layer 506 is removed (e.g., as shown in fig. 5F) to form a plurality of recesses 522 between dielectric layers 508. In some embodiments, a wet etchant with a high selectivity (e.g., higher than 5) to the sacrificial layer 506 relative to the dielectric layer 508 and the PCM elements 512 is applied through the slit structure to etch away the sacrificial layer 506. As shown in fig. 5H, a conductive layer 526 is deposited into the recesses 522 (e.g., as shown in fig. 5G) between the dielectric layers 508. In some embodiments, a conductive material (e.g., W) is deposited through the gap structure using one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof) to fill the recess 522. As a result, stacked layer structure 524 including interleaved conductive layers 526 and dielectric layers 508 may be formed to replace sacrificial stacked layer 504 (e.g., as shown in fig. 5H).

It should be understood that although not shown, in some examples, the stacked layered structure 524 may be formed first before forming the aperture 510. For example, conductive layers 526 and dielectric layers 508 can be alternately deposited on substrate 502 to form stacked layered structure 524, and then holes 510 can be etched through alternating conductive layers 526 and dielectric layers 508 of stacked layered structure 524, as opposed to sacrificial stacked layer 504. The PCM structure may be recessed back into the conductive layer 526 to replace portions of the conductive layer, rather than replacing portions of the sacrificial layer 506. Replacing sacrificial layer 506 with conductive layer 526 may also be omitted.

Fig. 6A-6H illustrate an exemplary fabrication process for forming a 3D PCM device according to some embodiments of the present disclosure. Fig. 7B illustrates a flow diagram of an exemplary method 750 for forming a 3D PCM device according to some embodiments of the present disclosure. Examples of the 3D PCM device depicted in fig. 6A-6H and 7B include the 3D PCM device 300 depicted in fig. 3A-3D. Fig. 3A to 3D, fig. 6A to 6H, and fig. 7B will be described together. It should be understood that the operations shown in method 750 are not exhaustive, and that other operations may be performed before, after, or in between any of the operations shown. Further, some operations may be performed concurrently, or in a different order than shown in fig. 7B.

In some embodiments, to form a 3D memory device, a stacked layer structure including a plurality of conductive layers and a plurality of dielectric layers interleaved is formed on a substrate. A PCM string is formed extending in a vertical direction through the stacked layered structure. Each PCM string may include a plurality of PCM structures separated by isolation structures. From a side view of a cross-section of the 3D memory device, each PCM string comprises a local bitline, a selector layer circumscribing the local bitline, two isolation structures combined with a stacked layer structure circumscribing the selector layer, and a plurality of PCM structures at intersections between the selector layer, the plurality of conductive layers and the isolation structures, respectively, in a lateral direction.

Referring to fig. 7B, the method 750 begins at operation 752 where a sacrificial isolation structure is deposited on a substrate in operation 752. As shown in fig. 6A and 6E, a sacrificial isolation structure 634 is formed on the substrate 602. In some embodiments, the sacrificial isolation structures 634 may be deposited in a stacked layer shape and then etched by a photolithography process to form a pillar shape.

The method 750 proceeds to operation 754 where a plurality of sacrificial layers and a plurality of dielectric layers are alternately deposited on the substrate and around the sacrificial isolation structures, as shown in fig. 7B. As shown in fig. 6A and 6E, dielectric layer 608 and sacrificial layer 606 are alternately deposited on substrate 602 and around sacrificial isolation structure 634 to form sacrificial stack 604. In some embodiments, as shown in fig. 6A, a plurality of sacrificial isolation structures are formed on a substrate, each sacrificial isolation structure being stripe-shaped in plan view. In some embodiments, the dielectric layer 608 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high-k) dielectric, and the sacrificial layer 606 may comprise any suitable material different from the dielectric layer 608. The sacrificial isolation structure 634 may comprise any suitable material, such as silicon oxide, silicon nitride, silicon oxynitride, or other insulating material. In one example, each dielectric layer 608 may include a silicon oxide layer, each sacrificial layer 606 may include a silicon nitride layer, and the sacrificial isolation structures may include silicon oxide. In another example, each dielectric layer 608 may comprise a silicon nitride layer, and each sacrificial layer 606 may comprise a polysilicon layer. Sacrificial stack 604 may be formed using one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, any other suitable deposition process, or any combination thereof.

Although not shown, a stepped structure may be formed on an edge of the sacrificial stack layer 604. The stair-step structure may be formed by performing a plurality of so-called "trim-etch" cycles on each pair of dielectric layers 608 and sacrificial layers 606 of sacrificial stack 604 toward substrate 602. Sacrificial stack layer 604 may have one or more beveled edges of dielectric layer 608 and sacrificial layer 606 in a stepped structure due to repeated trim-etch cycles applied to the pair of dielectric layer 608 and sacrificial layer 606.

The method 750 proceeds to operation 756 where, as shown in fig. 7B, in operation 756, a hole is etched that extends in a vertical direction through the sacrificial isolation structure and portions of the sacrificial isolation structure and exposes sidewalls of the isolation structure and a top surface of the substrate. As shown in fig. 6E and 6F, each hole 610 is an opening that extends vertically through the sacrificial isolation structure 634, the opening stopping at the substrate 602 while leaving the isolation structure 636 in the hole 610, and exposing sidewalls of the isolation structure 636 after the etching process. In some embodiments, as shown in fig. 6F, a plurality of apertures 610 are formed such that each aperture 610 becomes a location for forming a separate PCM string in a subsequent process. In some embodiments, as shown in fig. 3A, the isolation structures 336 are located outside of the holes in plan view and embedded in the sacrificial structure stack layers. In some embodiments, the fabrication process for forming the holes 610 includes wet etching and/or dry etching, e.g., deep rie (drie). According to some embodiments, the etching of the channel hole continues until stopped by the substrate 602. It should be appreciated that one or more of the apertures 610 may extend further into the substrate 602 to some extent, depending on the particular etch selectivity.

The method 750 proceeds to operation 758, as shown in fig. 7B, where portions of each of the plurality of sacrificial layers are replaced with respective ones of the plurality of PCM structures by apertures in operation 758. In some embodiments, to replace portions of each sacrificial layer with corresponding PCM structures, the plurality of sacrificial layers are etched back through the apertures to form a plurality of recesses, and the plurality of PCM structures are formed in the plurality of recesses through the apertures, respectively, except for those portions blocked by the isolation structures. To form a plurality of PCM structures, a PCM layer may be deposited in the plurality of recesses along sidewalls of the hole, and the PCM layer may be etched back to remove portions of the PCM layer along the sidewalls of the hole. The PCM structure may include a phase change material.

After the isolation structures 636 are formed, portions of each sacrificial layer 606 are replaced with a corresponding PCM structure 312 (e.g., in fig. 3B) through the apertures 610. To replace the sacrificial layer with a PCM structure, the sacrificial layer 606 may be etched back using dry etching and/or wet etching to form the recess. A wet etchant having a high selectivity (e.g., greater than 5) to the sacrificial layer 606 relative to the dielectric layer 608, the substrate 602, and the isolation structures 636 may be introduced into the holes 610 to etch the sacrificial layer 606. The etch rate and/or etch time may be controlled to partially etch the sacrificial layer 606 to form the recess. In some embodiments, a PCM layer (e.g., a phase change material layer (e.g., a chalcogenide-based alloy)) is then deposited through the aperture 610 into the recess and along the sidewalls of the aperture 610 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, any other suitable deposition process, or any combination thereof. The PCM layer may then be etched back using dry etching and/or wet etching to remove portions of the PCM layer along the sidewalls of the holes 610. As a result, the remaining portion of the PCM layer in the recess may become a separate PCM structure 312 (e.g., in fig. 3B) in the recess, which replaces a portion of the sacrificial layer 606.

The method 750 proceeds to operation 760 and, as shown in fig. 7B, in operation 760, a selector layer is deposited along sidewalls and a bottom surface of the hole, including sidewalls of the isolation structures, sidewalls of the sacrificial structures, and a top surface of the substrate. The selector layer may include a threshold switching material. As shown in fig. 3B, the selector layer 318 is deposited along the sidewalls of the stacked layered structure 324 and the top surface of the substrate 302 such that the selector layer 318 is in contact with the recessed PCM structure 312. As shown in fig. 3C, a selector layer 318 is also deposited along the sidewalls of the isolation structures 336. The selector layer 318 can be formed by depositing a layer of threshold switch material into the apertures using one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof). The deposition may be performed using a conformal deposition technique (e.g., CVD or ALD) to partially fill the hole along its sidewalls and bottom surface. In one example, a layer of OTS material (e.g., ZnTe, GeTe, NbO, or siaitee) may be deposited as the selector layer 318. In another example, a metal ion reservoir layer comprising Ag, Cu, AgS, CuS, AgSe, CuSe, or any combination thereof and a solid electrolyte layer comprising GeSe, GeS, AgSe, AgS, CuTe, or any combination thereof may be deposited as selector layer 318.

The method 750 proceeds to operation 762 where, as shown in fig. 7B, local bit lines are deposited over the selector layer in the holes in operation 762. As shown in the cross section of fig. 6G (and in fig. 3C), local bit lines 631 are deposited over the sidewalls of the isolation structures 636. From another cross-section as shown in fig. 3B, local bit lines 331 (e.g., corresponding to local bit lines 631 in fig. 6G) are also deposited over selector layer 318. In some embodiments, the isolation structure 336 in fig. 3C separates the PCM structure 312 in fig. 3B into two PCM structure portions in a lateral direction. A conductive material (e.g., W) may be deposited over selector layer 318 using one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof) to fill the holes, followed by a CMP process to form local bit lines 331. In some embodiments, global bit line 333 is formed on local bit line 331.

The method 750 proceeds to operation 764, where, as shown in fig. 7B, the slot structure extending in a vertical direction through the plurality of sacrificial layers and the plurality of dielectric layers is etched in operation 764. As shown in fig. 6H, similar to hole 610 (e.g., in fig. 6F), a slot structure 605 of interleaved sacrificial layers 606 (e.g., in fig. 6G) and dielectric layers 608 (e.g., in fig. 6G) vertically through sacrificial stack 604 (e.g., in fig. 6G) may be formed using dry etching and/or wet etching (e.g., DRIE) to remove portions of sacrificial stack 604. In some embodiments, a plurality of slot structures 605 (e.g., corresponding to slot structures 305 in fig. 3A and 3C) are formed between two adjacent isolation structures of two respective PCM strings in the x-direction. As shown in the plan view of fig. 3A, these slit structures laterally connecting all adjacent PCM strings define fingers. In some embodiments, the slot structure is perpendicular to the global bit line. In some embodiments, the slot structure has the same or similar width as compared to the isolation structure.

The method 750 proceeds to operation 766 where, as shown in fig. 7B, the plurality of sacrificial layers are replaced with a plurality of conductive layers, respectively, by a slit structure in operation 766. Sacrificial layer 606 (shown in figure 6G) is removed to form a plurality of recesses between the dielectric layers. In some embodiments, a wet etchant with high selectivity (e.g., higher than 5) to the sacrificial layer 606 relative to the dielectric layer 608 and the PCM structure 312 (e.g., in fig. 3B) is applied through the slit structure to etch away the sacrificial layer 606. After the etching process, as shown in fig. 3B, a conductive layer 326 is deposited into the recesses between the dielectric layers 308. In some embodiments, a conductive material (e.g., W) is deposited through the gap structure using one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof) to fill the recess. As a result, stacked layered structure 324 comprising interleaved conductive layers 326 and dielectric layers 308 may be formed in place of sacrificial stacked layer 604 as shown in FIG. 6G.

It should be understood that although not shown, in some examples, stacked layered structure 324 may be formed first before forming apertures 610 (e.g., shown in fig. 6F). For example, conductive layers 326 and dielectric layers 308 may be alternately deposited on substrate 302 to form stacked layered structure 324, and then holes may be etched through interleaved conductive layers 326 and dielectric layers 308 of stacked layered structure 324, as opposed to sacrificial stacked layer 604 (e.g., shown in fig. 6F). The PCM structure may be recessed back into the conductive layer 326 to replace portions of the conductive layer, rather than replacing portions of the sacrificial layer 606. Replacing sacrificial layer 606 with conductive layer 326 may also be omitted.

According to one aspect of the present disclosure, a three-dimensional (3D) memory device includes: a stacked layer structure including a plurality of word line layers and a plurality of dielectric layers which are staggered; and a plurality of Phase Change Memory (PCM) strings, each of the PCM strings extending through the stacked layer structure in a first direction and including: an isolation structure extending through the stacked layer structure in a first direction; and a plurality of PCM string portions separated by isolation structures, each PCM string portion including a local bitline, a selector layer interfacing the local bitline, and a plurality of PCM structures between the selector layer and the plurality of wordline layers.

In some embodiments, the isolation structure extends in a second direction to separate the plurality of PCM string portions, wherein the second direction is perpendicular to the first direction.

In some embodiments, the isolation structure includes a stripe shape in a plan view, and the number of the plurality of PCM string portions is two.

In some embodiments, the isolation structure includes a cross shape in a plan view, and the number of the plurality of PCM string portions is four.

In some embodiments, the 3D memory device further includes global bit lines extending in the second direction and contacting the respective local bit lines.

In some embodiments, the 3D memory device further includes one or more slit structures extending through the stacked layer structure in the first direction to separate each of the plurality of word line layers into a plurality of word lines.

In some embodiments, the 3D memory device further includes fingers defined by two adjacent slot structures, each global bitline in contact with a respective PCM string portion in each finger.

In some embodiments, the selector layer includes a threshold switching material.

In some embodiments, the plurality of PCM structures are separated by a plurality of dielectric layers in the first direction.

In some embodiments, each of the plurality of PCM structures includes a PCM element.

In some implementations, the PCM element includes a phase change material.

In some embodiments, the material of the isolation structure includes silicon oxide, silicon nitride, silicon oxynitride, or other insulating material.

According to another aspect of the present disclosure, a three-dimensional (3D) memory device includes: a stacked layer structure including a plurality of word line layers and a plurality of dielectric layers which are staggered; and a plurality of Phase Change Memory (PCM) strings, each of the PCM strings extending through the stacked layer structure in a first direction and including: local bit lines extending in a first direction; a selector layer, the selector layer external to the local bit line; a plurality of isolation structures extending in a first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and a plurality of PCM structures between the selector layer and the plurality of wordline layers in the second direction, each of the plurality of PCM structures between two of the plurality of isolation structures in the second direction.

In some embodiments, the 3D memory device further includes one or more slot structures, each slot structure formed between two isolation structures of two respective PCM strings.

In some embodiments, the 3D memory device further includes fingers defined by two adjacent slot structures, and the global bitline is in contact with a respective PCM string in each finger.

In some embodiments, each slot structure is filled with an insulating material.

According to another aspect of the disclosure, a system comprises: a three-dimensional (3D) memory device configured to store data, the 3D memory device comprising: a stacked layer structure including a plurality of word line layers and a plurality of dielectric layers which are staggered; and a plurality of Phase Change Memory (PCM) strings, each of the PCM strings extending through the stacked layer structure in a first direction and including: an isolation structure extending through the stacked layer structure in a first direction; and a plurality of PCM string portions separated by isolation structures, each PCM string portion comprising a local bitline, a selector layer interfacing the local bitline, and a plurality of PCM structures between the selector layer and the plurality of wordline layers; and a memory controller coupled to the 3D memory device and configured to control operation of the plurality of PCM cells through the local bit lines and the plurality of word lines.

According to another aspect of the disclosure, a system comprises: a three-dimensional (3D) memory device configured to store data, the 3D memory device comprising: a stacked layer structure including a plurality of word line layers and a plurality of dielectric layers which are staggered; and a plurality of Phase Change Memory (PCM) strings, each of the PCM strings extending through the stacked layer structure in a first direction and including: local bit lines extending in a first direction; a selector layer, the selector layer external to the local bit line; a plurality of isolation structures extending in a first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and a plurality of PCM structures between the selector layer and the plurality of wordline layers in the second direction, each of the plurality of PCM structures between two of the plurality of isolation structures in the second direction; and a memory controller coupled to the 3D memory device and configured to control operation of the plurality of PCM cells through the local bit lines and the plurality of word lines.

According to yet another aspect of the present disclosure, a method for forming a three-dimensional (3D) memory device includes: : forming a stacked layer structure on a substrate, the stacked layer structure including a plurality of conductive layers and a plurality of dielectric layers which are interleaved; and forming a Phase Change Memory (PCM) string extending through the stacked layer structure in a first direction, wherein the PCM string comprises: an isolation structure extending through the stacked layer structure in a first direction; a plurality of PCM string portions separated by isolation structures, each PCM string portion comprising: a local bit line structure extending in a first direction; a selector layer, which is externally connected with the corresponding local bit line; and a plurality of PCM structures between the selector layer and the plurality of conductive layers, respectively.

In some embodiments, forming the stacked layered structure comprises: alternately depositing a plurality of sacrificial layers and a plurality of dielectric layers on a substrate; etching a slit structure extending in a first direction through the plurality of sacrificial layers and the plurality of dielectric layers; and replacing the plurality of sacrificial layers with the plurality of conductive layers through the slits, respectively.

In some embodiments, forming the PCM string comprises: forming an isolation structure on a substrate; etching a plurality of holes extending through the plurality of sacrificial layers and the plurality of dielectric layers to expose the isolation structures; replacing portions of each of the plurality of sacrificial layers with respective ones of the plurality of PCM structures through the holes; depositing a plurality of selector layers along respective sidewalls and bottom surfaces of the plurality of holes; and depositing a plurality of local bit lines over the respective selector layers in the plurality of holes.

In some embodiments, replacing portions of each sacrificial layer with a respective PCM structure comprises: etching back the plurality of sacrificial layers through each of the holes to form a plurality of recesses; and forming a corresponding PCM structure of the plurality of PCM structures in the plurality of recesses through each of the holes, respectively.

In some embodiments, forming a plurality of PCM structures comprises: depositing a PCM layer in the plurality of recesses and along sidewalls of the hole; and etching back the PCM layer to remove portions of the PCM layer along sidewalls of the hole.

In some embodiments, the PCM structure includes a phase change material.

In some embodiments, the method further includes forming a global bit line extending over and in contact with the local bit line.

According to yet another aspect of the present disclosure, a method for forming a three-dimensional (3D) memory device includes: forming a stacked layer structure on a substrate, the stacked layer structure including a plurality of conductive layers and a plurality of dielectric layers which are interleaved; and forming a plurality of Phase Change Memory (PCM) strings extending through the stacked layer structure in a first direction, each PCM string comprising: local bit lines extending in a first direction; a selector layer, the selector layer external to the local bit line; a plurality of isolation structures extending in a first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and a plurality of PCM structures between the selector layer and the plurality of conductive layers in the second direction, the plurality of PCM structures being between two of the plurality of isolation structures in the second direction.

In some embodiments, forming the stacked layered structure comprises: alternately depositing a plurality of sacrificial layers and a plurality of dielectric layers on a substrate; etching a plurality of slit structures extending in a first direction through the plurality of sacrificial layers and the plurality of dielectric layers, each slit structure being respectively formed between two of the plurality of isolation structures of two adjacent PCM strings; and replacing the plurality of sacrificial layers with the plurality of conductive layers, respectively, through the slit structure.

In some embodiments, forming the plurality of PCM strings comprises: forming a plurality of sacrificial isolation structures on a substrate; etching a plurality of holes extending through portions of each of the plurality of sacrificial layers, the plurality of dielectric layers, and the plurality of sacrificial isolation structures to form a plurality of isolation structures; replacing portions of each of the plurality of sacrificial layers with respective ones of the plurality of PCM structures through the holes; depositing a plurality of selector layers along respective sidewalls and bottom surfaces of the plurality of holes; and depositing a plurality of local bit lines over the respective selector layers in the plurality of holes.

In some embodiments, the method further includes forming a plurality of global bit lines extending over and in contact with the respective local bit lines.

In some embodiments, the plurality of slot structures are perpendicular to the plurality of global bit lines.

The foregoing description of the specific embodiments will so reveal the general nature of the disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

The foregoing description of the specific embodiments may be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device, comprising:

a stacked layer structure including a plurality of word line layers and a plurality of dielectric layers that are interleaved; and

a plurality of Phase Change Memory (PCM) strings, each of the PCM strings extending through the stacked layer structure in a first direction and comprising:

an isolation structure extending through the stacked layer structure in the first direction; and

a plurality of PCM string portions separated by the isolation structures, each PCM string portion comprising a local bitline, a selector layer interfacing the local bitline, and a plurality of PCM structures between the selector layer and the plurality of wordline layers.

2. The 3D memory device of claim 1, wherein the isolation structures extend in a second direction to separate the plurality of PCM string portions, wherein the second direction is perpendicular to the first direction.

3. The 3D memory device of claim 1 or 2, wherein the isolation structure comprises a stripe shape in plan view and the number of the plurality of PCM string portions is two.

4. The 3D memory device of claim 1 or 2, wherein the isolation structure comprises a cross shape in plan view and the number of the plurality of PCM string portions is four.

5. The 3D memory device of any of claims 2-4, further comprising global bit lines extending in the second direction and contacting respective local bit lines.

6. The 3D memory device of any of claims 1-5, further comprising one or more slot structures extending through the stacked layer structure in the first direction to separate each of the plurality of word line layers into a plurality of word lines.

7. The 3D memory device of claim 6, further comprising fingers defined by two adjacent slot structures, each global bitline in contact with a respective PCM string portion in each finger.

8. The 3D memory device of any of claims 1-7, wherein the selector layer comprises a threshold switching material.

9. The 3D memory device of any of claims 1-8, wherein the plurality of PCM structures are separated by the plurality of dielectric layers in the first direction.

10. The 3D memory device of any of claims 1-9, wherein each of the plurality of PCM structures comprises a PCM element.

11. The 3D memory device of claim 10, wherein the PCM element comprises a phase change material.

12. The 3D memory device of any of claims 1-11, wherein the material of the isolation structure comprises silicon oxide, silicon nitride, silicon oxynitride, or other insulating material.

13. A three-dimensional (3D) memory device, comprising:

local bit lines extending in the first direction;

a selector layer that interfaces the local bit lines;

a plurality of isolation structures extending in the first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and

a plurality of PCM structures between the selector layer and the plurality of word line layers in the second direction, each of the plurality of PCM structures between two of the plurality of isolation structures in the second direction.

14. The 3D memory device of claim 13, further comprising one or more slot structures, each slot structure formed between two isolation structures of two respective PCM strings.

15. The 3D memory device of claim 14, further comprising global bit lines extending in the second direction and contacting respective local bit lines.

16. The 3D memory device of claim 15, further comprising fingers defined by two adjacent slot structures, wherein the global bitline is in contact with a respective PCM string in each finger.

17. The 3D memory device of any of claims 14-16, wherein each slot structure is filled with an insulating material.

18. A system, comprising:

a three-dimensional (3D) memory device configured to store data, the 3D memory device comprising:

a plurality of PCM string portions separated by the isolation structures, each PCM string portion comprising a local bitline, a selector layer interfacing the local bitline, and a plurality of PCM structures between the selector layer and the plurality of wordline layers; and

a memory controller coupled to the 3D memory device and configured to control operation of the plurality of PCM cells through the local bit lines and the plurality of word lines.

19. A system, comprising:

local bit lines extending in the first direction;

a selector layer that interfaces the local bit lines;

a plurality of PCM structures between the selector layer and the plurality of word line layers in the second direction, each of the plurality of PCM structures between two of the plurality of isolation structures in the second direction; and

20. A method for forming a three-dimensional (3D) memory device, comprising:

forming a stacked layer structure on a substrate, the stacked layer structure including a plurality of conductive layers and a plurality of dielectric layers interleaved; and

forming a plurality of Phase Change Memory (PCM) strings extending through the stacked layer structure in a first direction, each PCM string comprising:

an isolation structure extending through the stacked layer structure in the first direction;

a plurality of PCM string portions separated by the isolation structure, each PCM string portion comprising:

a local bit line structure extending in the first direction;

a selector layer external to a corresponding local bit line; and

a plurality of PCM structures between the selector layer and the plurality of conductive layers, respectively.

21. The method of claim 20, wherein forming the stacked layered structure comprises:

depositing a plurality of sacrificial layers and the plurality of dielectric layers alternately on the substrate;

etching a slot structure extending through the plurality of sacrificial layers and the plurality of dielectric layers in the first direction; and

replacing the plurality of sacrificial layers with the plurality of conductive layers, respectively, through the slit structures.

22. The method of claim 21, wherein forming the plurality of PCM strings comprises:

forming an isolation structure on the substrate;

etching a plurality of holes extending through the plurality of sacrificial layers and the plurality of dielectric layers to expose the isolation structures;

replacing a portion of each of the plurality of sacrificial layers with a respective PCM structure of the plurality of PCM structures through the hole;

depositing a plurality of selector layers along respective sidewalls and bottom surfaces of the plurality of holes; and

depositing a plurality of local bit lines over respective selector layers in the plurality of holes.

23. The method of claim 22, wherein replacing the portion of each sacrificial layer with the respective PCM structure comprises:

etching back the plurality of sacrificial layers through each hole to form a plurality of recesses; and

forming the respective PCM structure of the plurality of PCM structures in the plurality of recesses through each hole, respectively.

24. The method of claim 23, wherein forming the plurality of PCM structures comprises:

depositing a PCM layer in the plurality of recesses and along sidewalls of the hole; and

etching back the PCM layer to remove portions of the PCM layer along the sidewalls of the hole.

25. The method of claim 23 or 24, wherein the PCM structure comprises a phase change material.

26. The method of any of claims 20-25, wherein the selector layer comprises a threshold switching material.

27. The method of any of claims 20-26, further comprising forming a plurality of global bit lines extending over and in contact with the respective local bit lines.

28. A method for forming a three-dimensional (3D) memory device, comprising:

local bit lines extending in the first direction;

a selector layer that interfaces the local bit lines;

a plurality of PCM structures between the selector layer and the plurality of conductive layers in the second direction, the plurality of PCM structures between two of the plurality of isolation structures in the second direction.

29. The method of claim 28, wherein forming the stacked layered structure comprises:

etching a plurality of slit structures extending in the first direction through the plurality of sacrificial layers and the plurality of dielectric layers, each slit structure being respectively formed between two of the plurality of isolation structures of two adjacent PCM strings; and

30. The method of claim 29, wherein forming the plurality of PCM strings comprises:

forming a plurality of sacrificial isolation structures on the substrate;

etching a plurality of holes extending through portions of the plurality of sacrificial layers, the plurality of dielectric layers, and each of the plurality of sacrificial isolation structures to form the plurality of isolation structures;

31. The method of claim 30, wherein replacing the portion of each sacrificial layer with the respective PCM structure comprises:

32. The method of claim 31, wherein forming the plurality of PCM structures comprises:

33. The method of any of claims 28-32, further comprising forming a plurality of global bit lines extending over and in contact with the respective local bit lines.

34. The method of claim 33, wherein the plurality of slot structures are perpendicular to the plurality of global bit lines.