CN112567525A

CN112567525A - Novel vertical 3D PCM memory cell and program read scheme

Info

Publication number: CN112567525A
Application number: CN202080003468.XA
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-11-18
Filing date: 2020-11-18
Publication date: 2021-03-26
Anticipated expiration: 2040-11-18
Also published as: WO2022104591A1; CN112567525B

Abstract

Three-dimensional memory architectures with novel vertical 3D Phase Change Material (PCM) memory cells and programming/reading schemes are disclosed. This approach provides lower cost and other benefits. In the proposed integration scheme for vertical 3D x-point memory, word lines are all formed with the replacement metal, and local bit lines are all formed vertically perpendicular to the word lines, where global bit lines connect the local bit lines in different pages. The PCM cells are formed in the recesses of the word lines while an Ovonic Threshold Switch (OTS) film is deposited as a continuous film (due to its insulator properties). This vertical 3D X-point provides a more flexible approach to scaling and cost reduction than the conventional stacked 3D x-point architecture. Various embodiments of cell array architectures are also presented.

Description

Novel vertical 3D PCM memory cell and program read scheme

Technical Field

The present disclosure relates generally to three-dimensional electronic memories and, more particularly, to forming improved memory architectures having several advantages over current self-aligned dual-imaging (SADP) semiconductors.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the feature size of memory cells approaches the lower limit, planarization processes and fabrication techniques become challenging and costly. As such, the storage density of planar memory cells approaches an upper limit. Three-dimensional (3D) memory architectures can address density limitations in planar memory cells.

Phase Change Memory (PCM) is a non-volatile solid-state storage technology that utilizes reversible, thermally-assisted switching of a phase change material (a chalcogenic compound, such as GST (germanium antimony tellurium)) between states having different resistances. The basic memory cell (cell) can be programmed into a plurality of different states or levels exhibiting different resistance characteristics. Programmable cell states can be used to represent different data values, allowing the storage of information.

PCM cells are programmed or erased by self-heating of heat to induce an amorphous or crystalline state to represent a 1 or 0. The programming current is proportional to the size and cross-sectional area of the PCM cell. In a single level PCM device, each cell may be SET to one of two states, namely "SET" and "RESET", allowing one bit to be stored per cell. In the RESET state, which corresponds to a completely amorphous state of the phase change material, the resistance of the cell is very high. By heating to a temperature above the crystallization point of the phase change material and then cooling, the phase change material can be transformed into a fully crystalline state of low resistance. The low resistance state provides the SET state of the cell. If the cell is then heated to a high temperature above the melting point of the phase change material, the material reverts to a fully amorphous RESET state upon rapid cooling.

In addition, large programming current requirements also introduce large programming voltage requirements. Reading and writing of data within PCM cells is accomplished by applying appropriate voltages to the phase change material through a pair of electrodes associated with each cell. During a write operation, the generated programming signal causes joule heating of the phase change material to an appropriate temperature, causing the desired cell state when cooled. Reading of a PCM cell is performed using the cell resistance as a measure of the cell state. The applied read voltage causes a current to flow through the cell.

The current depends on the resistance of the cell. Thus, measurement of the cell current provides an indication of the programmed cell state. A sufficiently low read voltage is used for this resistance measurement to ensure that the application of the read voltage does not disturb the programmed cell state. Cell state detection may then be performed by comparing the resistance metric to a predefined reference level. The programming current (I) is typically about 100-200 μ A. This voltage drop may be significant if the Write Line (WL) and Bit Line (BL) in the cell encounter large resistances.

In a commercial 3D X-point memory, the bit lines and word lines are formed of tungsten (W) having a relatively high resistivity. A memory chip consists of many small memory arrays (tiles) and is at risk of large voltage drops occurring on word lines and bit lines during programming operations. The voltage drop due to the word line and bit line resistances will cause the memory cell to experience different programming currents, which may result in over-programming or under-programming along the word line and bit line. Furthermore, tungsten resistivity increases rapidly with smaller critical dimensions or CDs due to electron scattering at the surface and grain boundaries.

In a commercial 3D x-point memory, WL and BL are formed from 20nm/20nm L/S images. The memory cell is formed at the intersection of the vertical WL and BL. Two stacked layers of WL/BL/memory cells are stacked to increase bit density. Typically, in current commercial 3D x-point memories, the memory cells are first formed by imaging out both the BL and WL to define the bottom pillar memory cells. The formation of the pillar memory cells is then followed by top cell stack layer deposition and BL/WL imaging to define the top pillar memory cells. Each stack layer is formed using two self-aligned dual imaging (SADP) imaging steps. SADP is a form of dual imaging. This is sometimes referred to as compartmentalization, spacer or sidewall assisted dual imaging. Further scaling of the semiconductor will add more stacked layers on top to reduce cost. However, due to the high cost associated with additional SADP imaging for each stacked layer, the cost benefit will be reduced.

Therefore, there is a need in the art for a stack of memory cells that will minimize the cost associated with additional SADP imaging for each stack layer and still increase memory size. There is also a need in the art for a new cell architecture that is low cost and provides additional benefits to replace the additional SADP imaging for each storage stack layer.

Disclosure of Invention

The following summary is included to provide a basic understanding of various aspects and features of the disclosure. This summary is not an extensive overview, and as such it is not intended to specifically identify key or critical elements or to delineate the scope of the disclosure. Its sole purpose is to present concepts in a simplified form.

In one aspect, a novel vertical 3D PCM memory stack is disclosed. A plurality of metals WL are stacked one on top of the other and separated by dielectric layers. Each stack layer is composed of horizontal word lines and vertical bit lines perpendicular to each other. The memory cells are self-aligned to the word lines and bit lines.

In one aspect, a novel vertical 3D X-Point memory cell is disclosed. The memory cells are formed as horizontal cells between mutually perpendicular word lines and bit lines. Depending on the implementation, the memory cells are formed in the recesses.

In another aspect, a method for forming a novel 3D X-Point memory stack layer is disclosed. The method comprises the following steps: depositing a plurality of nitride layer/polysilicon (Ni/Poly Si or Poly) layer stacks; forming a circular hole through the stacked layers; recessing polysilicon (poly) to form a Phase Change Material (PCM) memory in the recess; depositing an Ovonic Threshold Switch (OTS) and a metallic material to form a vertical bit line; forming parallel lines of a cut oxide/nitride (ox/nit) stack perpendicular to the previously formed line segments; and removing the polysilicon and backfilling with metal to form the word line.

A vertical 3-D PCM architecture is also disclosed. The architecture has each finger storage area consisting of eight or six channel holes and/or six to eight holes. The finger storage areas are separated by gate gaps. Each vertical local bit line is connected to a different global bit line in the finger storage region.

In another aspect, a three-dimensional memory architecture with a novel vertical 3D Phase Change Material (PCM) memory cell and programming/reading scheme is disclosed. This approach provides lower cost and other benefits. In the proposed integration scheme for vertical 3D x-point memory, word lines are all formed with the replacement metal, and local bit lines are all formed vertically perpendicular to the word lines, where global bit lines connect the local bit lines in different pages. The PCM cells are formed in the recesses of the word lines while an Ovonic Threshold Switch (OTS) film is deposited as a continuous film (due to its insulator properties). This vertical 3D X-point provides a more flexible approach to scaling and cost reduction than the conventional stacked 3D x-point architecture. Various embodiments of cell array architectures are also presented. Additional benefits of the novel architecture include, but are not limited to: the replacement of the WL does not require additional self-aligned dual imaging (SADP) which may increase production costs. Another benefit is shared WLs and BLs between adjacent memory cells, and lower WL and BL resistance due to the shared WLs and BLs. Furthermore, there is no misalignment problem between different stacked layers. The novel architecture has a high degree of scalability to more stacked layers without the need to add photolithography steps. The novel technology can be extended to other resistive memory technologies. These and other benefits are possible through the emerging technology disclosed.

According to one aspect, a three-dimensional memory cell structure includes at least one memory cell stack layer having a selector, a phase change memory cell, and first and second electrodes. The phase change memory cell is disposed between the first electrode and the second electrode. Each memory cell stack has word lines and bit lines that are perpendicular to each other and coupled to the memory cell stack. The memory cell stack is self-aligned with respect to the word lines and bit lines. The word lines and bit lines are formed with self-aligned metal for improved programming and increased array size. Depending on the implementation, the metal is tungsten or other metal.

According to an aspect, a method of forming a three-dimensional memory further comprises: forming a plurality of nitride/polysilicon stack layers; forming holes in the stack for subsequent cell and bit line definition; and recessing the polysilicon and then filling the recess with PCM material, followed by dry or wet etch back. Depending on the embodiment, filling the recesses includes using only PCM material, using carbon and PCM material, or using carbon and PCM material and carbon material. The filling of the recesses may be done in an ordered sequence, wherein the material order listed previously is the order of filling of the recesses. Furthermore, the recess may form a pocket unit for filling of the above-mentioned material. The method further comprises the following steps: depositing an OTS material as a selector; depositing tungsten (W) or other metal followed by chemical mechanical polishing or planarization (CMP) to form local bit lines; forming a cut in the stack of layers and removing the polysilicon oxide using a wet etch; and gap filling with WL metal to form WL. Depending on the implementation, a gap fill with atomic layer deposited oxide, spin-on dielectric, or flowable chemical vapor deposited oxide is applied to the cell stack layer. Depending on the implementation, CMP with oxide and/or nitride compounds may or may not be applied to the cell stack layer.

Drawings

The foregoing aspects, features and advantages of the present disclosure will be further understood when considered in conjunction with the following description of exemplary embodiments and the accompanying drawings, wherein like reference numerals denote like elements. In the description of the exemplary embodiments of the present disclosure, specific terminology may be used for the sake of clarity.

However, aspects of the present disclosure are not intended to be limited to the specific terminology used.

Fig. 1A and 1B are isometric views of a prior art three-dimensional cross-point memory.

Fig. 2A, 2B-1, 2B-2, and 2C are illustrations of a section of a three-dimensional cross-point memory showing the formation of multiple nitride/poly stack layers, forming holes in the stack layers, and fig. 2C is an illustration showing a simplified representation of the layers in the cell stack layers.

Fig. 3A and 3B are plan views of a three-dimensional cross-point memory according to the embodiment of fig. 2A-2C, showing filling of the recesses with Phase Change Material (PCM) and deposition of an Ovonic Threshold Switch (OTS) material as a selector, respectively.

Fig. 4A and 4B are plan views of a three-dimensional cross-point memory according to the embodiment of fig. 3A and 3B, respectively, showing metal deposition followed by chemical mechanical planarization or grinding (CMP) to form local bit lines, and notching and removal of polysilicon dioxide (poly-Si) in the stacked layers.

Fig. 5 is a plan view of a three-dimensional cross-point memory according to the embodiment of fig. 4A and 4B, showing the formation of Write Lines (WL).

Fig. 6A is a plan view of a three-dimensional cross-point memory according to the embodiment of fig. 5 and shows that each Global Bit Line (GBL) is connected to a separate Local Bit Line (LBL) in each page and multiple LBLs in multiple pages, and fig. 6B is a schematic diagram showing the array architecture of fig. 6A.

Fig. 7A is a plan view of a three-dimensional cross-point memory according to the embodiment of fig. 6A-6B and showing Global Bit Lines (GBL) and Local Bit Lines (LBL) and Word Lines (WL) of a selected cell with voltage biasing, and fig. 7B is a schematic diagram showing the cell biasing architecture of fig. 7A.

Fig. 8A is a plan view of a three-dimensional cross-point memory according to another embodiment and showing that each Global Bit Line (GBL) is connected to a separate Local Bit Line (LBL) in each page and a plurality of LBLs in a plurality of pages, and fig. 8B is a schematic diagram showing the array architecture of fig. 8A.

Fig. 9A is a plan view of a three-dimensional cross-point memory according to another embodiment and shows that each Global Bit Line (GBL) is connected to a separate Local Bit Line (LBL) in each page and a plurality of LBLs in a plurality of pages, and fig. 9B is a schematic diagram showing the array architecture of fig. 9A.

Fig. 10A, 10B, and 10C are illustrations of another embodiment of a section of a three-dimensional cross-point memory showing the formation of multiple nitride/poly stack layers, forming holes in the stack layers, and fig. 2C still serves as an illustration showing a simplified representation of the layers in the cell stack layer.

Fig. 11A and 11B are plan views of a three-dimensional cross-point memory according to the embodiment of fig. 10A-10C, respectively showing recessing of polysilicon dioxide (polysilicon) and then filling the recess with Phase Change Material (PCM), and depositing an Ovonic Threshold Switch (OTS) material as a selector.

Fig. 12 is a plan view of a three-dimensional cross-point memory according to the embodiment of fig. 11A and 11B, showing deposition of metal followed by chemical mechanical planarization or grinding (CMP) to form local bit lines, and forming cuts and removal of polysilicon dioxide (poly-Si) in the stack, and showing the formation of Write Lines (WL), respectively.

Fig. 13A, 13B, and 13C are illustrations of another embodiment of a section of a three-dimensional cross-point memory showing the formation of multiple nitride/poly stack layers, forming holes in the stack layers, and fig. 2C still serves as an illustration showing a simplified representation of the layers in the cell stack layer.

Fig. 14A and 14B are plan views of a three-dimensional cross-point memory according to the embodiment of fig. 13A-13C, respectively showing recessing of polysilicon dioxide (polysilicon) and then filling the recess with Phase Change Material (PCM), and depositing an Ovonic Threshold Switch (OTS) material as a selector.

Fig. 15 is a plan view of a three-dimensional cross-point memory according to the embodiment of fig. 14A and 14B, showing deposition of metal followed by chemical mechanical planarization or grinding (CMP) to form local bit lines, and forming cuts and removal of polysilicon dioxide (poly-Si) in the stack, and showing the formation of Write Lines (WL), respectively.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that the discussion is made for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure may also be employed in a variety of other applications.

It is noted that references in this specification to "one embodiment," "an example embodiment," "some embodiments," etc., merely indicate that the embodiment described may include a particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms should be understood based at least in part on the context in which they are used. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, based at least in part on the context. Similarly, the terms "a," "an," or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context.

It should be readily understood that the meaning of "on … …," "over … …," and "over … …" in this disclosure should be interpreted in the broadest manner such that "on … …" means not only directly on something, but also includes the meaning of being on something with intervening features or layers therebetween, and "over … …" or "over … …" means not only over or on something, but also includes the meaning of being on or over something with no intervening features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's illustrated relationship to another element or feature. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and, as such, the spatially relative descriptors used herein may be interpreted accordingly.

The term "substrate" as used herein may refer to any workpiece on which it is desired to form or process a layer of material. Non-limiting examples include silicon, germanium, silicon dioxide, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, spinel, silicon-on-oxide carbide, gallium nitride, indium nitride, aluminum nitride, glass, polycrystalline silicon dioxide, combinations or alloys thereof, and other solid state materials. The substrate itself can be imaged. The material added on top of the substrate may be imaged or may remain unimaged. In addition, the substrate may comprise a wide range of semiconductor materials including, but not limited to, silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be formed of a non-conductive material, such as glass, plastic, or sapphire wafers.

The term "layer" as used herein refers to a portion of material that includes a region having a thickness. A layer may extend over the entire underlying or overlying structure or may have a smaller extent than the underlying or overlying structure. Further, a layer may be a region of a continuous structure, uniform or non-uniform, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of the continuous structure, or at the top and bottom surfaces. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

The term "horizontal" as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, taking into account the orientation of the substrate. The term "vertical" will refer to a direction perpendicular to "horizontal" as previously defined. Terms such as "above … …," "below … …," "bottom," "top," "side" (e.g., sidewall), "higher," "lower," "upper," "above … …," and "below … …" are defined with respect to the horizontal plane. The term "on … …" means that there is direct contact between the elements. The term "above … …" will allow for the presence of intervening elements.

As used herein, a material (e.g., a dielectric material or an electrode material) will be considered "crystalline" if the material exhibits a crystallinity of greater than or equal to 30% as measured by a technique such as x-ray diffraction (XRD). Amorphous materials are considered to be amorphous.

As used herein, the terms "first," "second," and other ordinal words are to be understood to provide only distinction, and not to impose any particular spatial or temporal order.

As used herein, the term "oxide" of an element will be understood to include additional elements in addition to the element and oxygen, including but not limited to dopants or alloys. As used herein, the term "nitride" of an element should be understood to include additional elements in addition to the element and nitrogen, including but not limited to dopants or impurities.

As used herein, the term "damascene" should be understood to mean a damascene process. In such a process, the underlying silicon oxide insulating layer is imaged with an open trench or channel in which the conductor should be located. A thick copper coating is deposited on the insulator that significantly overfills the trench and Chemical Mechanical Planarization (CMP) is used to remove the copper extending over the top of the insulating layer (referred to as overburden). The copper that sinks into the trenches or channels of the insulating layer is not removed and becomes the imaged conductor. Damascene processes are typically formed at each damascene stage and fill individual features with copper. Dual damascene processes are typically formed immediately and fill both features with copper.

Furthermore, "self-aligned dual imaging (SADP)" as used herein is a form of dual imaging. This is sometimes referred to as compartmentalization, spacer or sidewall assisted dual imaging. The SADP process uses one lithography step and additional deposition and etching steps to define the spacer-type features. Typically, in an SADP process, the first step is to form a mandrel on the substrate. The image is then covered with a deposition layer. The deposited layer is then etched, which in turn forms spacers. Finally, the top portion undergoes a chemical mechanical polishing or planarization (CMP) step.

The technology is applied to a novel vertical 3D X-Point PCM memory, a programming/reading scheme and the like so as to reduce the production cost. The newly proposed three-dimensional storage architecture provides lower cost and other benefits. In the proposed integration scheme for vertical 3D x-point memory, word lines are formed with replacement metals, and local bit lines are all formed vertically perpendicular to the word lines, with global bit lines connecting the local bit lines in different pages. The PCM cells are formed in the recesses of the word lines while an Ovonic Threshold Switch (OTS) film is deposited as a continuous film (due to its insulator properties). This vertical 3D X-point provides a more flexible approach to scaling and cost reduction, etc., than the conventional stacked setup 3D x-point architecture. Various embodiments of cell array architectures are also presented herein. Additional benefits of the novel architecture include, but are not limited to: the replacement of the WL does not require additional self-aligned dual imaging (SADP) which may increase production costs; shared WLs and BLs between adjacent memory cells, and lower WL and BL resistances due to the shared WLs and BLs. Furthermore, there is no misalignment problem between different stacked layers. The novel architecture has a high degree of scalability to more stacked layers without the need to add photolithography steps. The novel technology can be extended to other resistive memory technologies. In addition, the novel techniques disclosed herein may be utilized among other resistive memory technologies.

Turning to the drawings, a generalized prior art example of a three-dimensional (3D) memory is shown in fig. 1A. Specifically, fig. 1A is an isometric view of a section of a three-dimensional cross-point memory. The memory comprises a first layer of memory cells 5 and a second layer of memory cells 10. Between the first level memory cells 5 and the second level memory cells are a number of word lines 15 extending in the X-direction. Above the first level of memory cells 5 are a number of first bit lines 20 extending in the Y-direction and below the second level of memory cells are a number of second bit lines 25 extending in the Y-direction. Furthermore, as can be seen from the figure, the sequential structure of bit line-memory cell-word line-memory cell can be repeated in the Z-direction to achieve a stacked configuration. In any case, individual memory cells can be accessed by selectively activating the word lines and bit lines corresponding to the cells.

In fig. 1B, a single section 100 of the cell structure of fig. 1A is shown. Which shows a top cell bitline 110 connected to a top cell stack 150. The stack 150 is comprised of several layers, which will be described herein in a modification to this standard stack 150. The top cell word line 130 and the bottom cell word line 140 are perpendicular to the top cell bit line 110. The bottom cell stack layer 160 is connected to the bottom cell word line 140. The bottom cell bit line 120 is parallel to the top cell bit line 110. Bottom cell bit line 120 is coupled to bottom cell stack layer 160. Similar to cell stack layer 150, cell stack layer 160 is also composed of several layers. Fig. 1A and 1B show the general structure of a 3D X-Point memory cell, and the term 3D X-Point memory cell is used herein to describe the improvement. Fig. 1A depicts a section as seen in the Z (depth) direction. The segment includes a number of word lines (e.g., word lines 130, 140) extending in an X (horizontal) direction, a number of top cell bit lines (e.g., bit lines 110, 120) extending in a Y (vertical) direction and corresponding to a top cell array of memory cells 150, and a number of bottom cell bit lines extending in a vertical direction and corresponding to a bottom cell array of memory cells 160. The X-direction and Y-direction references will be made using the directional model shown in fig. 1A-1B. Fig. 1A-1B show the general structure of a 3D X-Point memory cell, and the term 3D X-Point memory cell is used herein to describe the improvements. Depending on the embodiment, the word lines, top cell bit lines, and bottom cell bit lines may or may not typically be formed according to a 20nm/20nm line/space (L/S) pattern, and are formed on a silicon substrate. Further, the memory may employ Complementary Metal Oxide Semiconductor (CMOS) technology.

As described above, the problem of reusing SADP imaging for each stack layer is solved by the present disclosure. Turning to fig. 2A, which is a plan view of the structure along the x-direction, it is shown that a multilayer nitride/poly-silicon dioxide (poly or poly-Si) stack 200 is formed. Stacked layer 200 includes alternating layers having a plurality of nitride layers 204 and a plurality of polysilicon dioxide layers 211. Depending on the embodiment, the layers may alternate with the nitride layer in a top position and/or a bottom position, as shown in fig. 2A. The substrate 201 is used for the formation of a plurality of nitride/polysilicon dioxide stack layers 200. FIG. 2B-1 is a top view of the stack 200 of FIG. 2A. The formation of a plurality of holes 202 or channel holes 202 that penetrate the stack for subsequent memory cell and bit line definition is shown. The hole 202 penetrates all the layers of the stack 200 up to the substrate 201. Depending on the implementation, holes 202 may or may not penetrate partially through stack 202 and/or penetrate stack 200 to various depths. For the purposes of the description herein, holes 202 have a uniform depth and penetrate completely through stack layer 200 to substrate 201. However, this example is not intended to limit the scope of the invention to any such example.

The cross-sectional view of fig. 2B-1 is taken along line a-a and is seen in a similar x-direction as fig. 2A. This cross-sectional view is shown in fig. 2B-2. Finger storage area 1, finger storage area 2, and finger storage area 3 are shown in fig. 2B-2. Multiple finger storage areas and apertures may be utilized in the present disclosure. Depending on the embodiment, the number of holes may be 6 to 8 or 6 or 8 holes. It is meant that memory regions 1-3 are formed by holes in stack layer 200. Fig. 2C shows layer key information (key). The layer key information indicates various layers that may or may not be added to the stack of layers 200. Also, layer 204 is a nitride layer. Examples of such materials include, but are not limited to, metal nitrides such as TiN, TiAlN, TaN, BN, metal oxynitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with or without doping), reduced metal oxides such as TiOx (x <2 denotes reduction), metals such as W, Ni, Co, or carbon-based materials.

Layer 211 is a polysilicon dioxide or polysilicon (poly or poly Si) material. Layer 211 may comprise any film thickness, depending on the embodiment, and may typically be 2-5 μm. Layer 208 is an Ovonic Threshold Switch (OTS) material. OTS materials are typically glass-based switches that return to a high resistance state when the current falls below a holding current value after being brought from the high resistance state to an on-state. Likewise, any OTS material may be used with the present disclosure.

Layer 206 is a Phase Change Material (PCM) memory cell layer. Also, PCM is a non-volatile solid-state storage technology that utilizes reversible, thermally-assisted switching of phase change materials, such as chalcogenides, such as GST (germanium antimony tellurium), between states having different resistances. The basic memory cell (cell) can be programmed into a plurality of different states or levels exhibiting different resistance characteristics. Programmable cell states can be used to represent different data values, allowing the storage of information.

Layer 205 is an electrode layer. The electrodes may be formed of any convenient conductive material, typically a metallic material (e.g., pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material, such as silicon. Furthermore, although the features described are particularly advantageous for multi-level cells, in some embodiments these features may also be applied to advantage in single level cells.

Layer 210 is a tungsten layer. Depending on the embodiment, tungsten may be used as the metal used to define the write lines and bit lines. Likewise, any metal-based material may utilize the principles of the present disclosure. Also, as previously mentioned, the use of the terms first, second and third merely provides a distinction, not imposing any particular spatial or temporal order. For example, the carbon electrodes may be interchangeable and references to the terms first, second and third are used only as references to describe adjacent elements. Each layer is abbreviated as: nitride/poly Si/OTS/PCM/carbon electrode/W (tungsten) as shown in fig. 2C. Reference numeral 201 refers to a substrate or oxide layer, depending on the implementation.

FIG. 3A shows exemplary cell

finger storage areas

1, 2, 3. Each finger storage area is composed of several layers as described previously. The

finger storage areas

1, 2, 3 are similar in function and composition. For the purposes of describing the materials disclosed herein, like reference numerals refer to like materials and functions of the elements shown and described throughout the figures. Recessing of the poly-Si layer is also shown. Recessing of these poly-Si layers 211 may be accomplished by various methods known to those skilled in the art. Depending on the implementation, all of layers 211 may be recessed, or a selected number of layers 211 may be recessed. The recess is defined by the removal of material from the polycrystalline silicon dioxide (poly-Si) layer 211, or the recess is defined by a partially removed polycrystalline silicon dioxide layer. The recess is followed by filling the formed depression with PCM material 206 as shown in fig. 3A. The filling of the PCM material 211 may or may not be followed by a dry or wet etch back. A wet etch may be used to remove the poly-Si material 211 for filling with the PCM material 206. Depending on the implementation, ammonium hydroxide or hydrogen peroxide may be utilized in the etching process.

The deposition of the OTS material 208 over the

finger storage regions

1, 2, 3 is shown in fig. 3B. These deposits form an encapsulation layer of the OTS layer 208 over the finger storage areas and cover the top of the substrate 201. The OTS or ovonic threshold switch 208 within each finger memory bank stack layer serves as a selector.

Fig. 4A illustrates the deposition of metal or tungsten (W) 210 in this embodiment into the hole 202 in fig. 3B. Depending on the embodiment, the filling of the metal material into the hole 202 may or may not be level with the top layer of the stack of layers (top layer 204 in this example). The filling or deposition of W or other material is followed by a chemical mechanical polishing or planarization (CMP) process to form the local bit lines. An oxide/nitride Chemical Mechanical Planarization (CMP) process may produce an oxide layer, if so desired. Fig. 4B shows the formation of a cut in stack 200 and the removal of poly-Si by wet etching to form a gap 209 in each finger storage region. Typically, the deposition may be accomplished by Chemical Vapor Deposition (CVD). In this process, vacuum deposition methods are used to produce high quality, high performance solid materials. In typical CVD, a wafer (substrate) is exposed to one or more volatile precursors (volatile precursors), which react and/or decompose on the substrate surface to produce the desired deposition. Other approaches may also be utilized depending on the implementation.

Fig. 5 shows the gap 209 in fig. 4B being filled with a Word Line (WL) metal 210 or material to form a word line. The WL material may be a material used by those skilled in the art. If gap filling is desired, the gap filling may be obtained by atomic layer deposition of oxide, spin-on dielectric (SOD), or flowable Chemical Vapor Deposition (CVD) oxide. Examples of gap fill materials include, but are not limited to, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), aluminum nitride (AlN), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium tellurite (CdTe), zinc sulfide (ZnS), lead sulfide (PbS), and lead selenide (PbSe), and cobalt-based compounds, and any combination thereof.

Fig. 6A and 6B show Global Bit Lines (GBLs) connected to individual Local Bit Lines (LBLs) in each page or section of the stack and to multiple LBLs in multiple pages as the stack grows. FIG. 6A shows

global bit lines

1 and 2 labeled 610 and 620, respectively. GBL1 or 610 and GBL2 or 620 communicate with a vertical local bit line LBLa labeled 630 and a vertical local bit line LBLb labeled 640, respectively, as shown in FIG. 6A. The word lines are formed horizontally to the vertical local bit lines, respectively, as shown in WL1 labeled 660 and WL2 labeled 670, respectively. Depending on the embodiment, the word lines communicate with local bit lines. As shown in fig. 6B, an array architecture is shown. The black dots represent the vertical bit lines in fig. 6A.

Global bit lines

610, 620, 653, 654 for

GBLs

1, 2, 3, 4, respectively, are shown in array 650. In this example, the two sections or pages are page 655 for page 1 and page 656 for page 2 as shown. However, it is within the scope of the present disclosure to have multiple pages with the build of stacked layers. The given structure is given only to describe the principles of the present method and system of the present disclosure. Each GBL is connected to a separate LBL in each page, as shown in fig. 6B. LBLa (630) and LBLi (668) are shown in communication with GBL1 (610). LBLc (662) and LBLg (667) communicate with GBL2 (620). LBLb (640) and LBLf (664) are in communication with GBL4 (654). LBLd (663) and LBLh (665) communicate with GBL3 (653).

Fig. 7A and 7B illustrate cell biasing for the illustrations in fig. 6A-6B, where like reference numerals refer to like structures. GBL 610 and LBL 630 biased to + Vhh and Word Line (WL) 670 biased to-Vll are shown for a selected cell 700 belonging to cell 710. All other GBLs/LBLs and WLs are biased to 0, e.g., as shown for

reference numbers GBL

620, 653 and 654. For example, selected

cells

700 and 710 are biased to Vhh + Vll. The unselected cells (such as 720) are biased to Vhh or Vll or 0.

Fig. 8A and 8B are second embodiments of the array architecture of fig. 6A and 6B for stacked layers 200. Each GBL is shown connected to a separate LBL in each page and multiple LBLs in multiple pages. The array architecture embodiment may require self-aligned quad imaging (SAQP). SAQP, such as SADP, is a multiple imaging (or multiple imaging) class of technology used in the manufacture of Integrated Circuits (ICs) that has been developed for use in lithography to enhance feature density. Which is expected to be necessary for 10nm and 7nm node semiconductor processes and higher. The precursor of which is a single lithographic exposure may not be sufficient to provide sufficient resolution. Thus, additional exposure would be required or a positioning image using etched feature sidewalls (using spacers) would be necessary. Shown in FIG. 8A are

global bit lines

1 and 2, labeled 810 and 820, respectively. GBL1 or 810 and GBL2 or 820 communicate with a vertical local bit line LBLa labeled 830 and a vertical local bit line LBLb labeled 840, respectively, as shown in FIG. 8A. The word lines are formed horizontally to the vertical local bit lines as shown in WL1 labeled 860 and WL2 labeled 870, respectively. Depending on the embodiment, the word lines communicate with local bit lines. As shown in fig. 8B, an array architecture is shown. The black dots represent the vertical bit lines in fig. 8A.

Global bit lines

810, 820, 853, 854, 856, 857 for BL1, 2, 3, 4, 5, 6, respectively, are shown in array 850. In this example, two pages are shown, e.g., page 855 for page 1 and page 856 for page 2. However, it is within the scope of the present disclosure to have multiple pages with the build of stacked layers. The given structure is given only to describe the principles of the present method and system of the present disclosure. Each GBL is connected to a separate LBL in each page, as shown in fig. 8B. LBLa (830) is shown in communication with GBL1 (810). LBLc (862) is in communication with GBL2 (820). LBLe (865) is in communication with GBL3 (853). LBLb (840) is in communication with GBL4 (854). LBLd (863) is in communication with GBL 5 (856). And LBLf (864) in communication with GBL6 (857).

Fig. 9A-9B illustrate a third embodiment of fig. 6A-6B. Each GBL is shown connected to a separate LBL in each page and multiple LBLs in multiple pages. This array architecture embodiment may require self-aligned quad imaging (SAQP) as in the second embodiment shown in FIGS. 8A-8B. Shown in FIG. 8A are

global bit lines

1 and 2, labeled 910 and 920, respectively. GBL1 or 910 and GBL2 or 920 communicate with a vertical local bit line LBLa, labeled 930, and a vertical local bit line LBLb, labeled 940, respectively, as shown in FIG. 9A. The word lines are formed horizontally to the vertical local bit lines, as shown in WL1 labeled 960 and WL2 labeled 970, respectively. Depending on the embodiment, the word lines communicate with local bit lines. As shown in fig. 9B, an array architecture is shown. The black dots represent the vertical bit lines in fig. 9A.

Global bit lines

910, 920, 953, 954, 956, 957, 958, 959 for BL1, 2, 3, 4, 5, 6, 7, 8, respectively, are shown in array 950. In this example, one page is shown, e.g., page 955 for page 1. However, it is within the scope of the present disclosure to have multiple pages with the build of stacked layers. The given structure is given only to describe the principles of the present method and system of the present disclosure. Each GBL is connected to a separate LBL in each page, as shown in fig. 9B. LBLa (930) is shown in communication with GBL1 (910). LBLc (962) is in communication with GBL2 (920). LBLe (965) communicates with GBL3 (953). LBLf (964) is in communication with GBL7 (958). LBLg (969) is in communication with GBL4 (954). LBLd (963) communicates with GBL6 (957). LBLf (964) is in communication with GBL7 (958). And LBLh (967) is in communication with GBL8 (959).

Fig. 10A-C, 11-11B, 12 are illustrations of a fourth embodiment of the present disclosure. There is shown another alternative description of the core concepts, methods, structures, material compositions and/or process steps for achieving the objects of the disclosure. Fig. 10A, 10B and 10C have similar structures and reference numerals as fig. 2A, 2B-2 and 2B-1, and similar descriptions as previously described, respectively. Fig. 10A, 10B and 10C illustrate the formation of a plurality of nitride/polysilicon stack layers 200 and the formation of a hole or channel hole 202 within the stack layers for subsequent cell and bit line definition.

Fig. 11-11B have similar reference numerals and structures as previously described for fig. 3A-3B. However, fig. 11A shows a difference from fig. 3A in that: fig. 11A shows recessing the polysilicon and filling the recess with a carbon layer 205 and a PCM material 206 to form pocket cells defined by both

material layers

205 and 206. The recess is formed using dry or wet etch back. Fig. 11B illustrates the deposition of the OTS material 208 as a selector.

Fig. 12 illustrates deposition of tungsten or other metal followed by CMP to form local bit lines. Similar reference numerals and structures shown in fig. 4A-4C and 5 illustrate common structures and descriptions. A cut is made in stack 200 and the poly-Si is removed, typically by a wet etch technique. The gaps formed by the wet etch are filled with word line metal to form word lines, such as 660 and 670 in fig. 12. Also, the differences between the previous embodiments of fig. 4A-4C, 5 and 6A are: rather than using only the PCM material 206, it is added to fill the recesses with the carbon layer 205 and the PCM material 206 to form pocket cells.

Fig. 13A, 13B, 13C, 14A-14B, and 15 are illustrations of a fifth embodiment of the present disclosure. There is shown another alternative description of the core concepts, methods, structures, material compositions and/or process steps for achieving the objects of the disclosure. Fig. 13A, 13B and 13C have similar structures and reference numerals as fig. 2A, 2B-2 and 2B-1, and similar descriptions as previously described, respectively. Fig. 13A, 13B and 13C illustrate the formation of a plurality of nitride/polysilicon stack layers 200 and the formation of a hole or channel hole 202 within the stack layers for subsequent cell and bit line definition.

Fig. 14-14B have similar reference numerals and structures as previously described for fig. 3A-3B. However, fig. 14A shows a difference from fig. 3A and the previous fig. 11A in that: fig. 14A shows recessing the polysilicon and filling the recess with a layer of carbon 205 and a PCM material 206 and again filling the recess with a layer of carbon 205 to form a pocket cell defined by both the layer of material 205 and the layer of material 206. The recess is formed using dry or wet etch back. Fig. 14B shows the deposition of the OTS material 208 as a selector.

Fig. 15 illustrates the deposition of tungsten or other metal followed by CMP to form local bit lines. Similar reference numerals and structures shown in fig. 4A-4C and 5 illustrate common structures and descriptions. A cut is made in stack 200 and the poly-Si is removed, typically by a wet etch technique. The gaps formed by the wet etch are filled with word line metal to form word lines, such as 660 and 670 in fig. 15. Also, the differences between the previous embodiments of FIGS. 4A-4C, 5 and 6A, and 11A-B and 12 are: instead of using only the PCM material 206 as shown in fig. 5 or using the PCM material 206 and one carbon layer 205 as shown in the illustrative example in fig. 12, it is added to fill the recess with the carbon layer 205 and then fill the recess again with the second carbon layer 205 to form a pocket cell.

Most of the previous alternative examples are not mutually exclusive and can be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features described above can be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. As an example, the preceding operations do not have to be performed in the exact order described above. Rather, the various steps may be processed in a different order, such as reverse order or concurrently. Steps may also be omitted unless otherwise stated. Furthermore, the provision of examples described herein and clauses expressed as "such as … …," "including … …," etc., should not be construed as limiting the claimed subject matter to specific examples; rather, the example is meant to illustrate only one of many possible embodiments. Moreover, the same reference numbers in different drawings may identify the same or similar elements.

Although the present disclosure has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A vertical three-dimensional phase change material memory cell structure, comprising:

at least one memory cell stack layer having a selector, a Phase Change Material (PCM) memory cell, and first and second electrodes; the PCM memory cell is disposed between the first electrode and the second electrode;

each memory cell stack layer having a horizontal word line and a vertical bit line that are perpendicular to each other and coupled to the memory cell stack layer, and wherein the memory cell stack layer is self-aligned with respect to the word line and the bit line; and is

Wherein the memory cells are self-aligned to the word lines and bit lines and are formed with metal for improved programming and increased array size.

2. The vertical three-dimensional phase change material memory cell structure of claim 1,

the memory cells are formed as horizontal cells between mutually perpendicular word lines and bit lines,

the stacked layers include alternating layers having a plurality of nitride layers and a plurality of polysilicon oxide layers (poly-Si), and

the PCM memory cells in each stacked layer are formed in recesses between the nitride layers, and the recesses are defined by partially removing the polysilicon dioxide layer between the nitride layers.

3. The vertical three-dimensional phase change material memory cell structure of claim 1, wherein the word lines and/or the bit lines are formed using a damascene process.

4. The vertical three-dimensional phase change material memory cell structure of claim 1, wherein the metal is a tungsten (W) material.

5. The vertical three-dimensional phase change material memory cell structure of claim 1, further comprising: additional memory cells in a region above or below the two-dimensional region defined by the word line.

6. The vertical three dimensional phase change material memory cell structure of claim 1, wherein the subarray or slice size is increased to improve array efficiency.

7. A vertical three-dimensional X-Point Phase Change Material (PCM) memory architecture, comprising:

a plurality of nitride/poly-silicon dioxide memory stack layers, wherein each stack layer defines a plurality of channel holes along a vertical direction for a plurality of memory cells and a plurality of bit lines;

the stacked layers forming a plurality of finger storage regions having channel holes therebetween;

each pair of finger storage regions defines a gate gap, and each finger storage region is separated by the gate gap;

wherein the plurality of bit lines includes vertical local bit lines connected to different global bit lines in the finger storage region; and is

Wherein the vertical local bit lines and the global bit lines are formed of a metal material to electrically access each memory cell.

8. The vertical three dimensional X-Point PCM storage architecture of claim 7, wherein the local bitlines are vertical and wordlines are horizontal and coupled with the local bitlines.

9. The vertical three-dimensional X-Point PCM storage architecture of claim 7, wherein the number of channel holes per finger storage region is 6 or 8 channel holes.

10. A method of forming a three-dimensional memory stack, comprising:

forming a stacked layer having a plurality of nitride layers and polycrystalline silicon dioxide layers;

forming a plurality of holes in the stack for subsequent cell and bit line definition;

recessing the polysilicon dioxide to form a recess, and filling the recess with a Phase Change Material (PCM), followed by dry or wet etch back;

depositing an Ovonic Threshold Switch (OTS) material as a selector on the stack of layers;

depositing tungsten (W) or other metal on the stack layer, followed by chemical mechanical polishing or planarization (CMP) to form a plurality of local vertical bit lines;

forming a cut in the stack of layers and removing the polysilicon dioxide using a wet etch; and

gap filling is performed by using word line metal to form a plurality of word lines.

11. The method of claim 10, wherein the plurality of wells is 6 to 8 wells.

12. The method of claim 10, wherein the recessing of the polycrystalline silicon dioxide further comprises: forming pocket cells and filling the recesses with an ordered sequence of carbon and phase change memory.

13. The method of claim 10, wherein the recessing of the polycrystalline silicon dioxide further comprises: forming pocket cells and filling the recesses with an ordered sequence of carbon, phase change material and carbon material.

14. The method of claim 10, wherein the plurality of apertures further define a plurality of finger storage regions, and each finger storage region is separated by a gate gap.

15. The method of claim 14, wherein the vertical local bit lines are connected to different global bit lines in the finger storage area.