WO2022241635A1

WO2022241635A1 - Three-dimensional phase-change memory devices and methods for forming the same

Info

Publication number: WO2022241635A1
Application number: PCT/CN2021/094295
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2021-05-18
Filing date: 2021-05-18
Publication date: 2022-11-24
Also published as: CN113439336A; CN113439336B

Abstract

A three-dimensional (3D) memory device includes a stack structure including interleaved a plurality of word line layers and a plurality of dielectric layers; and a plurality of phase-change memory (PCM) strings. Each of the PCM strings extends through the stack structure in a first direction and includes an isolation structure extending through the stack structure in the first direction; and a plurality of PCM string parts separated by the isolation structure. Each PCM string part includes a local bit line, a selector layer circumscribing the local bit line, and a plurality of PCM structures between the selector layer and the plurality of word line layers.

Description

THREE-DIMENSIONAL PHASE-CHANGE MEMORY DEVICES AND METHODS FOR FORMING THE SAME

BACKGROUND

The present disclosure relates to phase-change memory (PCM) devices and fabrication methods thereof.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials based on heating and quenching of the phase-change materials electrothermally. PCM array cells can be vertically stacked in 3D to form a 3D PCM.

SUMMARY

In an aspect, a three-dimensional (3D) memory device includes a stack structure including interleaved a plurality of word line layers and a plurality of dielectric layers; and a plurality of phase-change memory (PCM) strings, each of the PCM strings extending through the stack structure in a first direction and including an isolation structure extending through the stack structure in the first direction; and a plurality of PCM string parts separated by the isolation structure, each PCM string parts including a local bit line, a selector layer circumscribing the local bit line, and a plurality of PCM structures between the selector layer and the plurality of word line layers.

In another aspect, a three-dimensional (3D) memory device includes a stack structure including interleaved a plurality of word line layers and a plurality of dielectric layers; and a plurality of phase-change memory (PCM) strings, each of the PCM strings extending through the stack structure in a first direction and including a local bit line extending in the first direction; a selector layer circumscribing the local bit line; a plurality of isolation structure extending in the first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and a plurality of PCM structures between the selector layer and the plurality of word line layers in the second direction, each of the plurality of PCM structures between two of the plurality of isolation structures in the second direction.

In another aspect, a system includes a three-dimensional (3D) memory device configured to store data, the 3D memory device including: a stack structure including interleaved a plurality of word line layers and a plurality of dielectric layers; and a plurality of phase-change memory (PCM) strings, each of the PCM strings extending through the stack structure in a first direction and including an isolation structure extending through the stack structure in the first direction; and a plurality of PCM string parts separated by the isolation structure, each PCM string part including a local bit line, a selector layer circumscribing the local bit line, and a plurality of PCM structures between the selector layer and the plurality of word line layers; and a memory controller coupled to the 3D memory device and configured to control operations of the plurality of PCM cells through the local bit line and the plurality of word lines.

In another aspect, a system includes a three-dimensional (3D) memory device configured to store data, the 3D memory device including a stack structure including interleaved a plurality of word line layers and a plurality of dielectric layers; and a plurality of phase-change memory (PCM) strings, each of the PCM strings extending through the stack structure in a first direction and including a local bit line extending in the first direction; a selector layer circumscribing the local bit line; a plurality of isolation structure extending in the first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and a plurality of PCM structures between the selector layer and the plurality of word line layers in the second direction, each of the plurality of PCM structures between two of the plurality of isolation structures in the second direction; and a memory controller coupled to the 3D memory device and configured to control operations of the plurality of PCM cells through the local bit line and the plurality of word lines.

In still another aspect, a method for forming a three-dimensional (3D) memory device includes forming a stack structure including interleaved a plurality of conductive layers and a plurality of dielectric layers on a substrate; and forming a phase-change memory (PCM) string extending through the stack structure in a first direction, wherein the PCM string includes: an isolation structure extending through the stack structure in the first direction; a plurality of PCM string parts separated by the isolation structure, each PCM string parts including a local bit line structure extending in the first direction; a selector layer circumscribing a respective local bit line; and a plurality of PCM structures between the selector layer and the plurality of conductive layers, respectively.

In yet another aspect, a method for forming a three-dimensional (3D) memory device includes forming a stack structure including interleaved a plurality of conductive layers and a plurality of dielectric layers on a substrate; and forming a plurality of phase-change memory (PCM) strings extending through the stack structure in a first direction, each PCM string including a local bit line extending in the first direction; a selector layer circumscribing the local bit line; a plurality of isolation structures extending in the first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and a plurality of PCM structures between the selector layer and the plurality of conductive layers in the second direction, the plurality of PCM structures between two of the plurality of isolation structures in the second direction.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate implementations of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1 illustrates a perspective view of a 3D cross-point (XPoint) memory device.

FIG. 2A illustrates a plan view of a cross-section of an exemplary 3D PCM device, according to some aspects of the present disclosure.

FIG. 2B illustrates a plan view of a cross-section of an exemplary 3D PCM device, according to some aspects of the present disclosure.

FIG. 2C illustrates a side view of a cross-section of an exemplary 3D PCM device, according to some aspects of the present disclosure.

FIG. 2D illustrates a partially enlarged plan view of a cross-section of an exemplary 3D PCM device, according to some aspects of the present disclosure.

FIG. 3A illustrates a plan view of a cross-section of another exemplary 3D PCM device, according to some aspects of the present disclosure.

FIG. 3B illustrates a side view of a cross-section of another exemplary 3D PCM device, according to some aspects of the present disclosure.

FIG. 3C illustrates a side view of a cross-section of another exemplary 3D PCM device, according to some aspects of the present disclosure.

FIGs. 4A–4E illustrate PCM cell array layouts of various exemplary 3D PCM devices, according to various aspects of the present disclosure.

FIGs. 5A–5H illustrate an exemplary fabrication process for forming a 3D PCM device, according to some aspects of the present disclosure.

FIGs. 6A–6D illustrate plan views of a cross-section of an exemplary fabrication process for forming a 3D PCM device, according to some aspects of the present disclosure.

FIGs. 6E–6H illustrate side views of a cross-section of an exemplary fabrication process for forming a 3D PCM device, according to some aspects of the present disclosure.

FIG. 7A illustrates a flowchart of an exemplary method for forming a 3D PCM device, according to some aspects of the present disclosure.

FIG. 7B illustrates a flowchart of another exemplary method for forming a 3D PCM device, according to some aspects of the present disclosure.

FIG. 8 illustrates a block diagram of an exemplary system having a 3D memory device, according to some aspects of the present disclosure.

FIG. 9A illustrates a diagram of an exemplary memory card having a 3D memory device, according to some aspects of the present disclosure.

FIG. 9B illustrates a diagram of an exemplary solid-state drive (SSD) having a 3D memory device, according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 80 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term “3D memory device” refers to a semiconductor device with memory cells that can be arranged vertically on a laterally-oriented substrate so that the number of memory cells can be scaled up in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means perpendicular to the lateral surface of a substrate.

A PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally. The phase-change material in a PCM cell can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data. PCM cells can be vertically stacked in 3D to form a 3D PCM.

3D PCMs include 3D cross-point (XPoint) memory, which stores data based on a change in resistance of the bulk material property (e.g., in a high-resistance state or a low-resistance state) , in conjunction with a stackable cross-point data access array to be bit-addressable. For example, FIG. 1 illustrates a perspective view of a 3D XPoint memory device 100.3D XPoint memory device 100 has a transistor-less, cross-point architecture that positions memory cells at the intersections of perpendicular conductors, according to some implementations. 3D XPoint memory device 100 includes a plurality of parallel lower bit lines 102 in the same plane and a plurality of parallel upper bit lines 104 in the same plane above lower bit lines 102.3D XPoint memory device 100 also includes a plurality of parallel word lines 106 in the same plane vertically between lower bit lines 102 and upper bit lines 104. As shown in FIG. 1, each lower bit line 102 and each upper bit line 104 extends laterally along the bit line direction in the plan view (parallel to the wafer plane) , and each word line 106 extends laterally in the word line direction in the plan view. Each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.

It is noted that x and y axes are included in FIG. 1 to illustrate two orthogonal directions in the wafer plane. The x-direction is the word line direction, and the y-direction is the bit line direction. It is noted that z-axis is also included in FIG. 1 to further illustrate the spatial relationship of the components in 3D XPoint memory device 100. The substrate (not shown) of 3D XPoint memory device 100 includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the backside opposite to the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., a layer or a device) is “on, ” “above, ” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D XPoint memory device 100) is determined relative to the substrate of the semiconductor device in the z-direction (the vertical direction perpendicular to the x-y plane) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing the spatial relationships is applied throughout the present disclosure.

As shown in FIG. 1, 3D XPoint memory device 100 includes a plurality of memory cells 108, each disposed at an intersection of lower or

upper bit line

102 or 104 and respective word line 106. Each memory cell 108 has a vertical square pillar shape. Each memory cell 108 includes at least a PCM element 110 and a selector 112 stacked vertically. Each memory cell 108 stores a single bit of data and can be written or read by varying the voltage applied to respective selector 112, which replaces the need for transistors. Each memory cell 108 is accessed individually by a current applied through the top and bottom conductors in contact with each memory cell 108, e.g., respective word line 106 and lower or

upper bit line

102 or 104. Memory cells 108 in 3D XPoint memory device 100 are arranged in a memory array.

To form 3D XPoint memory device 100, bottom memory cells 108 in bottom cell stack between lower bit lines 102 and word lines 106 are formed first by patterning both lower bit lines 102 and word lines 106 to define bottom pillar memory cells 108, followed by the top cell stack deposition and upper bit lines 104 patterning to define top pillar memory cell 108. Each stack is formed with two self-aligned double patterning (SADP) processes. Further scaling will add more stacks on top to lower the fabrication cost. However, the cost-benefit will diminish because of the high cost associated with the additional SADP process for each stack formation.

To address one or more of the aforementioned issues, the present disclosure introduces a novel architecture of 3D PCM devices with lower manufacturing costs. In the architecture disclosed herein, lateral word lines can be all formed together, for example, by replacing sacrificial layers, and local bit lines can be all formed vertically perpendicular to the word lines, with global bit lines connecting local bit lines in different regions. PCM structures can be formed in the recesses of word lines, while the selector layer can be deposited as a continuous layer due to its insulator property. As a result, SADP processes can be eliminated, and misalignment between different cell stacks can be avoided in the architecture disclosed herein. Moreover, no additional lithography processes are needed to vertically scale up the word lines. Thus, the 3D PCM devices disclosed herein can provide more flexible scaling and cost reduction than conventional 3D XPoint memory devices. Last but not the least, by forming an isolation structure in the hole to separate memory cells, a local bit line and a PCM memory cell can be separated into two or four. Thus, the 3D PCM device disclosed herein can store more bits in each memory cell.

FIG. 2A illustrates a plan view of a cross-section of an exemplary 3D PCM device 200, according to some aspects of the present disclosure. As shown in FIG. 2A, 3D PCM device 200 can include an array of PCM strings 220 and one or a plurality of slit structures 205. Each PCM string 220 includes an isolation structure 214 separating the PCM string 220 into a plurality of PCM string parts (e.g., into two PCM string parts as PCM string parts 2201 and 2202) . In some implementations, the isolation structure 214 is formed in the middle of the PCM string 220 and separates the PCM string 220 into two semicircular shapes in the plan view. It is understood that the shape of PCM string parts in the plan view is not limited to semicircular and can be any other shapes. Also, the isolation structure 214 is not limited to form in the middle of the PCM string 220 and can be formed on the side or any place of the PCM string 220. It is also not limited to include only one isolation structure 214 in each PCM string 220 and can be formed multiple isolation structures in each PCM string 220. In some implementations, the isolation structure 214 of 3D PCM device 200 extends laterally in the y-direction. Slit structures 205 can extend laterally in the x-direction to divide 3D PCM device 200 into multiple regions in the y-direction, such as blocks, fingers, pages, etc., each of which includes multiple PCM strings 220. Each region may correspond to the smallest unit by a memory operation for 3D PCM device 200, such as read, program (write) , or erase, in different examples. In some implementations, the word lines of 3D PCM device 200 extend laterally in the x-direction, and the bit lines of 3D PCM device 200 extend laterally in the y-direction, which is perpendicular to the x-direction. That is, in the present disclosure, the x-direction may correspond to the word line direction, and the y-direction may correspond to the bit line direction.

FIG. 2B illustrates a plan view of a cross-section of another exemplary 3D PCM device 250, according to some aspects of the present disclosure. As shown in FIG. 2B, 3D PCM device 250 can include an array of PCM strings 240 and one or a plurality of slit structures 255. Each PCM string 240 includes an isolation structure 245 and separating the PCM string 240 into a plurality of PCM string parts (e.g., into four PCM string parts as

PCM string parts

2401, 2402, 2403, and 2404) . In some implementations, the isolation structure 245 is a cross shape and formed in the middle of the PCM string 240 to separate the PCM string 240 into four sector shapes in the plan view. It is understood that the shape of PCM string parts in the plan view is not limited to sector and can be any other shapes. Also, the isolation structure 245 is not limited to form in the middle of the PCM string 240 and can be formed on the side or any place of the PCM string 240. It is also not limited to include only one isolation structure 245 in each PCM string 240 and can be formed multiple isolation structures in each PCM string 240. In some implementations, the isolation structure 245 of 3D PCM device 250 extends laterally in the y-direction and in the x-direction. Slit structures 255 can extend laterally in the x-direction to divide 3D PCM device 250 into multiple regions in the y-direction, such as blocks, fingers, pages, etc., each of which includes multiple PCM strings 240. Each region may correspond to the smallest unit by a memory operation for 3D PCM device 250, such as read, program (write) , or erase, in different examples. In some implementations, the word lines of 3D PCM device 250 extend laterally in the x-direction, and the bit lines of 3D PCM device 250 extend laterally in the y-direction, which is perpendicular to the x-direction. That is, in the present disclosure, the x-direction may correspond to the word line direction, and the y-direction may correspond to the bit line direction.

FIG. 2C illustrates a side view of a cross-section of an exemplary 3D PCM device 200, according to some aspects of the present disclosure. In some implementations, 3D PCM device 200 is an example of 3D PCM device 200 in FIG. 2A, and the cross-section of 3D PCM device 200 is along the AA plane of 3D PCM device 200 in FIG. 2A. It should be noted that the disclosed structure in the exemplary 3D PCM device 200 of FIG. 2C can also be implemented in the exemplary 3D PCM device 250 of FIG. 2B with appropriate adjustment. As shown in FIG. 2C, 3D PCM device 200 can include a substrate 202, which can include silicon (e.g., single crystalline silicon) , silicon germanium (SiGe) , gallium arsenide (GaAs) , germanium (Ge) , silicon on insulator (SOI) , germanium on insulator (GOI) , or any other suitable materials. In some implementations, substrate 202 is a thinned substrate (e.g., a semiconductor layer) , which was thinned by grinding, wet/dry etching, chemical mechanical polishing (CMP) , or any combination thereof. In some implementations, substrate 202 may be removed by a lift-off process, and 3D PCM device 200 may be adhered to another permanent substrate (not shown) by a wafer bonding process.

In some implementations, one or more peripheral devices (not shown) are formed on and/or in substrate 202. The peripheral devices can include any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D PCM device 200. For example, the peripheral devices can include one or more of a data buffer, a decoder (e.g., a row decoder and a column decoder) , a sense amplifier, a driver, a charge pump, a current or voltage reference, or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors) .

3D PCM device 200 can also include a memory array device formed on substrate 202, such as an array of PCM strings 220, as shown in FIG. 2C. As used herein, whether one component (e.g., a layer or a device) is “on, ” “above, ” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D PCM device 200) is determined relative to the substrate of the semiconductor device (e.g., substrate 202) in the z-direction (i.e., the vertical direction) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing spatial relationships is applied throughout the present disclosure.

In some implementations, each PCM string 220 can include a plurality of PCM string parts (e.g., two PCM string parts 2201 and 2202) . Each

PCM string part

2201 or 2202 can include a plurality of vertically stacked PCM cells 211. That is, PCM cells 211 of 3D PCM device 200 are stacked vertically and provided in each PCM string parts of the PCM string 220. In some implementations, the plurality of PCM string parts (e.g., two PCM string parts 2201 and 2202) is separated by an isolation structure 214. As shown in FIG. 2C, PCM string 220 can extend in the z-direction (vertical direction) through interleaved conductive layers 226 and dielectric layers 208 (also referred to herein as “conductive/dielectric layer pairs” ) . The interleaved conductive layers 226 and dielectric layers 208 are also referred to herein as a stack structure 224. The number of the conductive/dielectric layer pairs in stack structure 224 can set the number of PCM cells 211 in 3D PCM device 200. The isolation structure 214 can include any suitable materials, such as silicon oxide, silicon nitride, silicon oxynitride, or other insulation material. Conductive layers 226 and dielectric layers 208 in stack structure 224 can alternate in the vertical direction. In other words, except the ones at the top and the bottom of stack structure 224, each conductive layer 226 can be adjoined by two dielectric layers 208 on both sides, and each dielectric layer 208 can be adjoined by two conductive layers 226 on both sides. Conductive layers 226 can each have the same thickness or have different thicknesses. Similarly, dielectric layers 208 can each have the same thickness or have different thicknesses. Conductive layers 226 can include conductive materials including, but not limited to, tungsten (W) , cobalt (Co) , copper (Cu) , aluminum (Al) , polycrystalline silicon (polysilicon) , doped silicon, silicides, or any combination thereof. Dielectric layers 208 can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in FIG. 2C, each conductive layer 226 can extend laterally (e.g., in the x-direction/word line direction) and include one or more word lines of 3D PCM device 200. Thus, conductive layer 226 is also referred to herein as a word line layer 226. That is, stack structure 224 can include interleaved word line layers 226 and dielectric layers 208. In some implementations, 3D PCM device 200 includes a plurality of silt structures (not shown in FIG. 2C, e.g., 205 in FIG. 2A) , each of which is filled with one or more dielectric materials and extends through stack structure 224 in the z-direction to separate each word line layer 226 into a plurality of word lines. That is, each word line layer 226 can include multiple word lines separated by slit structures (e.g., 205 in FIG. 2A) , such that each region can include a respective one of the word lines. As shown in FIG. 2C, word line layers 226 (and word lines therein) are parallel to one another, as well as to the top surface of substrate 202, according to some implementations. In some implementations, edges of word line layers 226 are staggered at one or more sides of 3D PCM device 200 to define one or more staircase structures (not shown) for landing on word line contacts.

As shown in FIG. 2C, each PCM string 220 can extend vertically through stack structure 224 above substrate 202. In some implementations, PCM string 220 includes a hole in which a local bit line 231 and a selector layer 218 are formed. Local bit line 231 can include conductive materials including, but not limited to, W, Co, Cu, Al, doped polysilicon, silicides, or any combination thereof. In one example, local bit line 231 may include a metal, such as W. 3D PCM device 200 thus can include an array of parallel local bit lines 231 each extending vertically in the z-direction. Different from 3D XPoint memory device 100 in which bit lines 102/104 and word lines 106 all extend laterally and parallel to one another, in 3D PCM device 200, local bit lines 231 are perpendicular to the word lines in word line layers 226. As shown in FIG. 2C, 3D PCM device 200 can also include a plurality of global bit lines 233 in contact with respective local bit lines 231.

As shown in FIG. 2C, selector layer 218 can be a continuous layer formed along the sidewall and the bottom surface of the hole of PCM string 220. That is, in some implementations, selector layer 218 circumscribes local bit line 231. Part of selector layer 218 on the bottom surface of the hole of PCM string 220 can also separate local bit line 231 from substrate 202 to provide insulation. Also, selector layer 218 can include a threshold switch material that exhibits a resistance switching behavior when an external bias voltage higher than the threshold voltage is applied. In some implementations, the threshold switch material includes ovonic threshold switch (OTS) materials, such as zinc telluride (ZnTe) , germanium telluride (GeTe) , niobium oxide (NbO) , or silicon arsenic telluride (SiAsTe) , which exhibits a field-dependent volatile resistance switching behavior (known as “OTS phenomenon” ) when an external bias voltage higher than the threshold voltage is applied. In some implementations, the threshold switch material includes metal filament threshold switch (MFTS) materials, such as a metal ion reservoir for supplying metal ions, such as silver (Ag) , copper (Cu) , silver sulfide (AgS) , copper sulfide (CuS) , silver selenide (AgSe) , copper selenide (CuSe) , in contact with a solid electrolyte, such as germanium selenide (GeSe) , germanium sulfide (GeS) , silver selenide (AgSe) , silver sulfide (AgS) , or copper telluride (CuTe) .

In some implementations, each PCM string 220 further includes a plurality of PCM structures 212 laterally between selector layer 218 and word line layers 226, respectively, in the x-direction and/or y-direction. As shown in FIG. 2C, each PCM structure 212 is recessed from the sidewall of the hole of PCM string 220 into a respective word line layer 226, according to some implementations. In some implementations, like word line layers 226, PCM structures 212 are also separated by dielectric layers 208 in the z-direction. As shown in FIG. 2C, separated PCM structures 212 can be in contact with continuous selector layer 218 in each PCM string part 2201.

In some implementations, as shown in FIG. 2C, parts of selector layer 218 that are in contact with PCM structures 212 may be viewed as selectors 213 of PCM cells 211 in the present disclosure. That is, selector layer 218 can include a plurality of selectors 213 in contact with PCM structures 212, respectively. Each selector 213 can be part of continuous selector layer 218. Each PCM structure 212 can be formed between a respective word line of word line layer 226 and a respective selector 213 in the x-direction and/or y-direction.

As described above, each PCM string 220 can include a plurality of PCM cells 211 stacked in the z-direction. In some implementations, each PCM cell 211 includes a PCM structure 212 and a selector 213, i.e., part of selector layer 218 in contact with the respective PCM structure 212, that is in contact with PCM structure 212. As shown in FIG. 2C, each PCM cell 211 of PCM string 220 is disposed at an intersection of local bit line 231 of PCM string 220, a respective word line of word line layer 226, and isolation structure 214, according to some implementations. In some implementations as shown in FIG. 2C, each PCM structure 212 includes a PCM element 216 in contact with a respective selector 213 in selector layer 218 and a respective word line in word line layer 226. PCM element 216 can include a phase change material. The phase change material may include chalcogenide-based alloys (chalcogenide glass) , such as germanium antimony telluride (GeSbTe or GST) alloy, or any other suitable phase-change materials. PCM element 216 can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase change materials based on heating and quenching of the phase change materials electrothermally. Electrical currents can be applied to switch the phase change material (or at least a fraction of it that blocks the current path) of PCM element 216 repeatedly between the two phases to store data. A single bit of data can be stored in each PCM cell 211 and can be written or read by varying the voltage applied to a respective selector 213.

As shown in FIG. 2C, 3D PCM devices 200 can further include a global bit line 233 extending in the y-direction (e.g., the bit line direction) and in contact with the plurality of local bit lines 231. That is, global bit lines 233 can be perpendicular to local bit lines 231, but in parallel with the word lines in word line layers 226. Global bit line 233 can include conductive materials including, but not limited to, W, Co, Cu, Al, doped polysilicon, silicides, or any combination thereof. In one example, global bit line 233 may include a metal, such as W. In some implementations, each 3D PCM device 200 can include two global bit lines 233 in contact with two local bit lines 231 of two respective

PCM string parts

2201 and 2202. By separating one PCM string 220 into two

PCM string parts

2201 and 2202 with the isolation structure 214, more bits can be stored in each PCM string 220.

FIG. 2D is a plan view of a cross-section of an exemplary 3D PCM device 200, according to some aspects of the present disclosure. FIG. 2D may be a plan view of a cross-section of 3D PCM device 200 along the BB plane in FIG. 2C. As shown in FIG. 2D, each PCM structure 212, in combination with the isolation structure 214, circumscribes selector layer 218, according to some implementations. Each PCM structure 212 can also be formed among the isolation structure 214, the selector layer 218, and the respective word line of word line layer 226 in the x-direction and/or y-direction. That is, each PCM structure 212 is interposed among the respective word line of word line layer 226, the selector layer 218, and the isolation structure 214 in the x-direction and/or y-direction. Also, as shown in FIG. 2D, the cross-section of local bit line 231 has a semicircular shape. The cross-section of selector layer 218 may have a semiring shape circumscribing the semicircular shape of local bit line 231. The cross-section of PCM structure 212, in combination with the isolation structure 214 and the local bit line 231, may circumscribe the semiring shape of selector layer 218.

FIG. 3A illustrates a plan view of a cross-section of an exemplary 3D PCM device 300, according to some aspects of the present disclosure. As shown in FIG. 3A, 3D PCM device 300 can include an array of PCM strings 320 and one or a plurality of slit structures 305. In some implementations, the isolation structure 336 is formed on both sides of the PCM string 320 and in line with the slit structure 305 in the x-direction. It is understood that the isolation structure 336 is not limited to form on two opposite sides of the PCM string 320 as shown in FIG. 3A and can be formed on any side of the PCM string 320. It is also not limited to include only two isolation structures 336 in each PCM string 320 and can include multiple isolation structures in each PCM string 320. Slit structures 305 can extend laterally in the x-direction to divide 3D PCM device 300 into multiple regions in the y-direction, such as blocks, fingers, pages, etc., each of which includes multiple PCM strings 320. Each PCM string may include a plurality of PCM string parts, or a plurality of PCM cells. Each region may correspond to the smallest unit by a memory operation for 3D PCM device 300, such as read, program (write) , or erase, in different examples. As a result, the 3D PCM device 300 may not need additional slit structures to define regions. In some implementations, the slit structure 305 may be used to replace the sacrificial layers with word line layers by processes including removing the sacrificial layers with an etch process and depositing the word line layers through the slit structure. In some implementations, the word lines of 3D PCM device 300 extend laterally in the x-direction, and the global bit lines of 3D PCM device 300 extend laterally in the y-direction, which is perpendicular to the x-direction. That is, in the present disclosure, the x-direction may correspond to the word line direction, and the y-direction may correspond to the global bit line direction.

FIG. 3B illustrates a side view of a cross-section of an exemplary 3D PCM device 300, according to some aspects of the present disclosure. In some implementations, 3D PCM device 300 is an example of 3D PCM device 300 in FIG. 3A, and the cross-section of 3D PCM device 300 is along the AA plane of 3D PCM device 300 in FIG. 3A. As shown in FIG. 3B, 3D PCM device 300 can include a substrate 302, which can include silicon (e.g., single crystalline silicon) , silicon germanium (SiGe) , gallium arsenide (GaAs) , germanium (Ge) , silicon on insulator (SOI) , germanium on insulator (GOI) , or any other suitable materials. In some implementations, substrate 302 is a thinned substrate (e.g., a semiconductor layer) , which was thinned by grinding, wet/dry etching, chemical mechanical polishing (CMP) , or any combination thereof. In some implementations, the substrate 302 may be removed by a lift-off process, and the 3D PCM device 300 may be adhered to another permanent substrate (not shown) by a wafer bonding process.

In some implementations, one or more peripheral devices (not shown) are formed on and/or in substrate 302. The peripheral devices can include any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D PCM device 300. For example, the peripheral devices can include one or more of a data buffer, a decoder (e.g., a row decoder and a column decoder) , a sense amplifier, a driver, a charge pump, a current or voltage reference, or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors) .

3D PCM device 300 can also include a memory array device formed on substrate 302, such as an array of PCM strings 320, as shown in FIG. 3A. As used herein, whether one component (e.g., a layer or a device) is “on, ” “above, ” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D PCM device 300) is determined relative to the substrate of the semiconductor device (e.g., substrate 302) in the z-direction (i.e., the vertical direction) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing spatial relationships is applied throughout the present disclosure.

In some implementations, PCM cells 311 of 3D PCM device 300 are stacked vertically and provided in each PCM string 320. That is, each PCM string 320 can include a plurality of vertically stacked PCM cells 311. As shown in FIG. 3B, PCM string 320 can extend in the z-direction (vertical direction) through interleaved conductive layers 326 and dielectric layers 308 (also referred to herein as “conductive/dielectric layer pairs” ) . The interleaved conductive layers 326 and dielectric layers 308 are also referred to herein as a stack structure 324. The number of the conductive/dielectric layer pairs in stack structure 324 can set the number of PCM cells 311 in 3D PCM device 300. Conductive layers 326 and dielectric layers 308 in stack structure 324 can alternate in the vertical direction. In other words, except the ones at the top and the bottom of stack structure 324, each conductive layer 326 can be adjoined by two dielectric layers 308 on both sides, and each dielectric layer 308 can be adjoined by two conductive layers 326 on both sides. Conductive layers 326 can each have the same thickness or have different thicknesses. Similarly, dielectric layers 308 can each have the same thickness or have different thicknesses. Conductive layers 326 can include conductive materials including, but not limited to, tungsten (W) , cobalt (Co) , copper (Cu) , aluminum (Al) , polycrystalline silicon (polysilicon) , doped silicon, silicides, or any combination thereof. Dielectric layers 308 can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

Each conductive layer 326 can extend laterally (e.g., in the x-direction/word line direction) and include one or more word lines of 3D PCM device 300. Thus, conductive layer 326 is also referred to herein as a word line layer 326. That is, stack structure 324 can include interleaved word line layers 326 and dielectric layers 308. In some implementations, 3D PCM device 300 includes a plurality of silt structures (not shown in FIG. 3B, e.g., 305 in FIG. 3A) , each of which is filled with one or more dielectric materials and extends through stack structure 324 in the z-direction. That is, each word line layer 326 can include multiple word lines separated by slit structures in the x-direction/global bit line direction (e.g., 305 in FIG. 3A) , such that each region can include a respective one of the word lines. As shown in FIG. 3B, word line layers 326 (and word lines therein) are parallel to one another, as well as to the top surface of substrate 302, according to some implementations. In some implementations, edges of word line layers 326 are staggered at one or more sides of 3D PCM device 300 to define one or more staircase structures (not shown) for landing on word line contacts.

As shown in FIG. 3B, each PCM string 320 can extend vertically through stack structure 324 above substrate 302. In some implementations, PCM string 320 includes a hole in which a local bit line 331 and a selector layer 318 are formed. Local bit line 331 can include conductive materials including, but not limited to, W, Co, Cu, Al, doped polysilicon, silicides, or any combination thereof. In one example, local bit line 331 may include a metal, such as W. 3D PCM device 300 thus can include an array of parallel local bit lines 331 each extending vertically in the z-direction. Different from 3D XPoint memory device 100 in which bit lines 102/104 and word lines 106 all extend laterally and parallel to one another, in 3D PCM device 300, local bit lines 331 are perpendicular to the word lines in word line layers 326. As shown in FIG. 3B, 3D PCM device 300 can also include a plurality of global bit lines 333 in contact with respective local bit lines 331.

As shown in FIG. 3B, selector layer 318 can be a continuous layer formed along the sidewall and the bottom surface of the hole. That is, in some implementations, selector layer 318 circumscribes local bit line 331. Part of selector layer 318 on the bottom surface of the hole can also separate local bit line 331 from substrate 302 to provide insulation. In the plan view, the cross-section of local bit line 331 has a circular shape, and the cross-section of selector layer 318 has a ring shape circumscribing the circular shape of local bit line 331, according to some implementations. Also, in the plan view, selector layer 318 can include a threshold switch material that exhibits a resistance switching behavior when an external bias voltage higher than the threshold voltage is applied. In some implementations, the threshold switch material includes ovonic threshold switch (OTS) materials, such as zinc telluride (ZnTe) , germanium telluride (GeTe) , niobium oxide (NbO) , or silicon arsenic telluride (SiAsTe) , which exhibits a field-dependent volatile resistance switching behavior (known as “OTS phenomenon” ) when an external bias voltage higher than the threshold voltage is applied. In some implementations, the threshold switch material includes metal filament threshold switch (MFTS) materials, such as a metal ion reservoir for supplying metal ions, such as silver (Ag) , copper (Cu) , silver sulfide (AgS) , copper sulfide (CuS) , silver selenide (AgSe) , copper selenide (CuSe) , in contact with a solid electrolyte, such as germanium selenide (GeSe) , germanium sulfide (GeS) , silver selenide (AgSe) , silver sulfide (AgS) , or copper telluride (CuTe) .

In some implementations, each PCM string 320 further includes a plurality of PCM structures 312 laterally among selector layer 318, word line layers 326, and isolation structure 336, respectively, in the x-direction and/or y-direction. As shown in FIG. 3B, each PCM structure 312 is recessed from the sidewall of the hole of PCM string 320 into a respective word line layer 326, according to some implementations. In some implementations, like word line layers 326, PCM structures 312 are also separated by dielectric layers 308 in the z-direction. As shown in FIG. 3B, separated PCM structures 312 can be in contact with continuous selector layer 318 in each PCM string 320. Each PCM structure 312 shown in FIG. 3B, in combination with the isolation structure 336 shown in FIG. 3A, circumscribes selector layer 318 shown in FIG. 3B, according to some implementations. For example, in the plan view, the cross-section of selector layer 318 may have a ring shape, and the cross-section of PCM structure 312, in combination with the isolation structure 336, may also form a ring shape circumscribing the ring shape of selector layer 318. Parts of selector layer 318 that are in contact with PCM structures 312 may be viewed as selectors 313 of PCM cells 311 in the present disclosure. That is, selector layer 318 can include a plurality of selectors 313 in contact with PCM structures 312, respectively. Each selector 313 can be part of continuous selector layer 318. Each PCM structure 312 can be formed between a respective word line of word line layer 326, a respective selector 313 in the x-direction and/or y-direction. Each PCM structure 312 can also be formed between two isolation structures 336 in the x-direction and/or y-direction. That is, each PCM structure 312 is surrounded among the respective word line of word line layer 326, the respective selector of the selector layer 318, and two isolation structures 336 in a lateral direction. And each PCM structure 312 is surrounded between the dielectric layers 308 in a vertical direction. In some implementations, the isolation structure 336 can include any suitable materials, such as silicon oxide, silicon nitride, silicon oxynitride, or other insulation material.

As described above, each PCM string 320 can include a plurality of PCM cells 311 stacked in the z-direction. In some implementations, each PCM cell 311 includes two PCM cell parts (not shown) , each having a PCM structure 312 and a selector 313, i.e., part of selector layer 318 in contact with the respective PCM structure 312, that is in contact with PCM structure 312. As shown in FIG. 3B, each PCM cell part of PCM cell 311 is disposed at an intersection of local bit line 331 of PCM string 320, and a respective word line of word line layer 326. As shown in FIG. 3C, each PCM cell part of PCM cell 311 is further disposed at an intersection of two isolation structures 336, according to some implementations. In some implementations as shown in FIG. 3B, each PCM structure 312 includes a PCM element 316 in contact with a respective selector 313 in selector layer 318 and a respective word line in word line layer 326. PCM element 316 can include a phase change material. The phase change material may include chalcogenide-based alloys (chalcogenide glass) , such as germanium antimony telluride (GeSbTe or GST) alloy, or any other suitable phase-change materials. PCM element 316 can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase change materials based on heating and quenching of the phase change materials electrothermally. Electrical currents can be applied to switch the phase change material (or at least a fraction of it that blocks the current path) of PCM element 316 repeatedly between the two phases to store data. A single bit of data can be stored in each PCM cell part of PCM cell 311 and can be written or read by varying the voltage applied to a respective selector 313. That is, each PCM cell 311 can store two bits in some implementations.

As shown in FIG. 3B, 3D PCM devices 300 can further include a global bit line 333 extending in the y-direction (e.g., the bit line direction) and in contact with the plurality of local bit lines 331. That is, global bit lines 333 can be perpendicular to local bit lines 331, but in parallel with the word lines in word line layers 326. Global bit line 333 can include conductive materials including, but not limited to, W, Co, Cu, Al, doped polysilicon, silicides, or any combination thereof. In one example, global bit line 333 may include a metal, such as W. In some implementations, each 3D PCM device 300 can include one global bit line 333 in contact with one local bit line 331 of respective PCM string 320.

FIG. 3C illustrates a side view of a cross-section of an exemplary 3D PCM device 300, according to some aspects of the present disclosure. In some implementations, 3D PCM device 300 is an example of 3D PCM device 300 in FIG. 3A, and the cross-section of 3D PCM device 300 is along the BB plane of 3D PCM device 300 in FIG. 3A. From the side view of this cross-section along the BB plane, the isolation structures 336 is coupled to sidewalls of the selector layer 318. The selector layer 318 circumscribes the local bit line 331. In a plan view, these two isolation structures 336 separate each PCM cell 311 into two PCM cell parts in the lateral direction. By separating one PCM cell 311 into two PCM cell parts with the isolation structures 336, more bits can be stored in each PCM string 320.

FIG. 8 illustrates a block diagram of an exemplary system 800 having a 3D memory device, according to some aspects of the present disclosure. System 800 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown in FIG. 8, system 800 can include a host 808 and a memory system 802 having one or more 3D memory devices 804 and a memory controller 806. Host 808 can be a processor of an electronic device, such as a central processing unit (CPU) , or a system-on-chip (SoC) , such as an application processor (AP) . Host 808 can be configured to send or receive data to or from 3D memory devices 804.

3D memory device 804 can be any 3D memory device disclosed herein, such as

3D PCM devices

200 and 300 shown in FIGs. 2A–3C. Consistent with the scope of the present disclosure, a novel architecture of

3D PCM devices

200 and 300 is provided to reduce the manufacturing cost and achieve a higher memory density. As a result, the 3D PCM devices disclosed herein can provide more flexible scaling and cost reduction than conventional 3D XPoint memory devices.

Memory controller 806 (a.k.a., a controller circuit) is coupled to 3D memory device 804 and host 808 and is configured to control 3D memory device 804, according to some implementations. For example, memory controller 806 may be configured to control operations of PCM cells 211 through local bit line 231 and the word lines of word line layers 226. Memory controller 806 can manage the data stored in 3D memory device 804 and communicate with host 808. In some implementations, memory controller 806 is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller 806 is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller 806 can be configured to control operations of 3D memory device 804, such as read, erase, and program operations. Memory controller 806 can also be configured to manage various functions with respect to the data stored or to be stored in 3D memory device 804 including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller 806 is further configured to process error correction codes (ECCs) with respect to the data read from or written to 3D memory device 804. Any other suitable functions may be performed by memory controller 806 as well, for example, formatting 3D memory device 804. Memory controller 806 can communicate with an external device (e.g., host 808) according to a particular communication protocol. For example, memory controller 806 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

Memory controller 806 and one or more 3D memory devices 804 can be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory system 802 can be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 9A, memory controller 806 and a single 3D memory device 804 may be integrated into a memory card 902. Memory card 902 can include a PC card (PCMCIA, personal computer memory card international association) , a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro) , an SD card (SD, miniSD, microSD, SDHC) , a UFS, etc. Memory card 902 can further include a memory card connector 904 electrically coupling memory card 902 with a host (e.g., host 808 in FIG. 8) . In another example as shown in FIG. 9B, memory controller 806 and multiple 3D memory devices 804 may be integrated into an SSD 906. SSD 906 can further include an SSD connector 908 electrically coupling SSD 906 with a host (e.g., host 808 in FIG. 8) . In some implementations, the storage capacity and/or the operation speed of SSD 906 is greater than those of memory card 902.

FIGs. 4A-4E illustrate PCM cell array layouts of various exemplary

3D PCM devices

450, 451, 452, 453, and 454, according to various aspects of the present disclosure. As shown in FIG. 4A, a 3D PCM device 450 can include a plurality of PCM strings 402 (corresponding to PCM strings 220 in FIG. 2A) , and a plurality of slit structures 405 (e.g., corresponding to slit structure 205 in FIG. 2A) each extending in the x-direction (e.g., the word line direction) to divide 3D PCM devices 450 into a plurality of fingers 406 (a.k.a. pages) . As described above, each slit structure 405 can also extend in the z-direction to separate each word line layer 226 into separated word lines. In other words, each word line in a respective finger 406 can be individually addressed and controlled, by for example, by applying a respective word line voltage. In some implementations, the plurality of PCM strings 402 may be placed in a staggered arrangement rather than inline arrangement. This will increase the memory density of the 3D PCM device 450, or have thermal consideration including heat dissipation at critical point, thereby enhancing the performance and reliability.

As shown in FIG. 4A, 3D PCM device 450 can also include a plurality of global bit lines 408 (e.g., corresponding to global bit line 233 in FIG. 2C) each extending in the y-direction (e.g., the bit line direction) . In some implementations as shown in FIG. 4A, each global bit line 408 is electrically connected to a plurality of PCM strings 402 in different fingers 406; in each finger 406, a PCM string 402 can be electrically connected to two global bit lines 408 rather than one because of the isolation structure 414 splitting the PCM string into two PCM string parts (e.g., corresponding to

PCM string parts

2201, and 2202 in FIG. 2C) . Global bit line 408 may be in contact with a local bit line 410 (e.g., corresponding to local bit line 231 in FIGs. 2C) via a contact point 412. Each local bit line 410 in one finger 406 is electrically connected to another local bit line 410 in a different finger 406, but not in the same finger 406, through a respective global bit line 408, according to some implementations. In some implementations, each local bit line 410 in the same finger 406 is electrically connected to a different global bit line 408. As a result, the number of global bit lines 408 can be twice as many as that of PCM strings 402 in each finger 406. This doubles the bits the 3D PCM device 450 can store in one PCM string 402. Similar to the word lines, each global bit line 408 can be individually addressed and controlled, for example, by applying a respective bit line voltage.

In some implementations, to select a specific PCM cell (in the dashed circle in FIG. 4A) in any suitable memory operation (e.g., read, write, or erase) , a selected global bit line 408 electrically connected the selected PCM cell is biased at a bit line voltage of Vhh, while unselected global bit lines 408 are biased at a bit line voltage of 0 V. As a result, local bit lines 410 in different fingers 406 that are in contact with selected global bit line 408 can also be biased at Vhh. On the other hand, a selected word line electrically connected to the selected PCM cell is biased at a word line voltage of -Vll, while unselected word lines in different word line layers (e.g., at different levels in the z-direction) or unselected word lines in the same word line layer (e.g., at the same level as the selected word line) but in different fingers 406 are biased at a word line voltage of 0 V, according to some implementations. As a result, only one PCM cell (in the dashed circle in FIG. 4A) is biased at a voltage of Vhh+Vll between the selected word line and the selected global bit line 408 and thus, become the selected PCM cell. In contrast, other PCM cells are biased at either Vhh, Vll, or 0 voltage and thus, are not selected.

It is understood that the number of PCM strings 402 in each finger 406 and the number of global bit lines 408 may vary in different examples. For example, as shown in FIG. 4A, each finger 406 may include 5 PCM strings 402 electrically connected to 10 global bit lines 408, and each PCM string 402 may be overlapped with two global bit lines 408.

In another example as shown in FIG. 4B, a 3D PCM device 451 may include 10 PCM strings 402 in each finger 406 that are electrically connected to 20 global bit lines 408, respectively, and each PCM string 402 may be overlapped with three global bit lines 408. Two of global bit lines 408 are electrically connected to two respective contact points 412 of each PCM string 402 while one of the global bit lines 408 is formed above isolation structure 414. It is noted that the isolation structure 414 may be slightly shifted to enable contact pitch shrink.

In another examples shown in FIG. 4C, the 3D PCM device 452 includes the first isolation structure 414 and the second isolation structure 416 perpendicular to the first isolation structure 414 in the second direction. The first isolation structure 414 and the second isolation structure 416 separate the PCM string 402 into four PCM string parts. Each PCM string part is electrically connected to one global bit line 408 via the contact point 412. In this example, each finger 406 may include 5 PCM strings 402 including 20 PCM string parts electrically connected to 20 global bit lines 408, and each PCM string 402 may be overlapped with four global bit lines 408. Each local bit line 410 in one finger 406 is electrically connected to another local bit line 410 in a different finger 406, but not in the same finger 406, through a respective global bit line 408, according to some implementations. In some implementations, each local bit line 410 in the same finger 406 is electrically connected to a different global bit line 408. As a result, the number of global bit lines 408 can be four times as many as the number of PCM strings 402 in each finger 406. That is, since the PCM string 402 is divided into four PCM string parts, this quadruples the bits the 3D PCM device 450 can store in one PCM string 402.

In yet another examples shown in FIG. 4D, each 3D PCM device 453 includes a first isolation structure 474 and a second isolation structure 476 perpendicular to the first isolation structure 474 in the second direction. The first isolation structure 474 and the second isolation structure 476 separate each PCM string 462 into four PCM string parts. Each PCM string part is electrically connected to one global bit line 468 via the contact point 472. In some implementations, the second isolation structure 476 extending in the first direction (e.g., the x-direction) forms a common isolation structure overlapping a plurality of PCM string 462 in the first direction. In the example of FIG. 4D, the slit structure is not necessarily needed since two of the adjacent common isolation structures 476 already form a finger 466. The two adjacent common isolation structures 476 define the region of the finger 466, which is one of the functions the slit structures provide. And the plurality of PCM string parts is separated by the first isolation structure 474 and the common isolation structure 476. In this example, each finger 466 may include two and a half PCM string 462 (i.e., five half a PCM string 462) including 10 PCM string parts electrically connected to 10 global bit lines 468. Each local bit line 470 in one finger 466 is electrically connected to another local bit line 470 in a different finger 466, but not in the same finger 466, through a respective global bit line 468, according to some implementations. Since the PCM string 462 is divided into four PCM string parts, this quadruples the bits the 3D PCM device 453 can store in one PCM string 462. Similar to the word lines, each global bit line 468 can be individually addressed and controlled, for example, by applying a respective bit line voltage.

In yet another example shown in FIG. 4E, the 3D PCM device 454 includes a slit structure 485 extending in the first direction (e.g., the x-direction) and perpendicular to the global bit line 488. The slit structure 485 separates the PCM string 482 into two PCM string parts. Each PCM string part is electrically connected to one global bit line 488 via the contact point 492. In this example, each finger 486 may include two and a half PCM strings 482 (i.e., five half a PCM string 482) electrically connected to 5 global bit lines 488, and each PCM string 482 may be overlapped with one global bit lines 488. Each local bit line 490 in one finger 486 is electrically connected to another local bit line 490 in a different finger 486, but not in the same finger 486, through a respective global bit line 488, according to some implementations. In some implementations, each local bit line 490 in the same finger 486 is electrically connected to a different global bit line 488. This architecture replaces the isolation structure with the slit structure to separate the PCM string 482 into two PCM string parts. As a result, the number of global bit lines 488 can be the same as the number of PCM strings 482 in each finger 486 while no isolation structure is needed.

FIGs. 5A–5H illustrate an exemplary fabrication process for forming a 3D PCM device, according to some implementations of the present disclosure. FIG. 7A illustrates a flowchart of an exemplary method 700 for forming a 3D PCM device, according to some implementations of the present disclosure. Examples of the 3D PCM device depicted in FIGs. 5A-5H and 7A include 3D PCM devices 200 depicted in FIGs. 2A-2D. FIGs. 5A-5H and 7A will be described together. It is understood that the operations shown in method 700 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 7A.

In some implementations, to form the 3D memory device, a stack structure including interleaved a plurality of conductive layers and a plurality of dielectric layers is formed on the substrate. A PCM string is formed extending through the stack structure in the vertical direction. Each PCM string can include two PCM string parts separated by an isolation structure. Each PCM string part can include a plurality of vertically stacked PCM cells. From a side view of a cross-section of the 3D memory device, each PCM string includes an isolation structure, two selector layer circumscribing the isolation structure, two local bit lines circumscribing the selector layer, two selector layer circumscribing the local bit line, and a plurality of PCM structures between the selector layer and the plurality of conductive layers, respectively, in the lateral direction.

Referring to FIG. 7A, method 700 starts at operation 702, in which an isolation structure is deposited on a substrate. As shown in FIG. 5A, the isolation structure 514 is formed on the substrate 502. In some implementations, the isolation structure 514 can be deposited as a stack shape and then etched to form a pillar shape by a lithography process. In some implementations, the isolation structure 514 can be deposited using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD) , physical vapor deposition (PVD) , atomic layer deposition (ALD) , electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof.

Method 700 proceeds to operation 704, as illustrated in FIG. 7A, a plurality of sacrificial layers and a plurality of dielectric layers are alternatingly deposited on the substrate and surrounding the isolation structure. As shown in FIG. 5A, dielectric layers 508 and sacrificial layers 506 are alternatingly deposited on the substrate 502 and surrounding the isolation structure 514 to form a sacrificial stack 504. Dielectric layers 508 can include any suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high-k) dielectric, and sacrificial layers 506 can include any suitable materials different from dielectric layers 508. In one example, each dielectric layer 508 may include a layer of silicon oxide, and each sacrificial layer 506 may include a layer of silicon nitride. In another example, each dielectric layer 508 may include a layer of silicon nitride, and each sacrificial layer 506 may include a layer of polysilicon. Sacrificial stack 504 can be formed using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD) , physical vapor deposition (PVD) , atomic layer deposition (ALD) , electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof.

Although not shown, a staircase structure can be formed on the edge of sacrificial stack 504. The staircase structure can be formed by performing a plurality of so-called “trim-etch” cycles to each pair of dielectric layer 508 and sacrificial layer 506 of sacrificial stack 504 toward substrate 502. Due to the repeated trim-etch cycles applied to the pairs of dielectric layer 508 and sacrificial layer 506, sacrificial stack 504 can have one or more tilted edges of dielectric layer 508 and sacrificial layer 506 in the staircase structure.

Method 700 proceeds to operation 706, as illustrated in FIG. 7A, in which a hole is etched extending through the plurality of sacrificial layers and the plurality of dielectric layers in the vertical direction and exposing the isolation structure. As illustrated in FIG. 5B, each hole 510 is an opening extending vertically through interleaved dielectric layers 508 and sacrificial layers 506 of sacrificial stack 504, stopping at substrate 502 while leaving the isolation structure 514 in the hole 510 and exposed after the etch process. In some implementations, a plurality of holes 510 are formed, such that each hole 510 becomes the location for forming an individual PCM string in the later process. In some implementations, as shown in FIG. 2A, the isolation structure 214 protrudes out of the hole in a plan view. That is, the longitude of the isolation structure 214 (i.e., corresponding to the isolation structure 514) is longer than the diameter of the hole 510. As such, the protruding part of the isolation structure 214 into the stack structure 224 may separate the PCM element 216 into two PCM element parts. In some implementations, fabrication processes for forming holes 510 include wet etching and/or dry etching, such as deep RIE (DRIE) . The etching of the channel holes continues until being stopped by substrate 502, according to some implementations. It is understood that depending on the specific etching selectivity, one or more holes 510 may extend further into substrate 502 to a certain degree.

Method 700 proceeds to operation 708, as illustrated in FIG. 7A, in which part of each of the plurality of sacrificial layers is replaced with a respective one of the plurality of PCM structures through the hole. In some implementations, to replace the part of each sacrificial layer with the respective PCM structure, the plurality of sacrificial layers is etched back through the hole to form a plurality of recesses, and a plurality of PCM elements is formed in the plurality of recesses, respectively, through the hole. To form the plurality of PCM elements, a PCM layer may be deposited in the plurality of recesses and along a sidewall of hole, and the PCM layer may be etched back to remove parts of the PCM layer along the sidewall of the hole. The PCM element can include a phase change material.

As illustrated in FIG. 5C, part of each sacrificial layer 506 is replaced with a respective PCM element 512 through hole 510. Sacrificial layers 506 can be etched back using dry etching and/or wet etching to form recesses. A wet etchant having a high selectivity (e.g., greater than 5) of sacrificial layers 506 against dielectric layers 508, substrate 502, and isolation structure 514 can be applied into hole 510 to etch sacrificial layers 506. The etch rate and/or etch time can be controlled to partially etch sacrificial layers 506 to form the recesses. In some implementations, a PCM layer, such as a layer of phase change material (e.g., chalcogenide-based alloys) , is then deposited into the recesses and along the sidewall of hole 510 through hole 510 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof. The PCM layer can then be etched back using dry etching and/or wet etching to remove parts of the PCM layer along the sidewall of hole 510. As a result, the remainders of the PCM layer in the recesses can become separate PCM elements 512 in the recesses, which replace parts of sacrificial layers 506.

Method 700 proceeds to operation 710, as illustrated in FIG. 7A, in which a selector layer is deposited along a sidewall and a bottom surface of the hole, and a sidewall of the isolation structure. The selector layer can include a threshold switch material. As illustrated in FIG. 5D, a selector layer 518 is deposited along the sidewall and the bottom surface of hole 510, and a sidewall of the isolation structure 514, such that selector layer 518 is in contact with recessed PCM elements 512. Selector layer 518 can be formed by depositing a layer of threshold switch material into 510 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof. The deposition may be performed using a conformal deposition technique, such as CVD or ALD, to partially fill hole 510 along the sidewall and the bottom surface thereof. In one example, a layer of OTS material, such as ZnTe, GeTe, NbO, or SiAiTe, may be deposited as selector layer 518. In another example, a metal ion reservoir layer including Ag, Cu, AgS, CuS, AgSe, CuSe, or any combinations thereof, and a solid electrolyte layer including GeSe, GeS, AgSe, AgS, CuTe, or any combination thereof, may be deposited as selector layer 518.

Method 700 proceeds to operation 712, as illustrated in FIG. 7A, in which a local bit line layer 520’ is deposited over the selector layer in the hole. As illustrated in FIG. 5E, a local bit line layer 520’ is deposited over selector layer 518 in hole 510.

Method 700 proceeds to operation 714, as illustrated in FIG. 7A, in which a local bit line 520 is formed by performing a chemical mechanical polishing (CMP) process on a surface of the local bit line layer 520’. As illustrated in FIG. 5F, a local bit line 520 is formed over selector layer 518 in hole 510. In some implementations, since the isolation structure 514 separates the hole 510 into two hole parts, two local bit lines 520 are deposited over two respective selector layers in the two hole parts accordingly. A conductive material, such as W, can be deposited over selector layer 518 to fill hole 510 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof, followed by a CMP process, to form local bit line 520.

Method 700 proceeds to operation 716, as illustrated in FIG. 7A, in which a slit structure is etched extending through the plurality of sacrificial layers and the plurality of dielectric layers in the vertical direction. Similar to hole 510, the slit structure (not shown) may be formed vertically through interleaved sacrificial layers 506 and dielectric layers 508 of sacrificial stack 504 using dry etching and/or wet etching, such as DRIE.

Method 700 proceeds to operation 718, as illustrated in FIG. 7A, in which the plurality of sacrificial layers are replaced with the plurality of conductive layers, respectively, through the slit structure. As illustrated in FIG. 5G, sacrificial layers 506 (e.g., shown in FIG. 5F) are removed to form a plurality of recesses 522 between dielectric layers 508. In some implementations, a wet etchant having a high selectivity (e.g., above 5) of sacrificial layers 506 against dielectric layers 508 and PCM elements 512 is applied through the slit structure to etch away sacrificial layers 506. As illustrated in FIG. 5H, conductive layers 526 are deposited into recesses 522 (e.g., shown in FIG. 5G) between dielectric layers 508. In some implementations, a conductive material, such as W, is deposited to fill recesses 522 through the slit structure using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof. As a result, a stack structure 524 including interleaved conductive layers 526 and dielectric layers 508 can be formed to replace sacrificial stack 504 (e.g., shown in FIG. 5H) .

It is understood that although not shown, in some examples, stack structure 524 may be formed first prior to the formation of holes 510. For example, conductive layers 526 and dielectric layers 508 may be alternatingly deposited on substrate 502 to form stack structure 524, and holes 510 then may be etched through interleaved conductive layers 526 and dielectric layers 508 of stack structure 524, as opposed to sacrificial stack 504. The PCM structures may be recessed back into conductive layers 526 to replace parts of conductive layers, instead of sacrificial layers 506. The replacement of sacrificial layers 506 with conductive layers 526 may be omitted as well.

FIGs. 6A–6H illustrate an exemplary fabrication process for forming a 3D PCM device, according to some implementations of the present disclosure. FIG. 7B illustrates a flowchart of an exemplary method 750 for forming a 3D PCM device, according to some implementations of the present disclosure. Examples of the 3D PCM device depicted in FIGs. 6A-6H and 7B include 3D PCM devices 300 depicted in FIGs. 3A-3D. FIGs. 3A-3D, 6A-6H, and 7B will be described together. It is understood that the operations shown in method 750 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 7B.

In some implementations, to form the 3D memory device, a stack structure including interleaved a plurality of conductive layers and a plurality of dielectric layers is formed on the substrate. A PCM string is formed extending through the stack structure in the vertical direction. Each PCM string can include a plurality of PCM structures separated by isolation structures. From a side view of a cross-section of the 3D memory device, each PCM string includes a local bit line, a selector layer circumscribing the local bit line, two isolation structures in combination with the stack structure circumscribing the selector layer, and a plurality of PCM structures among in intersection of the selector layer, the plurality of conductive layers, and the isolation structures, respectively, in the lateral direction.

Referring to FIG. 7B, method 750 starts at operation 752, in which a sacrificial isolation structure is deposited on a substrate. As shown in FIG. 6A and FIG. 6E, the sacrificial isolation structure 634 is formed on the substrate 602. In some implementations, the sacrificial isolation structure 634 can be deposited as a stack shape and then etched to form a pillar shape by a lithography process.

Method 750 proceeds to operation 754, as illustrated in FIG. 7B, a plurality of sacrificial layers and a plurality of dielectric layers are alternatingly deposited on the substrate and surrounding the sacrificial isolation structure. As shown in FIGs. 6A and 6E, dielectric layers 608 and sacrificial layers 606 are alternatingly deposited on the substrate 602 and surrounding the sacrificial isolation structure 634 to form a sacrificial stack 604. In some implementations, as shown in FIG. 6A, a plurality of sacrificial isolation structure is formed on the substrate, each sacrificial isolation structure is a strip shape in a plan view. In some implementations, dielectric layers 608 can include any suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high-k) dielectric, and sacrificial layers 606 can include any suitable materials different from dielectric layers 608. The sacrificial isolation structure 634 can include any suitable materials, such as silicon oxide, silicon nitride, silicon oxynitride, or other insulation material. In one example, each dielectric layer 608 may include a layer of silicon oxide, each sacrificial layer 606 may include a layer of silicon nitride, and the sacrificial isolation structure may include silicon oxide. In another example, each dielectric layer 608 may include a layer of silicon nitride, and each sacrificial layer 606 may include a layer of polysilicon. Sacrificial stack 604 can be formed using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD) , physical vapor deposition (PVD) , atomic layer deposition (ALD) , electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof.

Although not shown, a staircase structure can be formed on the edge of sacrificial stack 604. The staircase structure can be formed by performing a plurality of so-called “trim-etch” cycles to each pair of dielectric layer 608 and sacrificial layer 606 of sacrificial stack 604 toward substrate 602. Due to the repeated trim-etch cycles applied to the pairs of dielectric layer 608 and sacrificial layer 606, sacrificial stack 604 can have one or more tilted edges of dielectric layer 608 and sacrificial layer 606 in the staircase structure.

Method 750 proceeds to operation 756, as illustrated in FIG. 7B, in which a hole is etched extending through the sacrificial isolation structure and part of the sacrificial isolation structure in the vertical direction and exposing a sidewall of the isolation structure and a top surface of the substrate. As illustrated in FIGs. 6E and 6F, each hole 610 is an opening extending vertically through sacrificial isolation structure 634, stopping at substrate 602 while leaving the isolation structure 636 in the hole 610 and exposing a sidewall of the isolation structure 636 after the etch process. In some implementations, as shown in FIG. 6F, a plurality of holes 610 is formed, such that each hole 610 becomes the location for forming an individual PCM string in the later process. In some implementations, as shown in FIG. 3A, the isolation structure 336 is located out of the hole and embedded in the sacrificial structure stack in a plan view. In some implementations, fabrication processes for forming holes 610 include wet etching and/or dry etching, such as deep RIE (DRIE) . The etching of the channel holes continues until being stopped by substrate 602, according to some implementations. It is understood that depending on the specific etching selectivity, one or more holes 610 may extend further into substrate 602 to a certain degree.

Method 750 proceeds to operation 758, as illustrated in FIG. 7B, in which part of each of the plurality of sacrificial layers is replaced with a respective one of the plurality of PCM structures through the hole. In some implementations, to replace the part of each sacrificial layer with the respective PCM structure, the plurality of sacrificial layers are etched back through the hole to form a plurality of recesses, and a plurality of PCM structure are formed in the plurality of recesses, respectively, through the hole, except for those parts blocked by the isolation structures. To form the plurality of PCM structure, a PCM layer may be deposited in the plurality of recesses and along a sidewall of the hole, and the PCM layer may be etched back to remove parts of the PCM layer along the sidewall of the hole. The PCM structure can include a phase change material.

After forming the isolation structure 636, part of each sacrificial layer 606 is replaced with a respective PCM structure 312 (e.g., in FIG. 3B) through hole 610. To replace the sacrificial layer with PCM structure, sacrificial layers 606 can be etched back using dry etching and/or wet etching to form recesses. A wet etchant having a high selectivity (e.g., greater than 5) of sacrificial layers 606 against dielectric layers 608, substrate 602, and isolation structure 636 can be applied into hole 610 to etch sacrificial layers 606. The etch rate and/or etch time can be controlled to partially etch sacrificial layers 606 to form the recesses. In some implementations, a PCM layer, such as a layer of phase change material (e.g., chalcogenide-based alloys) , is then deposited into the recesses and along the sidewall of hole 610 through hole 610 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof. The PCM layer can then be etched back using dry etching and/or wet etching to remove parts of the PCM layer along the sidewall of hole 610. As a result, the remainders of the PCM layer in the recesses can become separate PCM structure 312 (e.g., in FIG. 3B) in the recesses, which replace parts of sacrificial layers 606.

Method 750 proceeds to operation 760, as illustrated in FIG. 7B, in which a selector layer is deposited along a sidewall and a bottom surface of the hole, which include a sidewall of the isolation structure, a sidewall of the sacrificial structure, and a top surface of the substrate. The selector layer can include a threshold switch material. As illustrated in FIG. 3B, a selector layer 318 is deposited along the sidewall of the stack structure 324, and the top surface of the substrate 302, such that selector layer 318 is in contact with recessed PCM structure 312. As illustrated in FIG. 3C, the selector layer 318 is also deposited along the sidewall of the isolation structure 336. Selector layer 318 can be formed by depositing a layer of threshold switch material into using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof. The deposition may be performed using a conformal deposition technique, such as CVD or ALD, to partially fill hole along the sidewall and the bottom surface thereof. In one example, a layer of OTS material, such as ZnTe, GeTe, NbO, or SiAiTe, may be deposited as selector layer 318. In another example, a metal ion reservoir layer including Ag, Cu, AgS, CuS, AgSe, CuSe, or any combinations thereof, and a solid electrolyte layer including GeSe, GeS, AgSe, AgS, CuTe, or any combination thereof, may be deposited as selector layer 318.

Method 750 proceeds to operation 762, as illustrated in FIG. 7B, in which a local bit line is deposited over the selector layer in the hole. As illustrated in cross-sections of FIG. 6G (and also in FIG. 3C) , a local bit line 631 is deposited over the sidewall of the isolation structure 636. From another cross-section as shown in FIG. 3B, the local bit line 331 (e.g., corresponding to local bit line 631 in FIG. 6G) is also deposited over selector layer 318. In some implementations, the isolation structure 336 in FIG. 3C separates the PCM structure 312 in FIG. 3B into two PCM structure parts in a lateral direction. A conductive material, such as W, can be deposited over selector layer 318 to fill hole using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof, followed by a CMP process, to form local bit line 331. In some implementations, a global bit line 333 is formed on the local bit line 331.

Method 750 proceeds to operation 764, as illustrated in FIG. 7B, in which a slit structure is etched extending through the plurality of sacrificial layers and the plurality of dielectric layers in the vertical direction. As shown in FIG. 6H, similar to hole 610 (e.g., in FIG. 6F) , a slit structure 605 may be formed vertically through interleaved sacrificial layers 606 (e.g., in FIG. 6G) and dielectric layers 608 (e.g., in FIG. 6G) of sacrificial stack 604 (e.g., in FIG. 6G) using dry etching and/or wet etching, such as DRIE, to remove part of the sacrificial stack 604. In some implementations, a plurality of the slit structure 605 (e.g., corresponding to slit structure 305 in FIGs. 3A and 3C) is formed between two adjacent isolation structures of two respective PCM strings in the x-direction. As shown in a plan view of FIG. 3A, these slit structures laterally connecting all adjacent PCM strings define the fingers. In some implementations, the slit structure is perpendicular to the global bit line. In some implementations, the slit structure has the same, or similar width compared with the isolation structure.

Method 750 proceeds to operation 766, as illustrated in FIG. 7B, in which the plurality of sacrificial layers are replaced with the plurality of conductive layers, respectively, through the slit structure. The sacrificial layers 606 shown in FIG. 6G are removed to form a plurality of recesses between dielectric layers. In some implementations, a wet etchant having a high selectivity (e.g., above 5) of sacrificial layers 606 against dielectric layers 608 and PCM structure 312 (e.g., in FIG. 3B) is applied through the slit structure to etch away sacrificial layers 606. After the etching process, as illustrated in FIG. 3B, conductive layers 326 are deposited into recesses between dielectric layers 308. In some implementations, a conductive material, such as W, is deposited to fill recesses through the slit structure using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof. As a result, a stack structure 324 including interleaved conductive layers 326 and dielectric layers 308 can be formed to replace sacrificial stack 604, as shown in FIG. 6G.

It is understood that although not shown, in some examples, stack structure 324 may be formed first prior to the formation of holes 610 (e.g., shown in FIG. 6F) . For example, conductive layers 326 and dielectric layers 308 may be alternatingly deposited on substrate 302 to form stack structure 324, and holes then may be etched through interleaved conductive layers 326 and dielectric layers 308 of stack structure 324, as opposed to sacrificial stack 604 (e.g., shown in FIG. 6F) . The PCM structures may be recessed back into conductive layers 326 to replace parts of conductive layers, instead of sacrificial layers 606. The replacement of sacrificial layers 606 with conductive layers 326 may be omitted as well.

According to one aspect of the present disclosure, a three-dimensional (3D) memory device includes a stack structure including interleaved a plurality of word line layers and a plurality of dielectric layers; and a plurality of phase-change memory (PCM) strings, each of the PCM strings extending through the stack structure in a first direction and including an isolation structure extending through the stack structure in the first direction; and a plurality of PCM string parts separated by the isolation structure, each PCM string parts including a local bit line, a selector layer circumscribing the local bit line, and a plurality of PCM structures between the selector layer and the plurality of word line layers.

In some implementations, the isolation structure extending in a second direction to separate the plurality of PCM string parts, wherein the second direction is perpendicular to the first direction.

In some implementations, the isolation structure includes a stripe shape in a plan view, and a number of the plurality of PCM string parts is two.

In some implementations, the isolation structure includes a cross shape in a plan view, and a number of the plurality of PCM string parts is four.

In some implementations, the 3D memory device further includes a global bit line extending in the second direction and in contact with a respective local bit line.

In some implementations, the 3D memory device further includes one or a plurality of slit structure extending through the stack structure in the first direction to separate each of the plurality of word line layers into a plurality of word lines.

In some implementations, the 3D memory device further includes a finger defined by two adjacent slit structures, each global bit line in contact with one respective PCM string part in each finger.

In some implementations, the selector layer includes a threshold switch material.

In some implementations, the plurality of PCM structures is separated by the plurality of dielectric layers in the first direction.

In some implementations, each of the plurality of PCM structures includes a PCM element.

In some implementations, the PCM element includes a phase change material.

In some implementations, a material of the isolation structure includes silicon oxide, silicon nitride, silicon oxynitride, or other insulation material.

According to another aspect of the present disclosure, a three-dimensional (3D) memory device includes a stack structure including interleaved a plurality of word line layers and a plurality of dielectric layers; and a plurality of phase-change memory (PCM) strings, each of the PCM strings extending through the stack structure in a first direction and including a local bit line extending in the first direction; a selector layer circumscribing the local bit line; a plurality of isolation structure extending in the first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and a plurality of PCM structures between the selector layer and the plurality of word line layers in the second direction, each of the plurality of PCM structures between two of the plurality of isolation structures in the second direction.

In some implementations, the 3D memory device further includes one or a plurality of slit structure, each formed between two isolation structures of two respective PCM strings.

In some implementations, the 3D memory device further includes a finger defined by two adjacent slit structures, and the global bit line is in contact with one respective PCM string in each finger.

In some implementations, each slit structure is filled with insulation material.

According to another aspect of the present disclosure, a system includes a three-dimensional (3D) memory device configured to store data, the 3D memory device including: a stack structure including interleaved a plurality of word line layers and a plurality of dielectric layers; and a plurality of phase-change memory (PCM) strings, each of the PCM strings extending through the stack structure in a first direction and including an isolation structure extending through the stack structure in the first direction; and a plurality of PCM string parts separated by the isolation structure, each PCM string part including a local bit line, a selector layer circumscribing the local bit line, and a plurality of PCM structures between the selector layer and the plurality of word line layers; and a memory controller coupled to the 3D memory device and configured to control operations of the plurality of PCM cells through the local bit line and the plurality of word lines.

According to another aspect of the present disclosure, a system includes a three-dimensional (3D) memory device configured to store data, the 3D memory device including a stack structure including interleaved a plurality of word line layers and a plurality of dielectric layers; and a plurality of phase-change memory (PCM) strings, each of the PCM strings extending through the stack structure in a first direction and including a local bit line extending in the first direction; a selector layer circumscribing the local bit line; a plurality of isolation structure extending in the first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and a plurality of PCM structures between the selector layer and the plurality of word line layers in the second direction, each of the plurality of PCM structures between two of the plurality of isolation structures in the second direction; and a memory controller coupled to the 3D memory device and configured to control operations of the plurality of PCM cells through the local bit line and the plurality of word lines.

According to yet another aspect of the present disclosure, a method for forming a three-dimensional (3D) memory device includes forming a stack structure including interleaved a plurality of conductive layers and a plurality of dielectric layers on a substrate; and forming a phase-change memory (PCM) string extending through the stack structure in a first direction, wherein the PCM string includes: an isolation structure extending through the stack structure in the first direction; a plurality of PCM string parts separated by the isolation structure, each PCM string parts including a local bit line structure extending in the first direction; a selector layer circumscribing a respective local bit line; and a plurality of PCM structures between the selector layer and the plurality of conductive layers, respectively.

In some implementations, forming the stack structure includes alternatingly depositing a plurality of sacrificial layers and the plurality of dielectric layers on the substrate; etching a slit structure extending through the plurality of sacrificial layers and the plurality of dielectric layers in the first direction; and replacing the plurality of sacrificial layers with the plurality of conductive layers, respectively, through the slit.

In some implementations, forming the PCM string includes forming an isolation structure on the substrate; etching a plurality of holes extending through the plurality of sacrificial layers, and the plurality of dielectric layers to expose the isolation structure; replacing part of each of the plurality of sacrificial layers with a respective one of the plurality of PCM structures through the holes; depositing a plurality of selector layers along respective sidewalls and bottom surfaces of the plurality of holes; and depositing a plurality of local bit lines over the respective selector layers in the plurality of holes.

In some implementations, replacing the part of each sacrificial layer with the respective PCM structure includes etching back the plurality of sacrificial layers through each hole to form a plurality of recesses; and forming the respective one of the plurality of PCM structure in the plurality of recesses, respectively, through each hole.

In some implementations, forming the plurality of PCM structures includes depositing a PCM layer in the plurality of recesses and along a sidewall of the holes; and etching back the PCM layer to remove parts of the PCM layer along the sidewall of the holes.

In some implementations, the PCM structure includes a phase change material.

In some implementations, the method further includes forming a global bit line extending above and in contact with the local bit line.

According to yet another aspect of the present disclosure, a method for forming a three-dimensional (3D) memory device includes forming a stack structure including interleaved a plurality of conductive layers and a plurality of dielectric layers on a substrate; and forming a plurality of phase-change memory (PCM) strings extending through the stack structure in a first direction, each PCM string including a local bit line extending in the first direction; a selector layer circumscribing the local bit line; a plurality of isolation structures extending in the first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and a plurality of PCM structures between the selector layer and the plurality of conductive layers in the second direction, the plurality of PCM structures between two of the plurality of isolation structures in the second direction.

In some implementations, forming the stack structure includes alternatingly depositing a plurality of sacrificial layers and the plurality of dielectric layers on the substrate; etching a plurality of slit structures extending through the plurality of sacrificial layers and the plurality of dielectric layers in the first direction, each slit structure formed between two of the plurality of isolation structures of two adjacent PCM strings, respectively; and replacing the plurality of sacrificial layers with the plurality of conductive layers, respectively, through the slit structure.

In some implementations, forming the plurality of PCM string includes forming a plurality of sacrificial isolation structures on the substrate; etching a plurality of holes extending through the plurality of sacrificial layers, the plurality of dielectric layers, and part of each of plurality of sacrificial isolation structures to form the plurality of isolation structures; replacing part of each of the plurality of sacrificial layers with a respective one of the plurality of PCM structures through the holes; depositing a plurality of selector layers along respective sidewalls and bottom surfaces of the plurality of holes; and depositing a plurality of local bit lines over the respective selector layers in the plurality of holes.

In some implementations, the method further includes forming a plurality of global bit lines extending above and in contact with the respective local bit lines.

In some implementations, the plurality of slit structures are perpendicular to the plurality of global bit lines.

The foregoing description of the specific implementations will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications of such specific implementations, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations but should be defined only in accordance with the following claims and their equivalents.

Claims

A three-dimensional (3D) memory device, comprising:

a stack structure comprising interleaved a plurality of word line layers and a plurality of dielectric layers; and

a plurality of phase-change memory (PCM) strings, each of the PCM strings extending through the stack structure in a first direction and comprising:

an isolation structure extending through the stack structure in the first direction; and

a plurality of PCM string parts separated by the isolation structure, each PCM string part comprising a local bit line, a selector layer circumscribing the local bit line, and a plurality of PCM structures between the selector layer and the plurality of word line layers.
The 3D memory device of claim 1, wherein the isolation structure extending in a second direction to separate the plurality of PCM string parts, wherein the second direction is perpendicular to the first direction.
The 3D memory device of claim 1 or 2, wherein the isolation structure comprises a stripe shape in a plan view and a number of the plurality of PCM string parts is two.
The 3D memory device of claim 1 or 2, wherein the isolation structure comprises a cross shape in a plan view and a number of the plurality of PCM string parts is four.
The 3D memory device of any one of claims 2-4, further comprising a global bit line extending in the second direction and in contact with a respective local bit line.
The 3D memory device of any one of claims 1-5, further comprising one or a plurality of slit structure extending through the stack structure in the first direction to separate each of the plurality of word line layers into a plurality of word lines.
The 3D memory device of claim 6, further comprising a finger defined by two adjacent slit structures, each global bit line in contact with one respective PCM string part in each finger.
The 3D memory device of any one of claims 1-7, wherein the selector layer comprises a threshold switch material.
The 3D memory device of any one of claims 1-8, wherein the plurality of PCM structures is separated by the plurality of dielectric layers in the first direction.
The 3D memory device of any one of claims 1-9, wherein each of the plurality of PCM structures comprises a PCM element.
The 3D memory device of claim 10, wherein the PCM element comprises a phase change material.
The 3D memory device of any one of claims 1-11, wherein a material of the isolation structure comprises silicon oxide, silicon nitride, silicon oxynitride, or other insulation material.
A three-dimensional (3D) memory device, comprising:

a stack structure comprising interleaved a plurality of word line layers and a plurality of dielectric layers; and

a plurality of phase-change memory (PCM) strings, each of the PCM strings extending through the stack structure in a first direction and comprising:

a local bit line extending in the first direction;

a selector layer circumscribing the local bit line;

a plurality of isolation structure extending in the first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and

a plurality of PCM structures between the selector layer and the plurality of word line layers in the second direction, each of the plurality of PCM structures between two of the plurality of isolation structures in the second direction.
The 3D memory device of claim 13, further comprising one or a plurality of slit structure, each formed between two isolation structures of two respective PCM strings.
The 3D memory device of claim 14, further comprising a global bit line extending in the second direction and in contact with a respective local bit line.
The 3D memory device of claim 15, further comprising a finger defined by two adjacent slit structures, wherein the global bit line is in contact with a respective PCM string in each finger.
The 3D memory device of any one of claims 14-16, wherein each slit structure is filled with insulation material.
A system, comprising:

a three-dimensional (3D) memory device configured to store data, the 3D memory device comprising:

a stack structure comprising interleaved a plurality of word line layers and a plurality of dielectric layers; and

a plurality of phase-change memory (PCM) strings, each of the PCM strings extending through the stack structure in a first direction and comprising:

an isolation structure extending through the stack structure in the first direction; and

a plurality of PCM string parts separated by the isolation structure, each PCM string part comprising a local bit line, a selector layer circumscribing the local bit line, and a plurality of PCM structures between the selector layer and the plurality of word line layers; and

a memory controller coupled to the 3D memory device and configured to control operations of the plurality of PCM cells through the local bit line and the plurality of word lines.
A system, comprising:

a three-dimensional (3D) memory device configured to store data, the 3D memory device comprising:

a stack structure comprising interleaved a plurality of word line layers and a plurality of dielectric layers; and

a plurality of phase-change memory (PCM) strings, each of the PCM strings extending through the stack structure in a first direction and comprising:

a local bit line extending in the first direction;

a selector layer circumscribing the local bit line;

a plurality of isolation structure extending in the first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and

a plurality of PCM structures between the selector layer and the plurality of word line layers in the second direction, each of the plurality of PCM structures between two of the plurality of isolation structures in the second direction; and

a memory controller coupled to the 3D memory device and configured to control operations of the plurality of PCM cells through the local bit line and the plurality of word lines.
A method for forming a three-dimensional (3D) memory device, comprising:

forming a stack structure comprising interleaved a plurality of conductive layers and a plurality of dielectric layers on a substrate; and

forming a plurality of phase-change memory (PCM) string extending through the stack structure in a first direction, each PCM string comprises:

an isolation structure extending through the stack structure in the first direction;

a plurality of PCM string parts separated by the isolation structure, each PCM string parts comprising:

a local bit line structure extending in the first direction;

a selector layer circumscribing a respective local bit line; and

a plurality of PCM structures between the selector layer and the plurality of conductive layers, respectively.
The method of claim 20, wherein forming the stack structure comprises:

alternatingly depositing a plurality of sacrificial layers and the plurality of dielectric layers on the substrate;

etching a slit structure extending through the plurality of sacrificial layers and the plurality of dielectric layers in the first direction; and

replacing the plurality of sacrificial layers with the plurality of conductive layers, respectively, through the slit structure.
The method of claim 21, wherein forming the plurality of PCM string comprises:

forming an isolation structure on the substrate;

etching a plurality of holes extending through the plurality of sacrificial layers and the plurality of dielectric layers to expose the isolation structure;

replacing part of each of the plurality of sacrificial layers with a respective one of the plurality of PCM structures through the holes;

depositing a plurality of selector layers along respective sidewalls and bottom surfaces of the plurality of holes; and

depositing a plurality of local bit lines over the respective selector layers in the plurality of holes.
The method of claim 22, wherein replacing the part of each sacrificial layer with the respective PCM structure comprises:

etching back the plurality of sacrificial layers through each hole to form a plurality of recesses; and

forming the respective one of the plurality of PCM structure in the plurality of recesses, respectively, through each hole.
The method of claim 23, wherein forming the plurality of PCM structures comprises:

depositing a PCM layer in the plurality of recesses and along a sidewall of the holes; and

etching back the PCM layer to remove parts of the PCM layer along the sidewall of the holes.
The method of claim 23 or 24, wherein the PCM structure comprises a phase change material.
The method of any one of claims 20-25, wherein the selector layer comprises a threshold switch material.
The method of any one of claims 20-26, further comprising forming a plurality of global bit lines extending above and in contact with the respective local bit lines.
A method for forming a three-dimensional (3D) memory device, comprising:

forming a stack structure comprising interleaved a plurality of conductive layers and a plurality of dielectric layers on a substrate; and

forming a plurality of phase-change memory (PCM) strings extending through the stack structure in a first direction, each PCM string comprising:

a local bit line extending in the first direction;

a selector layer circumscribing the local bit line;

a plurality of isolation structures extending in the first direction and coupled to the selector layer in a second direction, wherein the second direction is perpendicular to the first direction; and

a plurality of PCM structures between the selector layer and the plurality of conductive layers in the second direction, the plurality of PCM structures between two of the plurality of isolation structures in the second direction.
The method of claim 28, wherein forming the stack structure comprises:

alternatingly depositing a plurality of sacrificial layers and the plurality of dielectric layers on the substrate;

etching a plurality of slit structures extending through the plurality of sacrificial layers and the plurality of dielectric layers in the first direction, each slit structure formed between two of the plurality of isolation structures of two adjacent PCM strings, respectively; and

replacing the plurality of sacrificial layers with the plurality of conductive layers, respectively, through the slit structure.
The method of claim 29, wherein forming the plurality of PCM string comprises:

forming a plurality of sacrificial isolation structures on the substrate;

etching a plurality of holes extending through the plurality of sacrificial layers, the plurality of dielectric layers, and part of each of plurality of sacrificial isolation structures to form the plurality of isolation structures;

replacing part of each of the plurality of sacrificial layers with a respective one of the plurality of PCM structures through the holes;

depositing a plurality of selector layers along respective sidewalls and bottom surfaces of the plurality of holes; and

depositing a plurality of local bit lines over the respective selector layers in the plurality of holes.
The method of claim 30, wherein replacing the part of each sacrificial layer with the respective PCM structure comprises:

etching back the plurality of sacrificial layers through each hole to form a plurality of recesses; and

forming the respective one of the plurality of PCM structure in the plurality of recesses, respectively, through each hole.
The method of claim 31, wherein forming the plurality of PCM structures comprises:

depositing a PCM layer in the plurality of recesses and along a sidewall of the holes; and

etching back the PCM layer to remove parts of the PCM layer along the sidewall of the holes.
The method of any one of claims 28-32, further comprising forming a plurality of global bit lines extending above and in contact with the respective local bit lines.
The method of claim 33, wherein the plurality of slit structures are perpendicular to the plurality of global bit lines.