CN111969106A - Phase change memory device and method of manufacturing the same - Google Patents
Phase change memory device and method of manufacturing the same Download PDFInfo
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- CN111969106A CN111969106A CN202010823409.9A CN202010823409A CN111969106A CN 111969106 A CN111969106 A CN 111969106A CN 202010823409 A CN202010823409 A CN 202010823409A CN 111969106 A CN111969106 A CN 111969106A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8413—Electrodes adapted for resistive heating
Abstract
The invention discloses a phase change memory device and a method for manufacturing the same, comprising a stacked layer formed by alternately stacking a plurality of insulating layers and a plurality of memory layers on a substrate, and a first electrode penetrating through the stacked layer, wherein each memory layer comprises a heating electrode surrounding the first electrode, and a phase change layer surrounding the heating electrode. The annular laminated structure of the first electrode, the heating electrode and the phase change layer is separated by a plurality of insulating layers, and the storage layer can realize multi-layer stacking in the first longitudinal direction, so that the storage density is improved.
Description
Technical Field
The present invention relates generally to the field of semiconductors, and more particularly, to a phase change memory device and a method of manufacturing the same.
Background
Phase Change Random Access Memory (PCRAM) has obvious advantages over current Dynamic Random Access Memory (DRAM) and FLASH memory (FLASH): its advantages are small size, low drive voltage, low power consumption, high read-write speed and non-volatilization. The phase change memory is not only a non-volatile memory, but also can be made into a multi-machine memory, is suitable for ultralow-temperature and high-temperature environments, resists irradiation and vibration, and therefore is widely applied to daily portable electronic products and has huge potential application in the field of aerospace. In particular, the high speed and non-volatility of the high-speed and non-volatile memory in portable electronic products just make up for the defects of FLASH memories (FLASH) and ferroelectric memories (FERAM). Intel corporation predicted that phase change memory will replace FLASH, DRAM, and Static Random Access Memory (SRAM). Under the condition, the development of a phase change random access memory unit device is more urgent, and the phase change random access memory unit device is in the nanometer level, is favorable for the rapid phase change of a reversible phase change film material, and is also favorable for improving the integration level of a memory.
In order to improve the storage speed and show greater superiority than the existing storage technology, the method is particularly important for preparing a phase change storage unit by using a phase change thin film material, preparing a two-dimensional or three-dimensional nanoscale, and forming a nanometer storage unit by using the phase change storage unit and an electrode. The traditional research is mostly carried out on unit devices with electrodes and phase change materials connected longitudinally, then the density of the devices is improved through longitudinal stacking of the unit devices, but the heat efficiency in the structure is low, only less than 1% of heat is actually used for phase change, the rest heat is diffused in the bottom electrode and the dielectric layer, and the heat diffused in the bottom electrode accounts for about 70%. Meanwhile, the traditional phase change memory unit can only achieve a two-layer stacking structure, and the memory capacity can only reach 128Gb at most.
Disclosure of Invention
The invention aims to provide a phase change memory device and a manufacturing method thereof, aiming at improving the storage density of the phase change memory device and reducing heat dissipation.
In one aspect, the present invention provides a phase change memory device comprising:
a substrate;
a stack layer formed by alternately stacking a plurality of insulating layers and a plurality of memory layers on the substrate;
a first electrode penetrating the stacked layers in a first longitudinal direction perpendicular to the substrate;
wherein each of the memory layers includes a heater electrode surrounding the first electrode, and a phase change layer surrounding the heater electrode.
Further preferably, the first electrode has a cylindrical shape.
Further preferably, the storage layer further comprises word lines surrounding the phase change layer and extending in a first lateral direction parallel to the substrate.
Further preferably, the device further comprises a bit line electrically connected to the top of the first electrode.
Further preferably, the memory further comprises a peripheral control circuit, wherein the peripheral control circuit comprises a transistor, a drain of the transistor is connected with the word line, and a source of the transistor is connected with the bit line.
In another aspect, the present invention provides a method of manufacturing a semiconductor device, including:
providing a substrate;
forming a stacked layer in which a plurality of insulating layers and a plurality of conductor layers are alternately stacked on the substrate;
forming an electrode via hole penetrating the stacked layers in a first longitudinal direction perpendicular to the substrate;
partially etching each conductor layer through the electrode through holes to form a plurality of phase change spaces, and depositing a plurality of phase change layers in the plurality of phase change spaces, wherein one phase change layer is surrounded by one conductor layer;
partially etching each phase change layer to form a plurality of electrode spaces, depositing a plurality of heating electrodes in the electrode spaces, wherein one heating electrode is surrounded by one phase change layer and is connected with the electrode through hole;
forming a first electrode in the electrode through-hole, the first electrode being surrounded by the plurality of heating electrodes.
Further preferably, the first electrode has a cylindrical shape.
Further preferably, the conductor layer after partial etching is performed on each conductor layer, and word lines surrounding the phase change layer are formed in a first transverse direction parallel to the substrate.
Further preferably, the method further comprises the following steps: forming a bit line electrically connected to a top of the first electrode.
Further preferably, the method further comprises forming a peripheral control circuit, wherein the peripheral control circuit comprises a transistor, a drain of the transistor is connected with the word line, and a source of the transistor is connected with the bit line.
The invention has the beneficial effects that: a phase change memory device and a method of manufacturing the same are provided, including a stack layer on a substrate, the stack layer being formed by alternately stacking a plurality of insulation layers and a plurality of memory layers, and a first electrode penetrating the stack layer in a first longitudinal direction perpendicular to the substrate, wherein each of the memory layers includes a heater electrode surrounding the first electrode, and a phase change layer surrounding the heater electrode. The transverse laminated structures of the first electrode, the heating electrode and the phase change layer are isolated by the insulating layer, so that the size of a storage unit can be reduced, heat dissipation can be reduced, the storage unit can be longitudinally stacked, and the storage density can be improved.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic longitudinal cross-sectional view of a phase-change memory device provided by an embodiment of the present invention;
FIG. 2a is a schematic cross-sectional view of a phase-change memory device along the AA' plane according to an embodiment of the present invention;
FIG. 2b is a schematic cross-sectional view of a phase-change memory device along the BB' plane according to an embodiment of the present invention;
FIG. 3 is a schematic flow chart diagram illustrating a method of fabricating a phase-change memory device according to an embodiment of the present invention;
fig. 4a is a schematic longitudinal cross-sectional view of the phase-change memory device after completion of step S3;
fig. 4b is a schematic longitudinal cross-sectional view of the phase-change memory device after completion of step S4;
fig. 4c is a schematic longitudinal cross-sectional view of the phase-change memory device after completion of step S5;
fig. 4d is a schematic longitudinal cross-sectional view of the phase-change memory device after completion of step S6.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.
It will be understood that when an element is referred to as being "on," "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.
As used herein, the term "layer" refers to a portion of material having an area of thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any horizontal pair of surfaces at the top and bottom surfaces or between the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers above and/or below it. The layers may include multiple layers, for example, the interconnect layer may include one or more conductor and contact layers and one or more dielectric layers.
As used herein, the term "memory device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate such that the array structure extends in a vertical direction relative to the substrate. As used herein, the term "vertical" nominally refers to perpendicular to a lateral surface of a substrate.
It should be noted that the drawings provided in the embodiments of the present invention are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in the actual implementation, the type, quantity and proportion of the components in the actual implementation can be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, fig. 1 is a schematic longitudinal cross-sectional view of a phase-change memory device according to an embodiment of the invention. The phase-change memory device 10 includes a substrate 11, a stack layer 14 formed by alternately stacking a plurality of insulating layers 12 and a plurality of memory layers 13 on the substrate 11, and a first electrode 15 penetrating the stack layer 14 in a first longitudinal direction perpendicular to the substrate 11. Wherein each memory layer 13 includes a heater electrode 131 surrounding the first electrode 15, and a phase change layer 132 surrounding the heater electrode 131.
The substrate 11 may be a semiconductor material, the insulating layer 12 may be an insulating material such as silicon oxide, the first electrode 15 may be tungsten or other metal material, and the heating electrode 131 may be a good conductive material such as W, TiN, which mainly functions to conduct and heat the phase-change material. The material of the phase change layer 132 includes, for example, a chalcogenide-based material including any one of four elements of oxygen (O), sulfur (S), selenium (Se), and tellurium (Te) forming part of group VIA of the periodic table. The material of the phase change layer 132 is, for example, a chalcogenide compound with a more electropositive element or radical, a combination of chalcogenide with other materials such as transition metals, and a chalcogenide alloy. Chalcogenide alloys typically contain one or more elements from group IVA of the periodic table, such as germanium (Ge) and tin (Sn). Typically, chalcogenide alloys include combinations of one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in the technical literature, including alloys of: Ga/Sb, In/Se, Sb/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S.
In this embodiment, the storage layer 13 may further include word lines 133 surrounding the phase change layer 132, the word lines 133 extending in a first lateral direction parallel to the substrate 11, and having a generally rectangular cross-section.
In the present embodiment, the memory device 10 further includes a bit line 16 electrically connected to the top of the first electrode 15, which may be electrically connected through a metal plug 161.
In the present embodiment, the phase-change memory device 10 further includes a peripheral control circuit (not shown in the figure) including a transistor having a drain connected to the word line 133 and a source connected to the bit line 16. Specifically, a high level (for example, 3.3V) is applied to the drain, a control signal is applied to the gate of the transistor to turn on the drain and the source, and a current flows from the drain to the first electrode 15 through the bit line 16, the heater electrode 131 and the phase change layer 132 (in the solid line direction with arrows shown in fig. 1), flows to the word line 133, and finally reaches the source. The heating electrode 131 heats the phase change layer 132, and since the material of the phase change layer 132 has a reversible phase change property, storage can be achieved by using a high resistance property in an amorphous state and a low resistance property in a crystalline state.
The word lines 133 and the bit lines 16 may be perpendicular to each other, parallel to each other, or cross at a certain angle.
Referring to fig. 2a, fig. 2a is a schematic cross-sectional view of a phase-change memory device along plane AA' according to an embodiment of the present invention, in which the first electrode 15 of the phase-change memory device 10 is preferably cylindrical, the heater electrode 131 is a ring structure surrounding a sidewall of the first electrode 15, the phase-change layer 132 is a ring structure surrounding a sidewall of the heater electrode 131, and a lateral cross-section of the word line 133 is rectangular. Wherein the cross on the first electrode 15 indicates that the direction of the heating current is inwards towards the page.
In other embodiments, the first electrode 15 may have other pillar-shaped structures, and the transverse cross-section thereof has other shapes, such as square and rectangle.
Referring to fig. 2b, fig. 2b is a schematic cross-sectional view of a phase-change memory device along the BB' plane according to an embodiment of the invention. The insulating layer 12 surrounds the first electrode 15, the first electrode 15 may serve as a common electrode for a plurality of memory cells, and the insulating layer 12 may isolate the plurality of memory layers 13.
The phase-change memory device 10 provided by the embodiment of the invention is formed by stacking the plurality of memory layers 13 in the first longitudinal direction, and the plurality of memory layers 13 are isolated by the insulating layer 12 and do not affect each other, so that the phase-change memory with high memory density can be realized. Wherein each memory layer 13 includes a heater electrode 131 surrounding the first electrode 15, and a phase change layer 132 surrounding the heater electrode 131, the phase change cell of the annular stack structure can reduce heat dissipation, thereby reducing power consumption.
Embodiments of the present invention also provide a method of fabricating the phase-change memory device 10 described above, and thus the structural reference numerals of the phase-change memory device 10 are referenced in steps of the fabrication method. Fig. 3 is a flowchart illustrating a method of manufacturing a phase-change memory device according to an embodiment of the present invention, which includes the following steps S1-S6.
Step S1: a substrate 11 is provided.
Step S2: a stacked layer 14 'in which a plurality of insulating layers 12 and a plurality of conductor layers 13' are alternately stacked is formed on a substrate 11.
The insulating layer 12 may be silicon oxide or the like, and the conductive layer 13' may be a metal such as tungsten or the like. The Deposition method of the insulating Layer 12 and the conductive Layer 13' may adopt, but is not limited to, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), such as thermal oxidation, evaporation, sputtering, and other methods. The number of pairs of insulating layers 12/conductive layers 13 'in the stacked layer 14' may be 32, 64, 96, 128 or more, and the specific number may be set according to the actual requirement, and is not limited herein.
Step S3: an electrode via 141 penetrating the stacked layers 14' is formed in a first longitudinal direction perpendicular to the substrate 11.
For example, the electrode via hole 141 may be formed using a photolithography process and an etching process. The structure of the phase-change memory device after completion of step S3 is shown in fig. 4 a.
Step S4: each of the conductor layers 13 'is partially etched through the electrode via holes 141 to make a plurality of phase change spaces, and a plurality of phase change layers 132 are deposited in the plurality of phase change spaces, one phase change layer 132 being surrounded by one conductor layer 13'.
The phase change space may be formed using an etching process and then the phase change layer 132 may be formed using a deposition process. The structure of the phase-change memory device after the completion of step S4 is shown in fig. 4 b. In the present embodiment, the portion of the conductor layer 13' left after etching forms the word line 133. Wherein the word lines 133 extend in a first lateral direction parallel to the substrate 11 and surround the phase change layer 132.
Step S5: partially etching each phase change layer 132 to make a plurality of electrode spaces, and depositing a plurality of heater electrodes 131 in the electrode spaces, wherein one heater electrode 131 is surrounded by one phase change layer 132 and is connected with the electrode through hole 141.
The electrode space may be formed using an etching process and then the heating electrode 131 may be formed using a deposition process. The structure of the phase-change memory device after the completion of step S5 is shown in fig. 4 c.
Step S6: a first electrode 15 is formed in the electrode through hole 141, the first electrode 15 being surrounded by the plurality of heating electrodes 131.
The first electrode 15 may be formed by the deposition method described above, and the material of the first electrode 15 may be tungsten or other metal material. The structure of the phase-change memory device after the completion of step S6 is shown in fig. 4 d.
Continuing to refer to fig. 1, after step S6, a bit line 16 electrically connected to the top of the first electrode 15 is formed. Specifically, a dielectric layer 17 may be formed on the stacked layer 14, a metal plug 161 connected to the top of the first electrode 15 may be formed in the dielectric layer 17, and a bit line 16 may be formed on the dielectric layer 17, wherein the first electrode 15 and the bit line 16 are electrically connected through the metal plug 161. As shown in fig. 1, the formed phase-change memory device includes heater electrode 131, phase-change layer 132, and word line 133 that constitute memory layer 13 shown in fig. 1.
In this embodiment, the manufacturing method further includes forming a peripheral control circuit (not shown in the figure) including a transistor having a drain connected to the word line 133 and a source connected to the bit line 16.
In other embodiments, step S4 and step S5 may be replaced with the following steps: a plurality of storage spaces are made by partially etching the respective conductor layers 13 'through the electrode via holes 141, and the phase change layer 132 surrounded by the conductor layers 13' and the heater electrode 131 surrounded by the phase change layer 132 are sequentially deposited in each storage space. Wherein the heating electrode 131 is connected with the electrode through hole 141. The time and rate control requirements for the deposition process are higher at this point.
According to the manufacturing method of the phase change memory device, the stacked layer 14 ' formed by alternately stacking the insulating layer 12 and the conductor layer 13 ' is formed, then the conductor layer 13 ' is etched and deposited through the electrode through hole 141 to form the word line 133, the phase change layer 132 surrounded by the word line 133 and the heating electrode 131 surrounded by the phase change layer 132, and finally the first electrode 15 is formed in the electrode through hole 141, so that the heating electrode 131 surrounds the first electrode 15, the formed annular stacked structure can reduce heat dissipation, and the storage layers 13 are isolated by the insulating layer 12 and do not affect each other. The manufacturing method is simple, the cost is reduced, and the phase change memory device with high storage density can be manufactured.
The above description of the embodiments is only for helping understanding the technical solution of the present invention and its core idea; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A phase change memory device, comprising:
a substrate;
a stack layer formed by alternately stacking a plurality of insulating layers and a plurality of memory layers on the substrate;
a first electrode penetrating the stacked layers in a first longitudinal direction perpendicular to the substrate;
wherein each of the memory layers includes a heater electrode surrounding the first electrode, and a phase change layer surrounding the heater electrode.
2. The phase-change memory device as claimed in claim 1, wherein the first electrode has a cylindrical shape.
3. The phase-change memory device as claimed in claim 1, wherein the memory layer further comprises word lines surrounding the phase-change layer and extending in a first lateral direction parallel to the substrate.
4. The phase-change memory device as claimed in claim 3, further comprising a bit line electrically connected to a top portion of the first electrode.
5. The phase-change memory device as claimed in claim 4, further comprising a peripheral control circuit including a transistor having a drain connected to the word line and a source connected to the bit line.
6. A method of manufacturing a phase change memory device, comprising:
providing a substrate;
forming a stacked layer in which a plurality of insulating layers and a plurality of conductor layers are alternately stacked on the substrate;
forming an electrode via hole penetrating the stacked layers in a first longitudinal direction perpendicular to the substrate;
partially etching each conductor layer through the electrode through holes to form a plurality of phase change spaces, and depositing a plurality of phase change layers in the plurality of phase change spaces, wherein one phase change layer is surrounded by one conductor layer;
partially etching each phase change layer to form a plurality of electrode spaces, depositing a plurality of heating electrodes in the electrode spaces, wherein one heating electrode is surrounded by one phase change layer and is connected with the electrode through hole;
forming a first electrode in the electrode through-hole, the first electrode being surrounded by the plurality of heating electrodes.
7. The method of manufacturing a phase-change memory device according to claim 6, wherein the first electrode has a cylindrical shape.
8. The method of manufacturing a phase-change memory device as claimed in claim 6, wherein the conductor layers partially etched for each of the conductor layers are formed with word lines surrounding the phase-change layer in a first lateral direction parallel to the substrate.
9. The method of manufacturing a phase-change memory device according to claim 8, further comprising: forming a bit line electrically connected to a top of the first electrode.
10. The method of manufacturing a phase-change memory device according to claim 9, further comprising forming a peripheral control circuit including a transistor having a drain connected to the word line and a source connected to the bit line.
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| CN113439336B (en) * | 2021-05-18 | 2022-12-06 | 长江先进存储产业创新中心有限责任公司 | Three-dimensional phase change memory device and forming method thereof |
| CN113644087A (en) * | 2021-08-10 | 2021-11-12 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
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