CN113437157B - Table-board radio frequency PIN diode and preparation method thereof - Google Patents
Table-board radio frequency PIN diode and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a mesa radio frequency PIN diode and a preparation method thereof in the technical field of semiconductor power devices. This kind of mesa radio frequency PIN diode includes: the N-type heavily doped substrate comprises a bottom layer and a top layer, a high-resistance intrinsic layer and a P-type heavily doped layer are sequentially arranged above the top layer, and a PtSi doped part is arranged on the upper surface of the P-type heavily doped layer; the top layer, the P-type heavily doped layer and the high-resistance intrinsic layer jointly form a three-layer cylindrical body; the passivation layer is arranged above the bottom layer, wraps the cylindrical body and is provided with a through hole above the cylindrical body; and a front multilayer metal is arranged above the P-type heavily doped layer and passes through the through hole to be in contact with the P-type heavily doped layer. The table-board radio frequency PIN diode is provided with the PtSi doped part on the upper surface of the P-type heavily doped layer, so that surface charges are inhibited, and the reliability of a product is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a mesa radio frequency PIN diode and a preparation method thereof.
Background
The prior frequency transmitting tubes have wide and irreplaceable functions in the communication field because the prior frequency transmitting tubes have the characteristics of extremely low forward conduction voltage drop and electric leakage and near ideal reverse recovery and are commonly used in signal transmitting equipment. With the rapid development of communication equipment, especially mobile communication equipment, higher requirements are put on the operational reliability of the radio frequency tube.
The traditional planar technology radio frequency PIN diode has the defects that due to the fact that the area of a chip is large, impurities are easily contaminated on the surface of the chip, so that the breakdown curve is often unstable or the leakage is invalid, and the reliability of the radio frequency PIN diode is influenced; in addition, the traditional plane process radio frequency PIN diode generally only uses thicker thermal oxidation SiO 2 As a passivation layer to protect the region outside the contact hole, but SiO 2 The passivation layer has weak impurity shielding capability, is easily damaged by acid corrosive liquid, and can influence the reliability of the radio frequency PIN diode.
Disclosure of Invention
The application provides the table-board radio frequency PIN diode and the preparation method thereof, and solves the problem that the conventional plane technology in the prior art is low in reliability of the radio frequency PIN diode.
The embodiment of the application provides a mesa radio frequency PIN diode, includes:
the N-type heavily doped substrate comprises a bottom layer and a top layer, wherein a plurality of layers of back metal are arranged below the bottom layer, the cross section area of the top layer is smaller than that of the bottom layer, and the top layer is arranged above the bottom layer and is integrally formed with the bottom layer;
a high resistive intrinsic layer disposed over the top layer;
the P-type heavily doped layer is arranged above the high-resistance intrinsic layer, and a PtSi doped part is arranged on the upper surface of the P-type heavily doped layer;
the top layer, the P-type heavily doped layer and the high-resistance intrinsic layer jointly form a three-layer column body;
the passivation layer is arranged above the bottom layer and wraps the columnar body, and a through hole is formed in the passivation layer above the columnar body;
and a front multilayer metal is arranged above the P-type heavily doped layer and passes through the through hole to be in contact with the P-type heavily doped layer.
The beneficial effects of the embodiment are as follows: a PtSi doping part is arranged on the upper surface of the P-type heavily doped layer, and a layer of PtSi doping part is sputtered on the surface of the bare silicon through magnetron sputtering
Forming a compact Pt-Si compound through 55-700 ℃ high-temperature alloy, closely connecting the Pt-Si compound with a passivation layer, and completely covering the upper surface of the P-type heavily doped layer so as to achieve the effect of inhibiting surface charges and prevent surface electric leakage, further enhancing chip surface protection by increasing the structural design of the PtSi doped part, greatly reducing the risk of unstable breakdown curve or electric leakage failure and improving the reliability of the product; in addition, because Pt is not easy to migrate below 200 ℃, the surface can be effectively inhibited when the temperature of the working environment of the product is higherA charge; meanwhile, the adhesion of common front metal materials such as PtSi, Ti/Pt/Au and the like is good, so that the reliability of subsequent front metal is not influenced.
On the basis of the above embodiments, the present application can be further improved, specifically as follows:
in one embodiment of the present application, the passivation layer includes a first silicon dioxide layer, a second silicon dioxide layer and a silicon nitride layer from inside to outside, the first silicon dioxide layer is prepared by a thermal oxidation method, and the second silicon dioxide layer is prepared by a chemical deposition method.
The beneficial effects of the above embodiment are as follows: the passivation layer is prepared by compounding a silicon dioxide layer I (thermal oxidation), a silicon dioxide layer II (chemical deposition) and a silicon nitride layer, wherein the silicon dioxide prepared by thermal oxidation has the advantages of compact film structure, less defects in the film and strong impurity masking capability, the silicon dioxide prepared by chemical deposition has less stress with silicon, is loose and more defects compared with the silicon dioxide prepared by thermal oxidation, but has smaller stress with silicon and other silicides, and the silicon nitride has the strongest capability of resisting impurity contamination and ion contamination relative to the two silicon dioxide, but has large stress with silicon and other silicides and is easy to crack; based on the characteristics of three kinds of passive films, silicon dioxide layer one (thermal oxidation) plays main passivation effect, silicon dioxide layer two (chemical deposition) has more loose structure than silicon dioxide layer one (thermal oxidation), relative stress is less, it can reduce the stress between silicon nitride and silicon dioxide layer one to increase the silicon dioxide layer two that chemical deposition made between silicon dioxide layer one and silicon nitride layer, adjust silicon dioxide layer two with the matching stress, silicon nitride is the passivation of outermost layer, can effectively isolated steam and mobile ion, good passivation effect and stress matching are realized in the cooperation of three-layer, promote product reliability.
In one embodiment of the present disclosure, the thickness of the first silicon dioxide layer is greater than that of the second silicon dioxide layer, and the thickness of the second silicon dioxide layer is greater than that of the silicon nitride layer. The first silicon dioxide layer prepared by thermal oxidation is thickest so as to ensure the thickness of the passivation layer and improve the passivation effect; the silicon nitride layer is positioned on the outermost layer to improve the capability of resisting impurity contamination and ion contamination, and the thickness of the silicon nitride layer is the thinnest so as to reduce the possibility of cracking; and adjusting the thickness of the second silicon dioxide layer according to the thickness of the silicon nitride to ensure the appearance of the silicon nitride layer.
In one embodiment of the present application, the silicon dioxide layer has a thickness of
The silicon nitride layer has a thickness of
In one embodiment of the application, the included angle between the side wall of the cylindrical body and the horizontal plane is 85-90 degrees, and the height of the cylindrical body is more than 10 mu m. And the voltage requirement of the radio frequency PIN diode is met.
The embodiment of the application also provides a preparation method of the table-board radio frequency PIN diode, which comprises the following steps:
s1, selecting an N-type heavily doped silicon wafer as a substrate of a device, and epitaxially growing a high-resistance intrinsic layer on the top layer of the N-type heavily doped substrate;
s2, pushing out the P-type heavily doped layer on the high-resistance intrinsic layer through liquid source coating diffusion annealing;
s3, preparing the cylindrical body through photoetching and etching;
s4, preparing the passivation layer on the outer periphery of the cylinder, wherein the passivation layer wraps the side wall and the upper surface of the cylinder;
s5, photoetching to prepare a pattern, and etching to form the through hole contacted with the front electrode;
s6, sputtering Pt and alloying to form the PtSi doped part;
s7, forming a front metal pattern by using negative glue;
s8, evaporating to prepare the front multilayer metal;
s9, removing redundant metal and photoresist by using a stripping process;
s10, thinning and evaporating to prepare the back multilayer metal.
The beneficial effects of the embodiment are as follows: compared with the conventional radio frequency PIN diode, the preparation method of the table-board radio frequency PIN diode has the advantages that the design of a voltage division ring is omitted by adopting the table-board structure, the area of a chip is greatly reduced, meanwhile, the preparation steps of a plurality of voltage division rings in the conventional process are reduced, the production cost of the product is reduced, meanwhile, the preparation method can be suitable for a larger voltage area, and a high-voltage series radio frequency PIN diode (200V-1200V) can be developed.
In one embodiment of the present application, the step S3 is specifically as follows:
s3.1, growing silicon nitride on the P-type heavily doped layer to serve as a masking layer for etching;
s3.2, photoetching to form a pattern, removing photoresist after etching a cylindrical body by a dry method;
s3.3, removing the side wall etching damage layer and the natural oxidation layer by wet etching;
and S3.4, removing the residual silicon nitride layer by a wet method.
The growth of silicon nitride as a masking layer for etching can effectively ensure the appearance of the etched deep groove, and can avoid the appearance abnormality of the upper surface of the deep groove caused by steps at the edge of the photoresist in the etching process relative to the use of the photoresist as the masking layer.
In one embodiment of the present application, the step S4 is specifically as follows:
s4.1, preparing a first silicon dioxide layer on the periphery of the cylindrical body through thermal oxidation;
s4.2, preparing a second silicon dioxide layer on the periphery of the first silicon dioxide layer through chemical deposition;
and S4.3, synthesizing a silicon nitride layer at the periphery of the second silicon dioxide layer through chemical reaction.
In one embodiment of the present application, the step S6 is specifically as follows: sputtering a layer on the upper surface of the P-type heavily doped layer by magnetron sputtering
And forming a compact Pt-Si compound through high-temperature alloy at the temperature of 55-700 ℃, namely the PtSi doping part is tightly connected with the passivation layer until the upper surface of the P-type heavily doped layer is completely covered. Sputtered and alloyed filmThe step coverage is good, and the reliability is enhanced.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
1. a PtSi doping part is arranged on the upper surface of the P-type heavily doped layer, so that surface charges are inhibited, and the reliability of a product is improved;
2. the passivation layer is prepared by compounding a silicon dioxide layer I (thermal oxidation), a silicon dioxide layer II (chemical deposition) and a silicon nitride layer, and the three layers are matched to realize good passivation effect and stress matching, so that the reliability of the product is improved.
Drawings
In order to more clearly illustrate the detailed description of the invention or the technical solutions in the prior art, the drawings that are needed in the detailed description of the invention or the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.
FIG. 1 is a schematic structural diagram of a mesa RF PIN diode according to the present invention;
FIG. 2 is a flow chart of a method for manufacturing a mesa RF PIN diode according to the present invention;
the high-resistance intrinsic thin film transistor comprises a substrate 1, an N-type heavily doped substrate, a high-resistance intrinsic layer 2, a P-type heavily doped layer 3, a PtSi doped part 31, a passivation layer 4, a silicon dioxide layer I41, a silicon dioxide layer II 42, a silicon nitride layer 43, a front multilayer metal 5 and a back multilayer metal 6.
Detailed Description
The present invention is further illustrated by the following detailed description, which is to be construed as merely illustrative and not limitative of the remainder of the disclosure, and modifications and variations such as those ordinarily skilled in the art are intended to be included within the scope of the present invention as defined in the appended claims.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "vertical", "peripheral surface" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the present invention are conventionally placed when used, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or the element to which the present invention is directed must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless otherwise explicitly stated or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In describing the invention, it is not necessary for a schematic representation of the above terminology to be directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of different embodiments or examples described herein can be combined and combined by one skilled in the art without being mutually inconsistent.
The first embodiment is as follows:
as shown in fig. 1, a mesa rf PIN diode includes: the semiconductor device comprises an N-type heavily doped substrate 1, a high-resistance intrinsic layer 2, a P-type heavily doped layer 3, a passivation layer 4, a front multilayer metal 5 and a back multilayer metal 6; the N-type heavily doped substrate 1 comprises a bottom layer and a top layer, wherein a plurality of layers of metal 6 on the back surface are arranged below the bottom layer, the cross section area of the top layer is smaller than that of the bottom layer, and the top layer is arranged above the bottom layer and is formed with a first 41 bottom layer body; the high-resistance intrinsic layer 2 is arranged above the top layer, the P-type heavily doped layer 3 is arranged above the high-resistance intrinsic layer 2, the PtSi doped part 31 is arranged on the upper surface of the P-type heavily doped layer 3, and the top layer of the N-type heavily doped substrate 1, the P-type heavily doped layer 3 and the high-resistance intrinsic layer 2 jointly form a three-layer column body; the passivation layer 4 is arranged above the bottom layer, the passivation layer 4 coats the cylindrical body, a through hole is formed in the passivation layer 4 above the cylindrical body, the passivation layer 4 comprises a first silicon dioxide layer 41, a second silicon dioxide layer 42 and a silicon nitride layer 43 from inside to outside, the first silicon dioxide layer 41 is prepared through a thermal oxidation mode, the second silicon dioxide layer 42 is prepared through a chemical deposition mode, the thickness of the first silicon dioxide layer 41 is larger than that of the second silicon dioxide layer 42, and the thickness of the second silicon dioxide layer 42 is larger than that of the silicon nitride layer 43; the front multilayer metal 5 is arranged above the cylindrical body, and the front multilayer metal 5 penetrates through the through hole to be in contact with the P-type heavily doped layer 3.
Optionally, the silicon dioxide layer has a thickness of
The silicon nitride layer has a thickness of
Optionally, an included angle between the side wall of the cylinder and the horizontal plane is 85-90 degrees, and the height of the cylinder is greater than 10 μm.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
1. the PtSi doping part is arranged on the upper surface of the P-type heavily doped layer, so that surface charges are inhibited, and the reliability of a product is improved;
2. the passivation layer is prepared by compounding a silicon dioxide layer I (thermal oxidation), a silicon dioxide layer II (chemical deposition) and a silicon nitride layer, and the three layers are matched to realize good passivation effect and stress matching, so that the product reliability is improved.
Example two:
as shown in fig. 2, a method for preparing a mesa rf PIN diode includes the following steps:
s1, selecting an N-type heavily doped silicon wafer as a substrate of the device, and epitaxially growing a high-resistance intrinsic layer on the top layer of the N-type heavily doped substrate, wherein the thickness and the resistivity of the high-resistance intrinsic layer need to be set according to the electrical property requirement of a product;
s2, pushing out the P-type heavily doped layer on the high-resistance intrinsic layer through liquid source coating diffusion annealing, wherein the step can be repeated for multiple times according to the product requirements;
s3, preparing the columnar body through photoetching and etching, specifically:
s3.1, growing silicon nitride on the P-type heavily doped layer to serve as a masking layer for etching;
s3.2, photoetching to form a pattern, removing photoresist after etching a cylindrical body by a dry method;
s3.3, removing the side wall etching damage layer and the natural oxidation layer by wet etching;
s3.4, removing the residual silicon nitride layer by a wet method;
s4, preparing a passivation layer on the outer periphery of the cylinder, wherein the passivation layer wraps the side wall and the upper surface of the cylinder, and the method specifically comprises the following steps:
s4.1, preparing a first silicon dioxide layer on the outer periphery of the cylinder body through thermal oxidation;
s4.2, preparing a second silicon dioxide layer on the periphery of the first silicon dioxide layer through chemical deposition;
s4.3, synthesizing a silicon nitride layer on the periphery of the second silicon dioxide layer through a chemical reaction;
s5, photoetching a passivation layer to prepare a pattern, and etching to form a through hole contacted with the front electrode (the residual passivation layer is required to wrap the side wall of the table top and the edge of the upper surface of the cylindrical body);
s6, sputtering Pt and alloying to form a PtSi doped part, specifically: sputtering a layer on the surface of bare silicon by magnetron sputtering
Forming a compact Pt-Si compound through 55-700 ℃ high-temperature alloy, closely connecting with the passivation layer, and completely covering the upper surface of the P-type heavily doped layer;
s7, forming a front metal pattern by using negative glue;
s8, evaporating to prepare a front multilayer metal (Ti/Pt/Au system);
s9, removing redundant metal and photoresist by using a stripping process;
and S10, thinning and evaporating to prepare the back multilayer metal.
Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are exemplary and not to be construed as limiting the present invention, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (6)
1. A mesa rf PIN diode, comprising:
the N-type heavily doped substrate comprises a bottom layer and a top layer, wherein a plurality of layers of back metal are arranged below the bottom layer, the cross section area of the top layer is smaller than that of the bottom layer, and the top layer is arranged above the bottom layer and is integrally formed with the bottom layer;
a high resistive intrinsic layer disposed over the top layer;
the P-type heavily doped layer is arranged above the high-resistance intrinsic layer, and a PtSi doped part is arranged on the upper surface of the P-type heavily doped layer;
the top layer, the P-type heavily doped layer and the high-resistance intrinsic layer jointly form a three-layer column body;
the passivation layer is arranged above the bottom layer and wraps the cylindrical body, a through hole is formed in the passivation layer above the cylindrical body, the PtSi doping portion is tightly connected with the passivation layer and completely covers the upper surface of the P-type heavily doped layer, the passivation layer comprises a first silicon dioxide layer, a second silicon dioxide layer and a silicon nitride layer from inside to outside, the first silicon dioxide layer is prepared in a thermal oxidation mode, the second silicon dioxide layer is prepared in a chemical deposition mode, the thickness of the first silicon dioxide layer is larger than that of the second silicon dioxide layer, and the thickness of the second silicon dioxide layer is larger than that of the silicon nitride layer;
and a front multilayer metal is arranged above the P-type heavily doped layer and passes through the through hole to be in contact with the P-type heavily doped layer.
2. The mesa radio frequency PIN diode of claim 1, wherein: the silicon dioxide layer has a thickness of
The silicon nitride layer has a thickness of
3. The mesa radio frequency PIN diode of claim 1, wherein: the included angle between the side wall of the cylindrical body and the horizontal plane is 85-90 degrees, and the height of the cylindrical body is larger than 10 mu m.
4. A method of making the mesa rf PIN diode of claim 1, comprising the steps of:
s1, selecting an N-type heavily doped silicon wafer as a substrate of a device, and epitaxially growing a high-resistance intrinsic layer on the top layer of the N-type heavily doped substrate;
s2, pushing out the P-type heavily doped layer on the high-resistance intrinsic layer through liquid source coating diffusion annealing;
s3, preparing the cylindrical body through photoetching and etching;
s4, preparing the passivation layer on the outer periphery of the cylinder, wherein the passivation layer wraps the side wall and the upper surface of the cylinder, and the method comprises the following specific steps:
s4.1, preparing a first silicon dioxide layer on the periphery of the cylindrical body through thermal oxidation;
s4.2, preparing a second silicon dioxide layer on the periphery of the first silicon dioxide layer through chemical deposition;
s4.3, synthesizing a silicon nitride layer on the periphery of the second silicon dioxide layer through a chemical reaction;
s5, photoetching to prepare a pattern, and etching to form the through hole contacted with the front electrode;
s6, sputtering Pt and forming the PtSi doped part by alloy;
s7, forming a front metal pattern by using negative glue;
s8, evaporating to prepare the front multilayer metal;
s9, removing redundant metal and photoresist by using a stripping process;
s10, thinning and evaporating to prepare the back multilayer metal.
5. The method of manufacturing according to claim 4, characterized in that: the step S3 is specifically as follows:
s3.1, growing silicon nitride on the P-type heavily doped layer to serve as a masking layer for etching;
s3.2, photoetching to form a pattern, removing photoresist after etching a cylindrical body by a dry method;
s3.3, removing the side wall etching damage layer and the natural oxidation layer by wet etching;
and S3.4, removing the residual silicon nitride layer by a wet method.
6. The method of manufacturing according to claim 4, characterized in that: the step S6 is specifically as follows:
and sputtering a layer of Pt on the upper surface of the P-type heavily doped layer through magnetron sputtering, and then forming the PtSi doped part through 55-700 ℃ high-temperature alloy.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6213033A (en) * | 1985-07-10 | 1987-01-21 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| US6633071B1 (en) * | 1997-05-30 | 2003-10-14 | Sgs-Thomson Microelectronics S.A. | Contact on a P-type region |
| CN210575966U (en) * | 2019-11-11 | 2020-05-19 | 扬州国宇电子有限公司 | High-voltage radio frequency PIN tube |
| CN112117336A (en) * | 2020-09-22 | 2020-12-22 | 厦门大学 | 4H-SiC ultraviolet photoelectric detector array with back-illuminated structure and preparation |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2577330B2 (en) * | 1986-12-11 | 1997-01-29 | 新技術事業団 | Method of manufacturing double-sided gate static induction thyristor |
| CN206619599U (en) * | 2016-12-21 | 2017-11-07 | 北京飞行博达电子有限公司 | A kind of passivation on double surfaces solar cell |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6213033A (en) * | 1985-07-10 | 1987-01-21 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| US6633071B1 (en) * | 1997-05-30 | 2003-10-14 | Sgs-Thomson Microelectronics S.A. | Contact on a P-type region |
| CN210575966U (en) * | 2019-11-11 | 2020-05-19 | 扬州国宇电子有限公司 | High-voltage radio frequency PIN tube |
| CN112117336A (en) * | 2020-09-22 | 2020-12-22 | 厦门大学 | 4H-SiC ultraviolet photoelectric detector array with back-illuminated structure and preparation |
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