CN111540683A - Manufacturing method of power device - Google Patents
Manufacturing method of power device Download PDFInfo
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- CN111540683A CN111540683A CN202010475738.9A CN202010475738A CN111540683A CN 111540683 A CN111540683 A CN 111540683A CN 202010475738 A CN202010475738 A CN 202010475738A CN 111540683 A CN111540683 A CN 111540683A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 123
- 229910052751 metal Inorganic materials 0.000 claims abstract description 114
- 239000002184 metal Substances 0.000 claims abstract description 114
- 238000000034 method Methods 0.000 claims abstract description 70
- 238000007747 plating Methods 0.000 claims abstract description 34
- 239000000126 substance Substances 0.000 claims abstract description 27
- 239000011248 coating agent Substances 0.000 claims abstract description 4
- 238000000576 coating method Methods 0.000 claims abstract description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 34
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 22
- 239000010931 gold Substances 0.000 claims description 20
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 16
- 229910052737 gold Inorganic materials 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 15
- 229910052759 nickel Inorganic materials 0.000 claims description 15
- 229910052763 palladium Inorganic materials 0.000 claims description 10
- 238000007772 electroless plating Methods 0.000 claims description 9
- 239000002253 acid Substances 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 2
- 150000007513 acids Chemical class 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 7
- 239000012634 fragment Substances 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 75
- 230000001681 protective effect Effects 0.000 description 20
- 239000002585 base Substances 0.000 description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 10
- 238000005530 etching Methods 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 239000003513 alkali Substances 0.000 description 3
- 239000013043 chemical agent Substances 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 239000007888 film coating Substances 0.000 description 2
- 238000009501 film coating Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Abstract
The application discloses a manufacturing method of a power device, which relates to the field of semiconductor manufacturing and comprises the steps of forming a unit structure of the power device on a substrate, wherein the power device is an IGBT; forming a front metal layer; carrying out TAIKO thinning on the back surface of the substrate; forming a collector region on the back surface of the substrate; coating a film on the back surface of the substrate; forming a target metal on the front surface of the substrate by utilizing a chemical plating process; removing the film attached to the back surface of the substrate; forming a metal layer on the back of the substrate; the problem that wafer fragments are easily caused by increasing the thickness and the hardness of the metal on the front surface by using a chemical plating process is solved; the effects of improving the metal falling condition after chemical plating and optimizing the combination effect of the IGBT manufacturing process and the chemical plating process are achieved.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a power device.
Background
An Insulated Gate Bipolar Transistor (IGBT) device is a core device in new energy power electronic products, and with more extensive popularization in recent years, application products include not only traditional products such as white home appliances, industrial frequency conversion, welding machines and the like, but also high-end products such as new energy automobiles and the like.
At present, the IGBT is developing towards high voltage and high current, and the chip process and package of the IGBT face brand new challenges. For high-current IGBT chips and modules, achieving heat dissipation of the entire module has become a major research point. When the IGBT chip is packaged, the welding process used by wire bonding is developed from traditional aluminum wire welding to copper sheet welding, and the requirements on the thickness and hardness of the metal on the front surface of the IGBT are higher.
However, when the thickness and hardness of the metal on the front surface of the IGBT are increased by the chemical plating process, wafer fragments are easily generated.
Disclosure of Invention
In order to solve the problems in the related art, the present application provides a method for manufacturing a power device. The technical scheme is as follows:
in one aspect, an embodiment of the present application provides a method for manufacturing a power device, where the method includes:
forming a unit structure of a power device on a substrate, wherein the power device is an IGBT;
forming a front metal layer;
carrying out TAIKO thinning on the back surface of the substrate;
forming a collector region on the back surface of the substrate;
coating a film on the back surface of the substrate;
forming a target metal on the front surface of the substrate by utilizing a chemical plating process;
removing the film attached to the back surface of the substrate;
and forming a metal layer on the back of the substrate.
Optionally, the film attached to the back of the substrate is made of a material resistant to high temperature, strong acid and strong alkali.
Optionally, the forming a target metal on the front surface of the substrate by using an electroless plating process includes:
and plating the target metal on the front metal layer by utilizing an electroless plating process.
Optionally, the target metal includes two layers, a first layer of target metal is nickel, and a second layer of target metal is gold.
Optionally, the target metal includes three layers, a first layer of target metal is nickel, a second layer of target metal is palladium, and a third layer of target metal is gold.
Optionally, in the target metal layer, the thickness of nickel ranges from 0.5um to 20 um.
Optionally, in the target metal layer, the thickness of gold ranges from 500A to 5000A.
Optionally, in the target metal layer, the thickness of the palladium ranges from 500A to 5000A.
Optionally, the forming a unit structure of the power device in the substrate includes:
forming a drift region of the IGBT in the substrate;
forming a base region of the IGBT in the drift region;
forming a gate structure of the IGBT;
a source region is formed in the base region of the IGBT.
The technical scheme at least comprises the following advantages:
after a unit structure of an IGBT device is formed on a substrate, a front metal layer is formed on the front surface of the substrate, the substrate is thinned, a collector region is formed on the back surface of the substrate, a film is coated on the back surface of the substrate before chemical plating, a protective film is utilized to prevent a TAIKO ring on the back surface of a wafer from contacting with a chemical agent utilized by a chemical plating process, a target metal is formed on the front surface of the substrate by the chemical plating process, then the film attached to the back surface of the wafer is removed, and a back metallization process is carried out on the substrate, so that the problem that wafer fragments are easily caused by increasing the thickness and hardness of the front metal by the; the effects of improving the metal falling condition after chemical plating and optimizing the combination effect of the IGBT manufacturing process and the chemical plating process are achieved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a power device according to an embodiment of the present disclosure;
fig. 2 is an implementation schematic diagram of an IGBT device provided in an embodiment of the present application in a manufacturing process;
fig. 3 is an implementation schematic diagram of an IGBT device provided in the embodiment of the present application in a manufacturing process;
fig. 4 is an implementation schematic diagram of an IGBT device provided in the embodiment of the present application in a manufacturing process;
fig. 5 is an implementation schematic diagram of an IGBT device provided in an embodiment of the present application in a manufacturing process;
fig. 6 is an implementation schematic diagram of a manufacturing process of an IGBT device provided in the embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
In the wafer manufacturing process, the wafer warpage is reduced and the strength of the wafer is improved by using the TAIKO process for thinning the back surface, and a TAIKO ring is formed on the back surface of the wafer thinned by using the TAIKO process.
Because the whole heat dissipation requirement of the IGBT chip is higher and higher at present, in order to enhance the thickness and the hardness of the metal on the front surface of the wafer, the metal can be plated on the front surface of the wafer by adopting a chemical plating process. However, in the actual operation of the chemical plating process, metal is attached to the TAIKO ring with an uneven surface, and the metal on the TAIKO ring is easily dropped off after the chemical plating process is completed, and even wafer fragments and machine contamination are caused.
The embodiment of the application provides a manufacturing method of a power device, which comprises the following steps:
step 101, forming a unit structure of a power device on a substrate, wherein the power device is an IGBT.
And 102, forming a front metal layer.
And forming a front metal layer on the front surface of the substrate, and leading out the grid electrode and the source region of the IGBT.
Step 103, performing TAIKO thinning on the back surface of the substrate.
And thinning the substrate according to the thickness requirement and packaging condition of the power device.
And 104, forming a collector region on the back surface of the substrate.
And carrying out ion implantation on the back of the thinned substrate, and annealing to form a collector region of the IGBT.
Step 105, seal the back side of the substrate with a protective material.
The back of the substrate is sealed by the protective material, and when a chemical plating process is carried out subsequently, the chemical agent is isolated from the back of the substrate, so that metal residue on the TAIKO ring part on the back of the substrate is avoided, and the effect of avoiding metal falling off on the TAIKO ring is realized.
The protective material has the characteristics of corrosion resistance, high temperature resistance, strong acid resistance and strong alkali resistance, and can be removed; the protective material does not alter the structure and properties of the backside of the substrate.
Optionally, the protective material has a temperature resistance in the range of at least 25 ℃ to 150 ℃.
And 106, forming a target metal on the front surface of the substrate by utilizing an electroless plating process.
Optionally, the target metal is composed of multiple layers of metals, and the material and thickness of each layer of metal are determined according to actual conditions.
Optionally, the target metal is a layer of metal, for example, the target metal is nickel. The thickness and material of the target metal are determined according to actual conditions.
Step 107, removing the protective material on the back side of the substrate.
And removing the protective material on the back surface of the substrate, wherein the structure and the performance of the back surface of the substrate are not damaged after the protective material is removed.
And step 108, forming a metal layer on the back surface of the substrate.
And depositing metal on the back surface of the substrate to form a metal layer, and leading out the collector region of the IGBT by using the metal layer.
In one example, the protective material is a protective film. The manufacturing method of the power device can be realized by the following steps, as shown in fig. 1:
in step 201, a cell structure of a power device is formed on a substrate, the power device being an IGBT.
The cell structure of the IGBT device comprises a drift region, a base region, a source region, a gate structure and a collector region, wherein the source region, the gate structure and the collector region are located in the base region.
Optionally, a cell structure of one IGBT device or a cell structure of two or more IGBT devices is formed in the substrate, and other devices may also be formed on the substrate.
A drift region of the IGBT is formed in the substrate. An epitaxial layer is arranged on the substrate, and a drift region is formed in the epitaxial layer through an ion implantation process.
Optionally, the substrate is a P-type substrate, and N-type ions are implanted to form an N-drift region.
The base region of the IGBT is formed within the drift region. A base region pattern is defined by a photolithography process, and ions are implanted into the drift region according to the base region pattern to form a base region.
Alternatively, boron ions are implanted into the N-drift region according to the base region pattern to form a base region.
And forming a gate structure of the IGBT. The gate structure of the IGBT is a polysilicon gate or a trench gate positioned on the surface of the substrate.
When the grid structure of the IGBT is a polysilicon grid positioned on the surface of the substrate, a grid oxide layer is formed on the surface of the substrate, a polysilicon layer is deposited on the grid oxide layer, and the polysilicon layer is etched through photoetching and etching processes to obtain the polysilicon grid.
When the grid structure of the IGBT is a groove grid structure, a groove is formed in the substrate through photoetching and etching processes, the bottom of the groove is located in the drift region, a grid oxide layer is formed in the groove, and the groove is filled with polycrystalline silicon to form the groove grid structure.
The source region of the IGBT is formed within the base region by an ion implantation process and annealing.
In step 202, a front side metal layer is formed.
Depositing an interlayer dielectric layer on the front surface of the substrate, and forming a contact hole in the interlayer dielectric layer through photoetching and etching processes; sputtering metal, and forming a front metal layer on the front surface of the substrate through photoetching and etching processes to obtain metal electrodes of the lead-out source region and the grid electrode.
As shown in fig. 2, a front metal layer 12 is formed on the front surface of the substrate 11, and a dielectric layer 13 is also formed on the front surface of the substrate 11.
In step 203, a TAIKO thinning is performed on the backside of the substrate.
And thinning the back surface of the substrate by adopting a TAIKO process.
As shown in fig. 3, after thinning the back surface of the substrate 11, the thickness of the substrate 11 is reduced.
In step 204, a collector region is formed on the back side of the substrate.
And forming a collector region on the back surface of the substrate through an ion implantation process and annealing.
In step 205, a film is coated on the back side of the substrate.
Optionally, when the back surface of the substrate is subjected to a film coating process, the wafer is transferred to a corresponding film coating machine table by using the wafer box, after the wafer is taken down, the annular cutting knife is loaded above the wafer, the wafer is aligned with the annular cutting knife, the protective film is transferred, the protective film is adhered to the back surface of the wafer, the redundant protective film is removed by using the annular cutting knife, and then the wafer with the protective film attached to the back surface is taken down from the machine table and placed into the transfer box.
As shown in fig. 4, a protective film 14 is attached to the back surface of the substrate 11, and the protective film 14 seals the back surface of the substrate 11.
The film attached to the back of the substrate is made of high temperature resistant, strong acid and strong alkali resistant material, and the temperature resistant range is at least 20-150 ℃.
In step 206, a target metal is formed on the front side of the substrate using an electroless plating process.
And plating the target metal on the front metal layer on the front surface of the substrate by using an electroless plating process.
Optionally, the target metal includes two layers, a first layer of target metal is nickel (Ni), and a second layer of target metal is gold (Au). And sequentially plating nickel and gold on the metal electrode on the front surface of the substrate by using a chemical plating process.
Optionally, the target metal includes three layers, a first layer of target metal is (Ni), a second layer of target metal is palladium (Pd), and a third layer of target metal is gold (Au). And sequentially plating nickel, palladium and gold on the metal electrode on the front surface of the substrate by using a chemical plating process.
The thickness of each layer of metal is determined according to actual conditions. Such as: in the target metal layer, the thickness of gold ranges from 500A to 5000A; in the target metal layer, the thickness of the palladium ranges from 500A to 5000A; in the target metal layer, the thickness of nickel ranges from 0.5um to 20 um.
As shown in fig. 5, the front side of the substrate 11 is plated with a target metal 15.
In step 207, the film attached to the back of the substrate is removed.
And removing the protective film attached to the back of the substrate by using a back film uncovering process.
In step 208, a metal layer is formed on the back side of the substrate.
And carrying out metallization process on the back of the substrate to form a metal layer, and leading out the collector region.
As shown in fig. 6, a metal layer 16 is formed on the back surface of the substrate 11.
After a unit structure of an IGBT device is formed on a substrate, a front metal layer is formed on the front surface of the substrate, the substrate is thinned, a collector region is formed on the back surface of the substrate, a film is coated on the back surface of the substrate before chemical plating, a protective film is utilized to prevent a TAIKO ring on the back surface of a wafer from contacting with a chemical agent utilized by a chemical plating process, a target metal is formed on the front surface of the substrate by the chemical plating process, then the film attached to the back surface of the wafer is removed, and a back metallization process is carried out on the substrate, so that the problem that wafer fragments are easily caused by increasing the thickness and hardness of the front metal by the; the effects of improving the metal falling condition after chemical plating and optimizing the combination effect of the IGBT manufacturing process and the chemical plating process are achieved.
In another example, the protective material is a photoresist. The manufacturing method of the power device can be realized by the following steps:
in step 301, a cell structure of a power device is formed on a substrate, the power device being an IGBT.
The cell structure of the IGBT device comprises a drift region, a base region, a source region, a gate structure and a collector region, wherein the source region, the gate structure and the collector region are located in the base region.
Optionally, a cell structure of one IGBT device or a cell structure of two or more IGBT devices is formed in the substrate, and other devices may also be formed on the substrate.
A drift region of the IGBT is formed in the substrate. An epitaxial layer is arranged on the substrate, and a drift region is formed in the epitaxial layer through an ion implantation process.
Optionally, the substrate is a P-type substrate, and N-type ions are implanted to form an N-drift region.
The base region of the IGBT is formed within the drift region. A base region pattern is defined by a photolithography process, and ions are implanted into the drift region according to the base region pattern to form a base region.
Alternatively, boron ions are implanted into the N-drift region according to the base region pattern to form a base region.
And forming a gate structure of the IGBT. The gate structure of the IGBT is a polysilicon gate or a trench gate positioned on the surface of the substrate.
When the grid structure of the IGBT is a polysilicon grid positioned on the surface of the substrate, a grid oxide layer is formed on the surface of the substrate, a polysilicon layer is deposited on the grid oxide layer, and the polysilicon layer is etched through photoetching and etching processes to obtain the polysilicon grid.
When the grid structure of the IGBT is a groove grid structure, a groove is formed in the substrate through photoetching and etching processes, the bottom of the groove is located in the drift region, a grid oxide layer is formed in the groove, and the groove is filled with polycrystalline silicon to form the groove grid structure.
In step 302, a front side metal layer is formed.
Depositing an interlayer dielectric layer on the front surface of the substrate, and forming a contact hole in the interlayer dielectric layer through photoetching and etching processes; sputtering metal, and forming a front metal layer on the front surface of the substrate through photoetching and etching processes to obtain metal electrodes of the lead-out source region and the grid electrode.
In step 303, a TAIKO thinning is performed on the backside of the substrate.
And thinning the back surface of the substrate by adopting a TAIKO process.
In step 304, a collector region is formed on the back side of the substrate.
And forming a collector region on the back surface of the substrate through an ion implantation process and annealing.
In step 305, a photoresist is coated on the back side of the substrate.
And coating photoresist on the back surface of the substrate, exposing, covering the back surface of the substrate by using the photoresist, and preventing the TAIKO ring part on the back surface from contacting with chemical liquid in the chemical plating process.
In step 306, a target metal is formed on the front side of the substrate using an electroless plating process.
And plating the target metal on the front metal layer on the front surface of the substrate by using an electroless plating process.
Optionally, the target metal includes two layers, a first layer of target metal is nickel (Ni), and a second layer of target metal is gold (Au). And sequentially plating nickel and gold on the metal electrode on the front surface of the substrate by using a chemical plating process.
Optionally, the target metal includes three layers, a first layer of target metal is (Ni), a second layer of target metal is palladium (Pd), and a third layer of target metal is gold (Au). And sequentially plating nickel, palladium and gold on the metal electrode on the front surface of the substrate by using a chemical plating process.
The thickness of each layer of metal is determined according to actual conditions. Such as: in the target metal layer, the thickness of gold ranges from 500A to 5000A; in the target metal layer, the thickness of the palladium ranges from 500A to 5000A; in the target metal layer, the thickness of nickel ranges from 0.5um to 20 um.
In step 307, the photoresist on the back side of the substrate is removed.
In step 308, a metal layer is formed on the back side of the substrate.
And carrying out metallization process on the back of the substrate to form a metal layer, and leading out the collector region.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (9)
1. A method of fabricating a power device, the method comprising:
forming a unit structure of a power device on a substrate, wherein the power device is an IGBT;
forming a front metal layer;
carrying out TAIKO thinning on the back surface of the substrate;
forming a collector region on the back surface of the substrate;
coating a film on the back surface of the substrate;
forming a target metal on the front surface of the substrate by utilizing a chemical plating process;
removing the film attached to the back surface of the substrate;
and forming a metal layer on the back of the substrate.
2. The method of claim 1, wherein the film attached to the back of the substrate is a material that is resistant to high temperatures and strong acids and bases.
3. The method of claim 1, wherein forming a target metal on the front side of the substrate using an electroless plating process comprises:
and plating the target metal on the front metal layer by utilizing an electroless plating process.
4. A method according to claim 1 or 3, wherein the target metal comprises two layers, a first layer of target metal being nickel and a second layer of target metal being gold.
5. The method of claim 1 or 3, wherein the target metals comprise three layers, a first layer of target metal being nickel, a second layer of target metal being palladium, and a third layer of target metal being gold.
6. The method of claim 4 or 5, wherein the thickness of nickel in the target metal layer is in the range of 0.5um to 20 um.
7. The method of claim 4 or 5, wherein the thickness of gold in the target metal layer is in the range of 500A to 5000A.
8. The method of claim 5, wherein the thickness of the palladium in the target metal layer is in a range of 500A to 5000A.
9. The method of claim 1, wherein forming a cell structure of a power device in a substrate comprises:
forming a drift region of the IGBT in the substrate;
forming a base region of the IGBT in the drift region;
forming a gate structure of the IGBT;
and forming a source region in the base region of the IGBT.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN114045474A (en) * | 2022-01-14 | 2022-02-15 | 绍兴中芯集成电路制造股份有限公司 | Method for preventing chemical plating liquid seepage and method for preparing semiconductor device |
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| CN103794487A (en) * | 2012-10-26 | 2014-05-14 | 富士电机株式会社 | Semiconductor device manufacturing method |
| CN105103272A (en) * | 2013-09-27 | 2015-11-25 | 富士电机株式会社 | Method for manufacturing semiconductor device |
| US20190148306A1 (en) * | 2016-06-30 | 2019-05-16 | Semiconductor Components Industries, Llc | Semiconductor backmetal and over pad metallization structures and related methods |
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| CN103794487A (en) * | 2012-10-26 | 2014-05-14 | 富士电机株式会社 | Semiconductor device manufacturing method |
| CN105103272A (en) * | 2013-09-27 | 2015-11-25 | 富士电机株式会社 | Method for manufacturing semiconductor device |
| US20190148306A1 (en) * | 2016-06-30 | 2019-05-16 | Semiconductor Components Industries, Llc | Semiconductor backmetal and over pad metallization structures and related methods |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114045474A (en) * | 2022-01-14 | 2022-02-15 | 绍兴中芯集成电路制造股份有限公司 | Method for preventing chemical plating liquid seepage and method for preparing semiconductor device |
| CN114045474B (en) * | 2022-01-14 | 2022-04-15 | 绍兴中芯集成电路制造股份有限公司 | Method for preventing chemical plating liquid seepage and method for preparing semiconductor device |
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