CN112289867B - High-power high-voltage Schottky barrier diode - Google Patents
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- 230000004888 barrier function Effects 0.000 title claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 60
- 229910052751 metal Inorganic materials 0.000 claims abstract description 60
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 29
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- 239000002019 doping agent Substances 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 238000005530 etching Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005275 alloying Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000004347 surface barrier Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/66257—Schottky transistors
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Abstract
The invention discloses a high-power high-voltage Schottky barrier diode in the technical field of diodes, which comprises: a back metal layer; the N + substrate is arranged above the back metal layer; the N epitaxial layer is arranged above the N + substrate, and the upper part of the N epitaxial layer is provided with a heavily doped anode region; the metal silicide layer is arranged above the N epitaxial layer and is in contact with the heavily doped anode region; and the front metal layer is arranged above the metal silicide layer and covers the metal silicide layer. The heavily doped anode region of the diode is matched with the metal silicide layer on the heavily doped anode region and the front metal layer to form an independent ESD discharge region, so that the influence on the SSG (stress-induced breakdown) capability of the diode is reduced, the chip can obtain extremely high ESD capability and SSG capability at the same time, and the reliability of the device is greatly improved.
Description
Technical Field
The invention relates to the technical field of diodes, in particular to a high-power high-voltage Schottky barrier diode.
Background
Schottky barrier diodes are named by their inventor schottky doctor and utilize the metal-semiconductor junction principle formed by metal-to-semiconductor contact. Thus, an SBD is also known as a metal-semiconductor (contact) diode or surface barrier diode, which is a single-carrier diode.
Currently, the high-power high-voltage schottky barrier diode gradually develops towards high reliability, the reliability of the high-power high-voltage schottky barrier diode is paid more and more attention by customers, typical reliability indexes include HTRB, PCT, IFSM, ESD, SSG and the like, and the ESD capability and the SSG capability are particularly paid attention by high-voltage high-power SBD customers. However, there is a contradiction between ESD and SSG in conventional high power high voltage schottky barrier diodes, i.e., increasing ESD capability results in a decrease in SSG capability and vice versa.
Disclosure of Invention
The high-power high-voltage Schottky barrier diode solves the problem of compromise limitation of ESD and SSG capacity of the traditional high-power high-voltage Schottky barrier diode in the prior art, and can enable a device to obtain extremely high ESD capacity and SSG capacity at the same time.
The embodiment of the application provides a high-power high-voltage Schottky barrier diode, includes:
a back metal layer;
an N + substrate disposed above the back side metal layer;
the N epitaxial layer is arranged above the N + substrate, and a heavily doped anode region is arranged at the upper part of the N epitaxial layer;
a metal silicide layer disposed over the N epitaxial layer, the metal silicide layer in contact with the heavily doped anode region;
and the front metal layer is arranged above the metal silicide layer and covers the metal silicide layer.
The beneficial effects of the above embodiment are as follows: the upper part of the N epitaxial layer is provided with a heavily doped anode region, and the heavily doped anode region is matched with the metal silicide layer on the N epitaxial layer and the front metal layer to form an independent ESD discharge region.
On the basis of the above embodiments, the present application can be further improved, specifically as follows:
in one embodiment of the present disclosure, a trench is formed on an upper surface of the N epitaxial layer, and the heavily doped anode region is disposed at a bottom of the trench. The metal silicide layer is matched with the groove to cover the upper surface of the heavily doped anode, and the front metal layer is positioned above the metal silicide layer and fills the groove, so that the series resistance of the heavily doped anode is obviously reduced, and the ESD capability of the device is improved.
In one embodiment of the present application, the heavily doped anode region has a dopant amount in the range of 3e14/cm2～3e16/cm2. Dosage below 3e14/cm2The ESD protection effect is poor, and the dosage is higher than 3e16/cm2The ESD protection capability no longer increases with increasing dose.
In one embodiment of the present application, the heavily doped anode region has a dopant amount in the range of 1e15/cm2～1e16/cm2. The doping amount of the heavily doped anode region is controlled to be 1e by comprehensively considering the cost and the ESD protection effect15/cm2～1e16/cm2And meanwhile, the cost is lower, and the ESD protection effect is better.
In one embodiment of the present application, the heavily doped anode region is composed of one or more of a lightly doped P-type semiconductor, a heavily doped P-type semiconductor, and a heavily doped N-type semiconductor.
In one embodiment of the present application, a P + guard ring is further disposed on the N epitaxial layer, and the guard ring is disposed around the heavily doped anode region.
In one embodiment of the present application, a region surrounded by the guard ring is an active region, and the heavily doped anode region is provided with a plurality of blocks and is distributed at the periphery of the active region. The active region is a semiconductor region through which current flows when the device is conducted in the forward direction, and the heavily doped anode region is arranged on the periphery of the active region, so that the influence on the SSG capability of the device is reduced.
In one embodiment of the present application, the active region is rectangular, the corners of the active region are arc-shaped, the heavily doped anode region is provided with four blocks and distributed at the corners of the active region, and the heavily doped anode region is fan-shaped and has a radius larger than the radius of the arc-shaped active region corners. The heavily doped anode region is positioned at the corner of the active region, so that the resistance of the curvature can be reduced, the current concentration effect is reduced, the high-temperature working stability of the device is improved, and the ESD limit capability is improved as much as possible on the basis of reducing the influence on the SSG capability of the device.
In one embodiment of the present application, a dopant amount of the guard ring is not higher than a dopant amount of the heavily doped anode region.
In one embodiment of the present application, a thin oxygen layer is disposed between the guard ring and the front metal layer, and a field oxygen layer is disposed around an upper surface of the N epitaxial layer.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
the structure is characterized in that a heavily doped anode region is arranged on the upper part of an N epitaxial layer, and an independent ESD discharge region is formed by matching a metal silicide layer on the heavily doped anode region with a front metal layer;
2. the metal silicide layer is matched with the groove to cover the upper surface of the heavily doped anode, and the front metal layer is positioned above the metal silicide layer and fills the groove, so that the series resistance of the heavily doped anode is obviously reduced, and the ESD (electro-static discharge) capability of the device is improved;
and 3, the ESD discharge area is positioned at the corner of the active area, so that the resistance of the curvature part can be reduced, the current concentration effect is reduced, and the high-temperature working stability of the device is improved.
Drawings
In order to more clearly illustrate the detailed description of the invention or the technical solutions in the prior art, the drawings that are needed in the detailed description of the invention or the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.
FIG. 1 is a schematic structural diagram according to a first embodiment;
FIG. 2 is a schematic cross-sectional view of the first embodiment;
FIG. 3 is a schematic structural diagram according to a second embodiment;
fig. 4 is a schematic cross-sectional view of the second embodiment.
The structure comprises a back metal layer 1, a 2.N + substrate, a 3.N epitaxial layer, a heavily doped anode region 4, a guard ring 5, a metal silicide layer 6, a thin oxygen layer 7, a field oxygen layer 8 and a front metal layer 9.
Detailed Description
The present invention is further illustrated by the following detailed description, which is to be construed as merely illustrative and not limitative of the remainder of the disclosure, and modifications and variations such as those ordinarily skilled in the art are intended to be included within the scope of the present invention as defined in the appended claims.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "vertical", "peripheral surface" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the present invention are conventionally placed when used, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or the element to which the present invention is directed must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In describing the invention, it is not necessary for a schematic representation of the above terminology to be directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples of the invention and features of different embodiments or examples described herein may be combined and combined by those skilled in the art without contradiction.
The embodiment of the application provides the high-power high-voltage Schottky barrier diode, so that the compromise limitation of ESD and SSG capabilities of the traditional high-power high-voltage Schottky barrier diode in the prior art is solved, and the device can obtain extremely high ESD capability and SSG capability at the same time.
In order to solve the above problems, the technical solution in the embodiment of the present application has the following general idea:
the first embodiment is as follows:
as shown in fig. 1-2, a high power high voltage schottky barrier diode sequentially includes, from bottom to top: the structure comprises a back metal layer 1, an N + substrate 2, an N epitaxial layer 3, a metal silicide layer 6 and a front metal layer 9; a heavily doped anode region 4 and a P + protection ring 5 are arranged on the upper part of the N epitaxial layer 3, the protection ring 5 is arranged around the heavily doped anode region 4, a groove is formed in the upper surface of the N epitaxial layer 3, the heavily doped anode region 4 is arranged at the bottom of the groove, a metal silicide layer 6 is arranged along the groove, the upper surfaces of the heavily doped anode region 4 and the protection ring 5 are both contacted with the lower surface of the metal silicide layer 6, and the heavily doped anode region 4 at the bottom of the groove is matched with the metal silicide layer 6 and a front metal layer 9 on the heavily doped anode region to form an independent ESD discharge region; a thin oxygen layer 7 is arranged between the protection ring 5 and the front metal layer 9, a field oxygen layer 8 is arranged between the N epitaxial layer 3 and the front metal layer 9, and the field oxygen layer is arranged around the upper surface of the N epitaxial layer 3.
Wherein, the heavily doped anode of the ESD discharge region is composed of one or more of a lightly doped P-type semiconductor, a heavily doped P-type semiconductor and a heavily doped N-type semiconductor, and the doping dose range of the heavily doped anode region 4 is 3e14/cm2～3e16/cm2Preferably 1e15/cm2～1e16/cm2. The guard ring 5 has a dopant amount no higher than that of the heavily doped anode region 4.
Example two:
as shown in fig. 3-4, in the first embodiment, an area surrounded by a guard ring 5 is an active area, the active area is rectangular, corners of the active area are arc-shaped, four heavily doped anode regions 4 are disposed and distributed at the corners of the active area, and the radius of the heavily doped anode regions 4 is fan-shaped and is greater than the radius of the arc-shaped area at the corners of the active area.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
the structure is characterized in that a heavily doped anode region is arranged on the upper part of an N epitaxial layer, and an independent ESD discharge region is formed by matching a metal silicide layer on the heavily doped anode region with a front metal layer;
2. the metal silicide layer is matched with the groove to cover the upper surface of the heavily doped anode, and the front metal layer is positioned above the metal silicide layer and fills the groove, so that the series resistance of the heavily doped anode is obviously reduced, and the ESD (electro-static discharge) capability of the device is improved;
and 3, the ESD discharge area is positioned at the corner of the active area, so that the resistance of the curvature part can be reduced, the current concentration effect is reduced, and the high-temperature working stability of the device is improved.
Example three:
a preparation method of the diode for realizing the structure of the embodiment comprises the following steps:
step 1: forming an N epitaxial layer on an N + substrate;
step 2: forming field oxygen on the N epitaxial layer;
and step 3: forming a protection ring and thin oxygen on the N epitaxial layer and the field oxygen through photoetching, etching, injection, photoresist removal and annealing;
and 4, step 4: forming a groove on the N epitaxial layer and the field oxide through photoetching and etching;
and 5: forming a heavily doped anode below the groove in the N epitaxial layer through injection, photoresist removal and annealing;
step 6: forming a contact hole above the N epitaxial layer, the field oxide layer, the thin oxide layer and the groove through photoetching, etching and photoresist removal, wherein the contact hole is used for forming a metal silicide layer window;
and 7: forming a metal silicide layer on the contact hole by depositing a barrier metal layer, rapidly annealing, alloying and removing redundant barrier metal layer;
and 8: forming a back gold metal layer on the back of the N + substrate by thinning, slightly etching and depositing a plurality of layers of metal;
and step 9: and forming a front metal layer above the N epitaxial layer, the field oxide layer, the thin oxide layer and the metal silicide layer by the processes of depositing multiple layers of metal, photoetching, etching and the like.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (6)
1. A high power high voltage schottky barrier diode comprising:
a back metal layer;
an N + substrate disposed above the back side metal layer;
the N epitaxial layer is arranged above the N + substrate, a heavily doped anode region is arranged at the upper part of the N epitaxial layer, a P + protection ring is further arranged on the N epitaxial layer, the protection ring is arranged around the heavily doped anode region in a surrounding manner, an area surrounded by the protection ring is an active area, the active area is rectangular, the corners of the active area are arc-shaped, the heavily doped anode region is provided with four blocks and is distributed at the corners of the active area, and the radius of the heavily doped anode region is fan-shaped and is larger than the radius of the arc-shaped corners of the active area;
a metal silicide layer disposed over the N epitaxial layer, the metal silicide layer in contact with the heavily doped anode region;
and the front metal layer is arranged above the metal silicide layer and covers the metal silicide layer.
2. The diode of claim 1, wherein: the upper surface of the N epitaxial layer is provided with a groove, and the heavily doped anode region is arranged at the bottom of the groove.
3. The diode of claim 1, wherein: the doping dose range of the heavily doped anode region is 3e14/cm2～3e16/cm2。
4. The diode of claim 3, wherein: the doping dose range of the heavily doped anode region is 1e15/cm2～1e16/cm2。
5. The diode of claim 1, wherein: the guard ring has a dopant amount no higher than a dopant amount of the heavily doped anode region.
6. The diode of claim 1, wherein: a thin oxygen layer is arranged between the protection ring and the front metal layer, and a field oxygen layer is arranged on the periphery of the upper surface of the N epitaxial layer.
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| WO2011101956A1 (en) * | 2010-02-16 | 2011-08-25 | 株式会社三社電機製作所 | Pin diode |
| JP2013125928A (en) * | 2011-12-16 | 2013-06-24 | Mitsubishi Electric Corp | Semiconductor device |
| JP2015008281A (en) * | 2013-05-29 | 2015-01-15 | 三菱電機株式会社 | Semiconductor device and manufacturing method of the same |
| CN107170836A (en) * | 2017-05-17 | 2017-09-15 | 扬州扬杰电子科技股份有限公司 | The preparation method of cellular domain, structure cell and silicon carbide junction barrier schottky diodes |
| CN211350657U (en) * | 2020-03-09 | 2020-08-25 | 瑞能半导体科技股份有限公司 | Power device |
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