CN113394170B - Package structure and method for manufacturing the same - Google Patents
Package structure and method for manufacturing the same Download PDFInfo
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- CN113394170B CN113394170B CN202110450207.9A CN202110450207A CN113394170B CN 113394170 B CN113394170 B CN 113394170B CN 202110450207 A CN202110450207 A CN 202110450207A CN 113394170 B CN113394170 B CN 113394170B
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- cavity
- substrate
- circuit layer
- manufacturing
- package structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
- H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
Abstract
The invention discloses a packaging structure and a manufacturing method thereof, wherein the method comprises the steps of forming a plurality of cavity structures on a substrate in an embedding and injecting mode; then, forming a circuit layer on each cavity structure in a laser forming mode; then, carrying out surface treatment on the circuit layer; subsequently carrying out die bonding and wire bonding; and finally, covering the covering structures on the cavity structures, wherein each covering structure and the circuit layer are arranged in a matched mode, so that each cavity structure forms a conducting loop. Therefore, the packaging process can be simplified, the production efficiency is improved, and in addition, the application of the packaging structure is further optimized.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing processes, in particular to a packaging structure and a manufacturing method thereof.
Background
In the field of semiconductor manufacturing process, a packaging structure is used as a chip carrier of an integrated circuit, is a key structural member for realizing the electrical connection between a circuit leading-out end inside a chip and an external lead by means of bonding materials (gold wires, aluminum wires, copper wires and the like) to form an electrical circuit, plays a role of a bridge connected with an external lead, needs to be used in most semiconductor integrated blocks, and is an important basic element in the electronic information industry.
Most of the conventional package structures are formed by bonding a plurality of layers of different materials one by one, and include a bottom conductive substrate, a pillar structure (Holder) having a hollow area in the middle, and a top glass cover plate. The package body is high in overall height, and is formed by bonding a plurality of layers of different materials, so that the problem of warping is caused after the different materials are bonded in the production process, and the subsequent cutting process is influenced. Therefore, the packages can be produced only by individually bonding the packages, which is inefficient.
In addition, when a multi-layer material bonding technology is adopted, a certain proportion of risks are caused to the overall quality control and management in each bonding operation.
However, in order to simplify the above process, an EMC (Epoxy Molding Compound) type package or a PLCC (Plastic Leaded Chip Carrier) type package is used, and thus a complicated structure design cannot be realized on the package.
Therefore, the present invention is directed to a package structure and a method for manufacturing the same to solve the above-mentioned problems.
Disclosure of Invention
The present invention provides a package structure and a method for manufacturing the same, which can simplify the whole packaging process, improve the production efficiency of the package structure, and further optimize the application of the package structure.
To achieve at least one of the above advantages or other advantages, an embodiment of the present invention provides a method for manufacturing a package structure, including:
step one, forming a plurality of cavity structures on a substrate in an Insert Molding mode (Insert Molding); step two, forming a circuit layer on each cavity structure in a Laser Direct Structuring mode; step three, carrying out surface treatment on the circuit layer; step four, carrying out die bonding and wire bonding; covering and connecting the covering structures to the cavity structures, wherein each covering structure and the circuit layer are arranged in a matched mode, and therefore each cavity structure forms a conducting loop.
In some embodiments, the cavity structure is a plastic structure. In other words, the whole cavity structure is made of plastic material, which can protect the internal elements of the cavity and has the effect of electrical insulation.
In some embodiments, the substrate is one selected from a metal substrate, a ceramic substrate, a printed circuit board, and a flexible circuit board.
In some embodiments, step three further comprises: and performing surface treatment on the circuit layer in an electroplating or chemical plating mode.
In some embodiments, the cover structure is made of a light transmissive material.
Further, an ITO (Indium Tin Oxide) film layer is plated on the surface of the covering structure, and the ITO film layer and the circuit layer form an electronic circuit.
Furthermore, the surface of the covering structure may also be plated with a metal layer, and the metal layer and the circuit layer form an electronic loop.
In some embodiments, step five is followed by the steps of: and carrying out cutting operation processing on the substrate to form a plurality of independent packaging elements.
In some embodiments, the cover structure covers a side of the cavity structure away from the substrate.
To achieve at least one of the advantages or other advantages, a package structure manufactured by the method for manufacturing a package structure according to any one of the above embodiments is further provided.
Therefore, the package structure and the manufacturing method thereof provided by the invention can simplify the whole packaging process and improve the production efficiency of the package structure. In addition, the application of the packaging structure can be further optimized, specifically, the circuit layer of a single packaging element obtained by cutting is matched with the covering structure plated with the ITO film layer, so that the covering structure can be separated from the cavity structure to form an open circuit when an application end device is impacted by impact, the work of the packaging element is stopped, and the damage of energy emitted by a wafer for die bonding to human eyes is reduced.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described below in detail with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It should be apparent that the drawings in the following description are only examples of the present application and are not intended to limit the embodiments of the present invention, and that other drawings may be derived from the drawings by those skilled in the art without inventive faculty. The drawings comprise:
FIG. 1 is a schematic flow chart of a method for manufacturing a package structure according to the present invention; and
FIG. 2 is a schematic diagram of a process for fabricating a package structure according to the present invention; and
fig. 3 is a schematic cross-sectional view of a package structure at various stages in its manufacture.
The attached drawings are marked as follows: 10-a packaging structure; 12-a substrate; 14-a cavity structure; 16-a line layer; 18-cover structure.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations and positional relationships based on those shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or component in question must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be taken as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. In addition, the term "comprises" and any variations thereof mean "including at least".
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integrally formed connection; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, and the two components can be communicated with each other. The specific meanings of the above terms in the present invention can be understood in a specific case to those of ordinary skill in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Referring to fig. 1, fig. 2 and fig. 3, fig. 1 is a flow chart illustrating a method for manufacturing a package structure 10 according to the present invention, fig. 2 is a schematic diagram illustrating a process for manufacturing the package structure 10 according to the present invention, and fig. 3 is a schematic cross-sectional diagram illustrating each stage in the process for manufacturing the package structure 10. To achieve at least one of the above advantages or other advantages, a method for manufacturing a package structure 10 is provided in an embodiment of the invention. As shown in the figure, the manufacturing method of the package structure 10 includes the following steps:
s100: forming a plurality of cavity structures on the substrate in an embedding and ejecting mode;
s200: forming a circuit layer on each cavity structure in a laser forming mode;
s300: carrying out surface treatment on the circuit layer;
s400: carrying out die bonding and wire bonding;
s500: and covering the covering structure on the cavity structure.
Further, in step S100, the Insert Molding process (Insert Molding process) refers to a Molding method in which a cavity structure 14 formed by filling a predetermined Insert made of a different material into a substrate 12, injecting a resin, and joining and curing the molten material and the Insert is integrated with the substrate 12. In one embodiment, the cavity structure 14 is made of a plastic material, in other words, the cavity structure 14 is a plastic structure.
In step S200, the Laser Direct Structuring (Laser Direct Structuring) is based on the principle that a common plastic element or circuit board is provided with the functions of electrical interconnection, supporting components, supporting and protecting the plastic housing, and the functions of shielding and antenna, which are generated by the combination of the mechanical entity and the conductive pattern, to form the circuit layer 16.
In step S300, the surface treatment is performed by electroplating or chemical plating to treat the surface of the circuit layer 16, so as to prevent the circuit layer 16 from being oxidized, and if it is required to meet other special functional requirements, the surface treatment can be performed accordingly. For example, organic Solderability Preservative (OSP) is plated, silver is plated, nickel gold is plated, nickel palladium gold is plated, and the like. Taking as an example the cross-sectional view of fig. 3 corresponding to the surface treatment step, the dashed box is shown as surface treating the wiring layer 16.
In step S500, the cover structure 18 is attached to the cavity structure 14 on a side away from the substrate 12, that is, the cover structure 18 is attached above the cavity structure 14. Each of the capping structures 18 and the circuit layer 16 are disposed in a matching manner, so that each of the cavity structures 14 forms a conductive loop. Specifically, the capping structure 18 and the wiring layer 16 form an electronic circuit. In an embodiment, an ITO (Indium Tin Oxide) film is plated on the surface of the covering structure 18, and the ITO film and the circuit layer 16 form an electronic circuit, which can ensure good conductivity, visible light transmittance, and chemical stability. In one embodiment, the surface of the cover structure 18 is plated with a metal layer, and the metal layer and the circuit layer 16 form an electronic circuit, and the metal layer can be used for welding, which helps to improve the overall airtightness.
After step S500 is completed, a dicing operation, i.e., a process of a dicing operation, may also be performed on the substrate 12 to form a plurality of individual package elements. The cavity structures 14 are arranged on the substrate 12 in an array, and the cutting operation is performed at equal intervals along the gaps between the cavity structures 14.
In one embodiment, the cover structure 18 is made of a light-transmitting material. For example, glass, a laminate structure of glass and polymer, quartz, resin, or the like has a light-transmitting property. The substrate 12 may be one selected from a metal substrate 12, a ceramic substrate 12, a printed circuit board, and a flexible circuit board, and may be selected according to actual needs. To further illustrate, the glass-on-glass illustration of fig. 2 and 3 corresponds to step S500 of the present invention for covering the covering structure 18.
To achieve at least one of the advantages or other advantages, a package structure 10 is further provided in another embodiment of the present invention. The package structure 10 is manufactured according to the manufacturing method of the package structure 10 in the foregoing embodiment. The package structure 10 includes a substrate 12, a cavity structure 14, a circuit layer 16, and a cover structure 18. The cavity structure 14 is disposed on the substrate 12. The surface of the cavity structure 14 forms a wiring layer 16. The cover structure 18 is capped onto the cavity structure 14.
In summary, the package structure 10 and the manufacturing method thereof provided by the present invention can simplify the whole packaging process and improve the production efficiency of the package structure 10. In addition, the application of the package structure 10 can be further optimized, specifically, the circuit layer 16 of the single package component obtained by cutting is matched with the cover structure 18 plated with the ITO film layer, so that when the application end device is impacted, the cover structure 18 can be separated from the cavity structure 14 to form an open circuit, thereby stopping the operation of the package component and reducing the harm of energy emitted by the die bonding wafer to human eyes.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (4)
1. A manufacturing method of a package structure is characterized by comprising the following steps:
forming a plurality of cavity structures on the substrate in an embedding and ejecting mode;
forming a circuit layer on each cavity structure in a laser forming mode;
carrying out surface treatment on the circuit layer;
carrying out die bonding and wire bonding; and
covering and connecting covering structures to the cavity structures, wherein the covering structures and the circuit layer are arranged in a matched mode, so that the cavity structures form a conducting loop;
wherein the cavity structure is a plastic structure; the substrate is one selected from a metal substrate, a ceramic substrate and a printed circuit board; the covering structure is made of a light-transmitting material; the cover structure is covered on one side of the cavity structure far away from the substrate, an ITO film layer or a metal layer is plated on the surface of the cover structure, and an electronic loop is formed by the ITO film layer or the metal layer and the circuit layer.
2. The method of manufacturing a package structure according to claim 1, wherein the step of surface treating the circuit layer further comprises: and performing surface treatment on the circuit layer in an electroplating or chemical plating mode.
3. The method of manufacturing a package structure according to claim 1, further comprising the following steps after the step of fixing the cover structure to the cavity structure: and carrying out cutting operation processing on the substrate to form a plurality of independent packaging elements.
4. A package structure, characterized in that the package structure is manufactured by the method for manufacturing a package structure according to any one of claims 1 to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110450207.9A CN113394170B (en) | 2021-04-25 | 2021-04-25 | Package structure and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110450207.9A CN113394170B (en) | 2021-04-25 | 2021-04-25 | Package structure and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
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| CN113394170A CN113394170A (en) | 2021-09-14 |
| CN113394170B true CN113394170B (en) | 2022-10-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110450207.9A Active CN113394170B (en) | 2021-04-25 | 2021-04-25 | Package structure and method for manufacturing the same |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0745751A (en) * | 1993-07-30 | 1995-02-14 | Nippon Chemicon Corp | Sealing structure of circuit element |
| JP2015015477A (en) * | 2014-08-06 | 2015-01-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| CN104465950A (en) * | 2014-12-02 | 2015-03-25 | 深圳市华星光电技术有限公司 | Light-emitting diode and manufacturing method of light-emitting diode |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0831968A (en) * | 1994-07-15 | 1996-02-02 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacture |
| US7295029B2 (en) * | 2005-03-24 | 2007-11-13 | Memsic, Inc. | Chip-scale package for integrated circuits |
| JP2010040655A (en) * | 2008-08-01 | 2010-02-18 | Yamaha Corp | Package body for semiconductor device and method of manufacturing the same, package, semiconductor device, and microphone package |
| US8546841B2 (en) * | 2009-07-30 | 2013-10-01 | Nichia Corporation | Light emitting device |
| CN102185090B (en) * | 2011-03-29 | 2013-08-21 | 晶科电子（广州）有限公司 | Luminescent device adopting COB (chip on board) packaging and manufacturing method thereof |
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2021
- 2021-04-25 CN CN202110450207.9A patent/CN113394170B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0745751A (en) * | 1993-07-30 | 1995-02-14 | Nippon Chemicon Corp | Sealing structure of circuit element |
| JP2015015477A (en) * | 2014-08-06 | 2015-01-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| CN104465950A (en) * | 2014-12-02 | 2015-03-25 | 深圳市华星光电技术有限公司 | Light-emitting diode and manufacturing method of light-emitting diode |
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| CN113394170A (en) | 2021-09-14 |
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