CN113363243A - 用于耦接多个半导体装置的设备和方法 - Google Patents
用于耦接多个半导体装置的设备和方法 Download PDFInfo
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- CN113363243A CN113363243A CN202110225352.7A CN202110225352A CN113363243A CN 113363243 A CN113363243 A CN 113363243A CN 202110225352 A CN202110225352 A CN 202110225352A CN 113363243 A CN113363243 A CN 113363243A
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- Semiconductor Integrated Circuits (AREA)
Abstract
公开了用于耦接多个半导体装置的设备和方法。可以通过将半导体装置的一或多个端子耦接到两个导电接合焊盘的导电结构以菊链的方式耦接多个半导体装置的端子(例如,管芯焊盘)。所述导电结构可以包含在重新分布层RDL结构中。在本公开的一些实施例中,所述RDL结构可以为“U”形。所述“U”形的每一端可以耦接到所述两个导电接合焊盘中的相应一个导电接合焊盘,并且所述半导体装置的所述端子可以耦接到所述RDL结构。半导体装置的所述导电接合焊盘可以通过导体(例如,接合线)耦接到其它半导体装置的导电接合焊盘。因此,所述半导体装置的所述端子可以通过所述RDL结构、导电接合焊盘和导体以菊链的方式耦接。
Description
技术领域
本申请涉及半导体,并且具体地涉及用于耦接多个半导体装置的设备和方法。
背景技术
近年来,已经引进了三维(3D)存储器装置。一些3D存储器装置通过竖直堆叠管芯并且使用硅穿(或衬底穿)孔(TSV)和/或引线接合耦接管芯而形成。因此,3D存储器也可以被称为“堆叠的存储器”。与非3D存储器相比,3D存储器可以提供更大的存储器容量和/或更高的带宽,而面积增加更少。示例3D存储器装置包含混合存储器立方体(HMC)、高带宽存储器(HBM)和主从存储器(MSM),所述HMC、所述HBM和所述MSM中的每一个可以包含在堆叠中彼此耦接的多个动态随机存取存储器(DRAM)管芯。
存储器装置可以耦接到外部电路,所述外部电路向堆叠的管芯提供命令信号、地址信号和数据信号以存取存储器。堆叠的管芯通常以并联方式耦接到外部电路。因此,在向堆叠的管芯提供信号时,外部电路驱动信号抵靠所有管芯的可能是大量的负载。堆叠的管芯所呈现的重负载可以降低信号完整性(SI),这可能会使数据在接收器处被不正确地锁存,和/或导致功耗增加。在一些应用中,降低的SI和增加的功率可能是不可接受的。
发明内容
在一方面,本申请涉及一种设备,其包括:多个半导体装置,所述多个半导体装置包含第一半导体装置、第二半导体装置和第三半导体装置,所述多个半导体装置中的每个半导体装置包含耦接到相应半导体装置的至少一个电路的管芯焊盘,并且进一步包含耦接到所述管芯焊盘并进一步耦接到第一接合焊盘和第二接合焊盘的重新分布层结构,其中所述第一半导体装置的所述第二接合焊盘耦接到所述第二半导体装置的所述第一接合焊盘,并且所述第二半导体装置的所述第二接合焊盘耦接到所述第三半导体装置的所述第一接合焊盘。
在另一方面,本申请涉及一种多管芯装置,其包括:衬底,所述衬底包含导电信号线;半导体装置的堆叠,所述堆叠附接到所述衬底,所述堆叠中的所述半导体装置中的每个半导体装置包含端子和耦接到所述端子的重新分布层结构,并且其中所述堆叠中的所述半导体装置的所述端子通过所述重新分布层结构以菊链的形式耦接在一起;以及电路,所述电路附接到所述衬底并且通过所述导电信号线耦接到半导体装置的所述堆叠中的第一半导体装置。
在另一方面,本申请涉及一种设备,其包括:存储器阵列,所述存储器阵列被配置成存储数据;端子;输入/输出电路,所述输入/输出电路被配置成从所述存储器阵列接收数据并提供读取数据,并且接收要存储在所述存储器阵列中的写入数据;命令和地址输入电路,所述命令和地址输入电路被配置成接收命令和地址信号;第一接合焊盘和第二接合焊盘;以及U形导电结构,所述U形导电结构耦接到所述端子并且包含在所述端子与所述第一接合焊盘之间延伸并耦接到所述端子和所述第一接合焊盘的第一部分,并且进一步包含在所述端子与所述第二接合焊盘之间延伸并耦接到所述端子和所述第二接合焊盘的第二部分。
在另一方面,本申请涉及一种方法,其包括:将第一半导体装置的接合焊盘耦接到第一U形导电结构;将第二半导体装置的接合焊盘耦接到第二U形导电结构;将第三半导体装置的接合焊盘耦接到第三U形导电结构;将所述第一U形导电结构的第二部分耦接到所述第二U形导电结构的第一部分;以及将所述第二U形导电结构的第二部分耦接到所述第三U形导电结构的第一部分,其中将所述第一U形导电结构的第一部分耦接到电路,并且其中将所述第三U形导电结构的第二部分耦接到第四半导体装置。
附图说明
图1是根据本公开的实施例的半导体装置的框图。
图2是示出了根据本公开的实施例的多管芯装置的图。
图3是根据本公开的一个实施例的半导体装置的布局图。
图4是根据本公开的实施例的半导体装置的导电结构的横截面视图。
图5是根据本公开的实施例的耦接在一起的半导体装置的示意图。
图6是示出了根据本公开的实施例的将半导体装置的端子耦接到接合焊盘的RDL结构的图。
图7是根据本公开的实施例的耦接在一起的半导体装置的接合焊盘的平面图。
具体实施方式
公开了用于耦接半导体装置的设备和方法。可以通过将半导体装置的一或多个端子耦接到两个导电接合焊盘的导电结构以菊链的方式耦接多个半导体装置的端子。端子可以是半导体装置的管芯焊盘。所述导电结构可以包含在重新分布层RDL结构中。在本公开的一些实施例中,所述RDL结构可以为“U”形。所述“U”形的每一端可以耦接到所述两个导电接合焊盘中的相应一个导电接合焊盘,并且所述半导体装置的所述端子可以耦接到所述RDL结构。半导体装置的所述导电接合焊盘可以通过导体(如接合线)耦接到其它半导体装置的导电接合焊盘。因此,所述半导体装置的所述端子可以通过所述RDL结构、导电接合焊盘和导体以菊链的方式耦接。
以下将参考附图详细解释本公开的各个实施例。以下详细描述参考了附图,所述附图通过说明的方式示出了本公开的具体方面和实施例。详细描述包含足够的细节以使本领域的技术人员能够实践本公开的实施例。在不脱离本公开的范围的情况下,可以利用其它实施例,并且可以进行结构、逻辑和电气改变。本文所公开的各个实施例不必相互排斥,因为一些公开的实施例可以与一或多个其它公开的实施例组合以形成新的实施例。
图1是根据本公开的实施例的半导体装置110的框图。例如,在一些实施例中,半导体装置110可以是集成到单个半导体芯片(例如,半导体管芯)中的存储器。示例存储器可以包含易失性存储器,如动态随机存取存储器(DRAM)和静态随机存取存储器(SRAM),以及非易失性存储器,如闪存、电阻式存储器和铁电存储器或以上的任何组合。
半导体装置10包含存储器单元阵列111。存储器单元阵列111包含多个库,每个库包含多条字线WL、多条位线BL和布置在所述多条字线WL和所述多条位线BL的交叉点处的多个存储器单元MC。对字线WL的选择由行解码器/驱动器112执行,并且对位线BL的选择由列解码器/驱动器113执行。读出放大器118耦接到对应位线BL并连接到本地I/O线对LIOT/B。本地IO线对LIOT/B通过用作开关的传输门TG 119连接到主IO线对MIOT/B。
半导体装置110包含多个端子。在本公开的一些实施例中,端子可以是管芯焊盘。所述多个端子包含命令和地址端子121、时钟端子123和123'、数据端子124、数据选通端子124'、电源端子125和126。数据端子124可以耦接到输入/输出电路117的输出缓冲器以进行读取操作。可替代地,数据端子124可以响应于在数据选通端子124'处提供的数据选通信号DQS而耦接到输入/输出电路117的用于存储器的写入存取的输入缓冲器。
命令和地址端子121供应有命令和地址信号CA,所述CA包含命令地址和存储器地址。通过命令/地址输入电路131将向命令和地址端子121提供的地址传输到地址解码器132。地址解码器132接收地址并向行解码器/驱动器112供应经解码的行地址并且向列解码器/驱动器113供应经解码的列地址。地址解码器132还接收组地址并且向行解码器/驱动器112和/或列解码器/驱动器113提供组地址信号。在自刷新模式中,自刷新电路138可以向行解码器/驱动器112提供行地址以进行自刷新操作。
通过命令和地址输入电路131将提供给命令和地址端子121的命令提供给命令解码器134。命令解码器134解码命令并向内部控制信号发生器137提供经解码的命令。响应于来自命令解码器134的经解码的命令,内部控制信号生成器137可以生成各种内部命令信号。例如,内部命令可以包含用于选择字线的行命令信号和用于选择位线的列命令信号,如读取命令或写入命令等。
因此,当发出激活命令并用激活命令及时供应行地址,并且用读取命令及时供应列地址时,从存储器单元阵列111中由行地址和列地址指定的存储器单元MC中读取读取数据。读出数据DQ通过读取/写入放大器115和输入/输出电路117从数据端子124中输出。类似地,当发出激活命令并用激活命令及时供应行地址,并且用写入命令及时供应列地址时,通过输入/输出电路117和读取/写入放大器115向存储器单元阵列111供应向数据端子124供应的写入数据DQ,并且将所述DQ写入由行地址和列地址指定的存储器单元MC中。
时钟端子123分别供应有时钟信号CK_t和CK_c,并且时钟端子123'供应有数据时钟信号WCK_t和WCK_c。时钟输入电路135接收时钟信号CK_t和CK_c以及WCK_t和WCK_c,并且生成内部时钟信号ICLK。内部时钟信号ICLK可以包含基于时钟信号CK_t和CK_c的内部时钟信号和/或基于数据时钟信号WCK_t和WCK_c的内部时钟信号。向内部时钟和定时发生器136供应内部时钟信号ICLK的一些或全部,所述内部时钟和定时发生器作为响应生成相控内部时钟信号LCLK。尽管不限于此,但是内部时钟和定时发生器136可以包含DLL电路。可以将相控内部时钟信号LCLK供应到输入和/或输出电路117并用于数据的输入和输出的定时。内部时钟和定时发生器136可以进一步生成各种其它内部时钟信号以进行各种存储器操作。
向电源端子125供应电源电位VDD和VSS。将这些电源电位VDD和VSS供应到电源电路139。电源电路139可以生成各种内部电位,例如,VPP、VOD、VARY、VPERI等。内部电位VPP主要用于行解码器/驱动器112中,内部电位VOD和VARY主要用于包含在存储器单元阵列111中的读出放大器118中,并且内部电位VPERI用于许多其它电路块中。向电源端子126供应电源电位VDDQ和VSSQ。将这些电源电位VDDQ和VSSQ供应到输入/输出电路117。电源电位VDDQ和VSSQ分别可以是与供应到电源端子125的电源电位VDD和VSS相同的电位。然而,电源电位VDDQ和VSSQ可以用于输入/输出电路117,使得由输入/输出电路117生成的电源噪声不会传播到其它电路块。
图2是示出了根据本公开的实施例的多管芯装置200的图。多管芯装置200可以包含半导体装置220的堆叠215。本公开的实施例不限于图2中所示的包含在堆叠215中的特定数量的半导体装置220。在本公开的一些实施例中,半导体装置220中的每个半导体装置包含图1的半导体装置110。
半导体装置220可以以交错的方式堆叠,从而为堆叠215提供“瓦片式堆叠(shingle-stack)”配置。半导体装置220可以彼此附接。在本公开的一些实施例中,半导体装置220通过粘合环氧树脂彼此附接。半导体装置220彼此偏移,以允许暴露半导体装置220的边缘区域。暴露的边缘区域可以包含导体225可以耦接到的接合焊盘。在本公开的一些实施例中,边缘区域的接合焊盘可以是导电焊盘。接合焊盘可以耦接到相应半导体装置220的端子。在本公开的一些实施例中,导体225是接合线。
堆叠215可以附接到衬底230。在本公开的一些实施例中,堆叠可以通过粘合环氧树脂附接到衬底230。衬底230可以包含用于沿衬底例如向半导体装置220或从半导体装置路由信号的导电信号线。其它电路也可以附接到衬底230并且也可以耦接到导电信号线。因此,附接到衬底230的电路可以例如通过衬底230的导电信号线和耦接到半导体装置的导电信号线和接合焊盘的导体而耦接到半导体装置220。图2中示出了附接到衬底230并耦接到堆叠215中的半导体装置的示例电路235。在本公开的一些实施例中,电路235可以是寄存器时钟驱动器(RCD)。在本公开的此类实施例中,RCD电路接收并缓冲向多管芯装置200提供的信号并且可以向半导体装置220提供信号。在不脱离本公开的范围的情况下,另外或可替代的电路可以包含在多管芯装置200中,和/或电路235也可以是其它电路。
图3是根据本公开的一个实施例的半导体装置310的布局图。在本公开的一些实施例中,半导体装置310包含图1的半导体装置110。在本公开的一些实施例中,半导体装置310包含在图2中所示的堆叠215中的半导体装置220中。
半导体装置310可以具有边缘350a、350b、350c和350d,这些边缘限定了半导体装置310的端部。边缘350b和350d可以沿第一方向357a延伸,并且边缘350a和350c可以沿可以垂直于第一方向357a的第二方向357b延伸。半导体装置310可以包括焊盘形成区351、外围电路区352和存储器单元阵列区353,所述存储器单元阵列区包含存储器单元、电路和信号线,例如读出放大器电路、地址解码器电路、数据输入/输出线等。外围电路区352可以包含用于执行半导体装置310的各种操作的各种电路和信号线。例如,外围电路区352可以包含命令和地址输入电路、地址和命令解码器、时钟电路、电源电路和输入/输出电路。外围电路区352还可以包含耦接到半导体装置的各种电路的端子(例如,如先前针对图1的半导体装置170描述的)。端子可以是例如半导体装置的管芯焊盘。
焊盘形成区351可以包含沿边缘350a安置的多个接合焊盘354。所述多个接合焊盘354可以耦接到半导体装置的端子(例如,管芯焊盘),并且表示半导体装置310的外部端子。例如,所述多个焊盘354可以包含数据端子、命令和地址端子、时钟端子和/或电源端子。
包含在存储器单元阵列区353中的电路和/或外围电路区352的电路可以耦接到包含在焊盘形成区351中的一或多个接合焊盘354。如先前所述,可以将半导体装置300的各种电路耦接到端子(例如,管芯焊盘)。导电结构可以用于将端子耦接到接合焊盘354中的一或多个接合焊盘。因此,耦接到端子的电路也耦接到接合焊盘354。导电结构可以从包含在存储器单元阵列区353和/或外围电路区352中的端子的位置延伸到焊盘形成区351。在本公开的一些实施例中,导电结构可以包含导电重新分布层(RDL)。
图4是根据本公开的实施例的半导体装置的导电结构的横截面视图。在本公开的一些实施例中,导电结构可以包含在图1的半导体装置110、图2的多管芯装置200的半导体装置220、图3的半导体装置310和/或根据本公开的实施例的任何半导体装置中。例如,在本公开的一些实施例中,导电结构可以包含在图1-3的半导体装置中的一或多个半导体装置中的导电重新分布层(RDL)中。
导电结构430可以将半导体装置的端子440耦接到接合焊盘420。在本公开的一些实施例中,端子440可以是管芯焊盘。端子440可以耦接到半导体装置的一或多个电路445。因此,接合焊盘420可以通过导电结构430和端子440耦接到电路445。在本公开的一些实施例中,电路445可以是例如包含在存储器单元阵列区(例如,图3的存储器单元阵列区352)中的电路。在本公开的一些实施例中,电路445可以是例如包含在外围电路区(例如,图3的外围电路区354)中的电路。电路445可以用于执行半导体装置的各种操作。在本公开的一些实施例中,电路445可以包含命令和地址输入电路、地址和命令解码器、时钟电路、电源电路和输入/输出电路以及其它电路。
半导体装置的接合焊盘420、导电结构430、端子440和电路445可以由半导体结构形成。半导体结构可以包含导电层、导电通孔、绝缘中间层等。端子440可以通过例如金属层和/或导电通孔耦接到电路445。导电结构430可以安置在一或多个绝缘中间层上。如先前所述,导电结构430可以进一步耦接到接合焊盘420。导电结构430从端子440延伸到接合焊盘420,使得接合焊盘420和电路端子440可以耦接在一起。因此,耦接到端子440的电路445可以通过接合焊盘420可从外部存取。接合焊盘420可以通过钝化层435中的开口425暴露。在本公开的一些实施例中,钝化层435可以是聚酰亚胺材料。
在本公开的一些实施例中,导电结构430可以耦接到半导体装置的端子440(例如,半导体装置的管芯焊盘),以提供用于耦接到处于不同位置的端子440的接合焊盘420。例如,端子440可以表示通常沿半导体装置的中心区域定位于外围电路区中的管芯焊盘,并且导电结构430可以将中心区域中的管芯焊盘耦接到沿半导体装置的边缘定位的接合焊盘420。沿边缘的接合焊盘420可以更方便地定位,并且提供到半导体装置的电路445的耦接,也就是说,通过导电结构430和端子440。
图5是根据本公开的实施例的耦接在一起的半导体装置的示意图。在本公开的一些实施例中,图5的半导体装置可以包含在多管芯装置的半导体装置(例如,图2的多管芯装置200的半导体装置220)中。在本公开的一些实施例中,图5的半导体装置中的每个半导体装置可以包含图1的半导体装置110,并且可以是存储器装置。
通过导电结构520(1)-520(20)将半导体装置510(1)-510(10)耦接在一起,所述导电结构可以包含在重新分布层(RDL)中。导电结构520在图5中表示为信号线。导电结构可以将半导体装置510的管芯焊盘515(例如,端子)耦接到相应半导体装置的接合焊盘525。半导体装置510中的每个半导体装置的接合焊盘525可以通过相应导体BW(1)-BW(9)耦接在一起。在本公开的一些实施例中,导体BW可以是接合线。
电路540可以耦接到半导体装置510。例如,电路540通过导电信号线545和导体BW(0),并且进一步通过接合焊盘525(1)和导电结构520(1)耦接到半导体装置510(1),所述导电结构耦接到半导体装置510(1)的管芯焊盘515。在本公开的一些实施例中,电路540可以是附接到包含导电信号线545的衬底的寄存器时钟驱动器(RCD),并且导体BW(0)可以是接合线。例如,在本公开的一些实施例中,电路540和导电信号线545可以表示包含在衬底230中的电路235和导电信号线,并且半导体装置510(1)可以表示图2的堆叠215中的半导体装置220。
在本公开的一些实施例中,可以将两个接合焊盘525和两个导电结构520耦接到半导体装置的一个管芯焊盘515。例如,将半导体装置510(1)的管芯焊盘515(1)分别通过导电结构520(1)和520(2)耦接到接合焊盘525(1)和525(2)。类似地,将半导体装置510(2)的管芯焊盘515(2)分别通过导电结构520(3)和520(4)耦接到接合焊盘525(3)和525(4);将半导体装置510(3)的管芯焊盘515(3)分别通过导电结构520(5)和520(6)耦接到接合焊盘525(5)和525(6);等等。
在本公开的一些实施例中,耦接到半导体装置510的管芯焊盘515的所述两个导电结构520可以表示“U”形RDL结构。U形RDL结构可以包含两个分支部分。所述分支部分中的每个分支部分具有耦接到另一个分支部分的第一端的第一端,并且所述分支部分中的每个分支部分具有与第一端相对的第二端。每个分支部分的第二端可以耦接到相应接合垫。分支部分的耦接在一起的第一端可以表示RDL结构的封闭端,并且所述两个分支部分的与第一端相对的第二端可以表示RDL结构的开口端。例如,参考图5,导电结构520(1)和520(2)表示具有耦接在一起的最靠近RDL结构的半导体装置510(1)的管芯焊盘515的分支部分。分支部分的第二端最靠近接合焊盘525(1)和525(2)。可以将半导体装置的管芯焊盘耦接到RDL结构的任何部分。在本公开的一些实施例中,可以将半导体装置的管芯焊盘耦接到RDL结构的封闭端。
半导体装置510可以通过RDL结构(例如,导电结构520)、接合焊盘525和导体BW以菊链的方式耦接在一起。例如,半导体装置510(1)-510(3)可以从接合焊盘525(1)开始以菊链的形式耦接在一起,如下:接合焊盘525(1)通过导电结构520(1)耦接到半导体装置510(1)的管芯焊盘515(1);管芯焊盘515(1)通过导电结构520(2)耦接到接合焊盘525(2);接合焊盘525(2)通过导体BW(1)耦接到接合焊盘525(3);接合焊盘525(3)通过导电结构520(3)耦接到半导体装置510(2)的管芯焊盘515(2);管芯焊盘515(2)通过导电结构520(4)耦接到接合焊盘525(4);接合焊盘525(4)通过导体BW(2)耦接到接合焊盘525(5);接合焊盘525(5)通过导电结构520(5)耦接到半导体装置510(3)的管芯焊盘515(3)。类似地,半导体装置510(4)-510(10)还以菊链的方式彼此耦接,并且耦接到半导体装置510(1)-510(3)。
与半导体装置510的并联耦接相比,菊链耦接可以向耦接到半导体装置510的电路(例如,电路540(例如,RCD))呈现较低负载。例如,利用堆叠的装置的并联耦接,呈现给电路的负载可以包含堆叠中的所有装置的负载。相比之下,利用堆叠的装置的菊链(例如,串联)耦接,呈现给电路的负载由半导体管芯链中的第一电路,随后每个后续电路的分布式负载产生。这种电气分布导致有效减少在比并联配置的频率更高的频率下观察到的负载。U形转弯RDL可以用于实施真正的菊链。在不使用U形转弯RDL的情况下,可以存在造成反射并降低信号完整性的长的电短截线(从接合焊盘到管芯焊盘)。然而,通过使用U形转弯RDL,RDL的“分支”不再形成短截线,而是没有平行段的串联路径。此类布置可能有益于信号完整性。因此,可能有利的是具有菊链耦接,如本公开的一或多个实施例提供的菊链耦接。
图5中示出了具有一个管芯焊盘515(例如,端子)的半导体装置510。然而,半导体装置510可以具有另外的管芯焊盘。另外的管芯焊盘还可以例如以菊链的方式通过导电结构耦接到接合焊盘,并且通过导体耦接到接合焊盘。在本公开的一些实施例中,每个半导体装置的管芯焊盘中的一些管芯焊盘不以菊链的方式与其它半导体装置耦接,而半导体装置的管芯焊盘中的其它管芯焊盘以菊链的方式耦接。例如,每个半导体装置的管芯焊盘中的一些管芯焊盘可以并联耦接到半导体装置中的另一个半导体装置的对应管芯焊盘,并且每个半导体装置的管芯焊盘中的一些管芯焊盘可以以菊链的形式耦接(例如,串联耦接)到半导体装置中的另一个半导体装置的对应管芯焊盘。在本公开的一些实施例中,可以以菊链的方式耦接半导体装置的数据端子和/或命令和地址端子。
图6是示出了根据本公开的实施例的将半导体装置的端子耦接到接合焊盘的RDL结构的图。在本公开的一些实施例中,RDL结构可以包含在先前参考图1-5描述的半导体装置中的任何半导体装置中。例如,RDL结构可以包含在图3的半导体装置310中,以将接合焊盘354耦接到包含在外围电路区中的端子。
接合焊盘610(1)-610(6)通过RDL结构630(1)-630(3)耦接到管芯焊盘620(1)-620(3)中的至少一个管芯焊盘。例如,将至少两个接合焊盘610通过相应RDL结构630耦接到至少一个管芯焊盘620。在图6的实例中,将接合焊盘610(1)和610(2)通过RDL结构630(1)耦接到管芯焊盘620(1);将接合焊盘610(3)和610(4)通过RDL结构630(2)耦接到管芯焊盘620(2);并且将接合焊盘610(5)和610(6)通过RDL结构630(3)耦接到管芯焊盘620(3)。在本公开的一些实施例中,RDL结构630可以具有将两个接合焊盘610耦接到一个管芯焊盘620的“U”形。
RDL结构630(1)可以包含从接合焊盘610(1)(例如,第一接合焊盘)延伸到管芯焊盘620(1)的第一部分632(1),并且可以进一步包含从接合焊盘610(2)(例如,第二接合焊盘)延伸到管芯焊盘620(1)的第二部分634(1)。部分632(1)可以包含导电结构,并且部分634(1)可以包含导电结构。在本公开的一些实施例中,导电结构中的每个导电结构可以包含在RDL中。第一部分632(1)和第二部分634(1)耦接到管芯焊盘620(1)。在本公开的一些实施例中,第一部分632(1)和第二部分634(1)可以通过耦接到第一部分632(1)和第二部分634(1)的第三部分耦接到管芯焊盘620(1)。例如,在图6中,第三部分636(1)耦接到第一部分632(1)和第二部分634(1),并且耦接到管芯焊盘620(1)。第三部分636(3)可以包含在RDL结构630(1)中。在本公开的一些实施例中,第一部分632(1)和第二部分634(1)耦接到没有第三部分的管芯焊盘620。例如,第一部分和第二部分可以被成形为在第一接合焊盘与第二接合焊盘之间提供到没有第三部分的同一管芯焊盘620的耦接。
RDL结构630(2)和630(3)可以包含如先前针对RDL结构630(1)所述的相应的第一部分和第二部分,所述第一部分和第二部分耦接到相应的管芯焊盘620(2)和620(3)。同样地,在本公开的一些实施例中,RDL结构630(2)和630(3)可以包含如先前针对RDL结构630(1)所述的相应的第三部分。
RDL结构630可以由一或多个导电层的导电材料形成。例如,在本公开的一些实施例中,RDL结构630的第一部分和第二部分可以由同一导电层形成。第三部分可以由同一导电层形成。在本公开的一些实施例中,RDL层的部分中的一或多个部分可以由不同于其它部分的导电层形成。所述部分本身可以由一或多个导电层形成。导电结构可以由位于接合焊盘610下方和管芯焊盘620上方的导电层形成。
已经通过实例提供了RDL结构630,并且本公开的实施例并不限于图6的特定实例。
图7是根据本公开的实施例的耦接在一起的半导体装置的接合焊盘的平面图。在本公开的一些实施例中,半导体装置可以包含在多管芯装置(例如,图2的多管芯装置200)中。
接合焊盘731-736可以包含在相应半导体装置710(1)-710(4)的焊盘形成区中。接合焊盘对可以耦接到半导体装置的相应管芯焊盘。例如,参考半导体装置710(1)的接合焊盘731(1)-736(1),可以将接合焊盘对721(1)的接合焊盘731(1)和732(1)耦接到半导体装置710(1)的同一管芯焊盘。类似地,均可以将接合焊盘对722(1)的接合焊盘733(1)和734(1)耦接到半导体装置710(1)的另一个管芯焊盘,并且均可以将接合焊盘对723(1)的接合焊盘735(1)和736(1)耦接到半导体装置710(1)的又另一个管芯焊盘。也可以将其它半导体装置710(2)-710(4)的接合焊盘对耦接到相应的公共管芯焊盘。
可以通过从相应的接合焊盘延伸到同一管芯焊盘的导电结构耦接接合焊盘对。例如,接合焊盘731(1)和732(1)可以通过从相应的接合焊盘731(1)和732(1)延伸到同一管芯焊盘的导电结构耦接。类似地,可以通过从相应的接合焊盘733(1)和734(1)延伸到同一管芯焊盘的导电结构耦接接合焊盘733(1)和734(1)。导电结构可以包含在RDL结构中。在本公开的一些实施例中,U形RDL结构可以用于将接合焊盘耦接到同一管芯焊盘。例如,在本公开的一些实施例中,可以使用图5的导电结构和RDL结构。在本公开的一些实施例中,可以使用图6的导电结构和RDL结构。
可以通过耦接到相应管芯焊盘的所述接合焊盘对以菊链的方式将半导体装置710(1)-710(4)的管芯焊盘耦接在一起。例如,假设管芯焊盘“A”是半导体装置710(1)的耦接到所述接合焊盘对721(1)的管芯焊盘;管芯焊盘“B”是半导体装置710(2)的耦接到接合焊盘对721(2)的管芯焊盘;管芯焊盘“C”是半导体装置710(3)的耦接到接合焊盘对721(3)的管芯焊盘;并且管芯焊盘“D”是半导体装置710(4)的耦接到接合焊盘对721(4)的管芯焊盘。管芯焊盘A可以通过借助于导体BW1(1)将接合焊盘732(1)耦接到接合焊盘731(2)而耦接到管芯焊盘B;管芯焊盘B可以通过借助于导体BW1(2)将接合焊盘732(2)耦接到接合焊盘731(3)而耦接到管芯焊盘C;并且管芯焊盘C可以通过借助于导体BW1(3)将接合焊盘732(3)耦接到接合焊盘731(4)而耦接到管芯焊盘D。因此,管芯焊盘A、B、C和D可以以菊链的方式耦接。
管芯焊盘A、B、C和D的菊链可以通过导体BW1(0)进一步耦接到电路(例如,附接到衬底的RCD)。例如,焊盘731(1)可以通过BW1(0)耦接到导电信号线,并且导电信号线可以进而耦接到电路。
管芯焊盘A、B、C和D的菊链还可以通过导体BW1(4)进一步耦接到其它半导体装置(例如,多管芯堆叠中的另外的半导体装置)的管芯焊盘。例如,接合焊盘732(4)可以通过BW1(4)耦接到另一个半导体装置的接合焊盘,并且所述接合焊盘可以进而耦接到其它半导体装置的管芯焊盘。
半导体装置710(1)-710(4)的其它管芯焊盘可以以类似的菊链方式耦接在一起。例如,耦接到所述接合焊盘对722(1)、722(2)、722(3)和722(4)的管芯焊盘可以以菊链的方式耦接如下:接合焊盘734(1)通过导体BW2(1)耦接到接合焊盘733(2);接合焊盘734(2)通过导体BW2(2)耦接到接合焊盘733(3);接合焊盘734(3)通过导体BW2(3)耦接到接合焊盘733(4)。类似地,耦接到所述接合焊盘对723(1)、723(2)、723(3)和723(4)的管芯焊盘可以以菊链的方式耦接如下:接合焊盘736(1)通过导体BW3(1)耦接到接合焊盘735(2);接合焊盘736(2)通过导体BW3(2)耦接到接合焊盘735(3);接合焊盘736(3)通过导体BW3(3)耦接到接合焊盘735(4)。分别耦接到接合焊盘733(1)和734(4)的导体BW2(0)和BW2(4)可以用于将菊链式管芯焊盘耦接到电路(例如,RCD)和其它半导体装置(例如,在多管芯堆叠中)。同样,分别耦接到接合焊盘735(1)和736(4)的导体BW3(0)和BW3(4)可以用于将菊链式管芯焊盘耦接到电路(例如,RCD)和其它半导体装置(例如,在多管芯堆叠中)。
在图7的实例中,示出了来自半导体装置710(1)-710(4)中的每个半导体装置的六个接合焊盘731-736。所述六个接合焊盘731-736是通过实例提供的,并且在不脱离本公开的范围的情况下,半导体装置710(1)-710(4)中的每个半导体装置可以包含更多或更少数量的接合焊盘。另外,图7中示出了四个半导体装置710(1)-710(4)。然而,在不脱离本公开的范围的情况下,更多或更少数量的半导体装置可以耦接在一起。
已经描述了一些细节以提供对本公开的实例的充分理解。然而,对于本领域的技术人员而言将清楚的是,可以在没有这些特定细节的情况下实践本公开的实例。此外,本文描述的本公开的特定实例不应被解释为将本公开的范围限制于这些特定实例。在其它情况下,未详细示出众所周知的电路、控制信号、定时协议和软件操作,以避免不必要地模糊本公开。另外,如“耦接”和“耦接的”等术语意指两个组件可以直接地或间接地电耦接。间接耦接可以暗指两个组件通过一或多个中间组件耦接。
根据上文,应理解的是,虽然本文中出于说明的目的已经描述了本公开的具体实施例,但可以在不偏离本公开的精神和范围的情况下进行各种修改。因此,本公开的范围不应受本文所描述的任何具体实施例的限制。
Claims (25)
1.一种设备,其包括:
多个半导体装置,所述多个半导体装置包含第一半导体装置、第二半导体装置和第三半导体装置,所述多个半导体装置中的每个半导体装置包含耦接到相应半导体装置的至少一个电路的管芯焊盘,并且进一步包含耦接到所述管芯焊盘并进一步耦接到第一接合焊盘和第二接合焊盘的重新分布层结构,其中所述第一半导体装置的所述第二接合焊盘耦接到所述第二半导体装置的所述第一接合焊盘,并且所述第二半导体装置的所述第二接合焊盘耦接到所述第三半导体装置的所述第一接合焊盘。
2.根据权利要求1所述的设备,其中所述多个半导体装置包含在半导体装置的堆叠中。
3.根据权利要求2所述的设备,其中所述多个半导体装置以交错的方式堆叠,并且暴露所述多个半导体装置中的半导体装置中的每个半导体装置的边缘区域,其中相应第一接合焊盘和第二接合焊盘定位于所述多个半导体装置的所述边缘区域处。
4.根据权利要求1所述的设备,其中所述第一半导体装置的所述第二接合焊盘通过接合线耦接到所述第二半导体装置的所述第一接合焊盘,并且所述第二半导体装置的所述第二接合焊盘通过另一条接合线耦接到所述第三半导体装置的所述第一接合焊盘。
5.根据权利要求1所述的设备,其中所述多个半导体装置中的每个半导体装置的所述重新分布层结构呈U形。
6.根据权利要求1所述的设备,其中所述多个半导体装置中的每个半导体装置的所述重新分布层结构包含在所述管芯焊盘与所述第一接合焊盘之间延伸的第一部分并且进一步包含在所述管芯焊盘与所述第二接合焊盘之间延伸的第二部分。
7.根据权利要求6所述的设备,其中所述多个半导体装置中的每个半导体装置的所述重新分布层结构进一步包含耦接到所述第一部分和所述第二部分并进一步耦接到所述管芯焊盘的第三部分。
8.根据权利要求1所述的设备,其进一步包括:
外部电路,所述外部电路耦接到所述第一半导体装置的所述第一接合焊盘;以及
衬底,所述衬底包含导电信号线,其中所述多个半导体装置和所述外部电路附接到所述衬底,并且所述外部电路通过所述导电信号线耦接到所述第一半导体装置的所述第一接合焊盘。
9.根据权利要求1所述的设备,其中所述多个半导体装置中的每个半导体装置的相应管芯焊盘包含在沿相应半导体装置的中心区域定位的外围电路区中。
10.根据权利要求1所述的设备,其中所述多个半导体装置中的每个半导体装置的相应管芯焊盘通过所述接合焊盘和所述重新分布层结构以菊链的形式耦接在一起。
11.一种多管芯装置,其包括:
衬底,所述衬底包含导电信号线;
半导体装置的堆叠,所述堆叠附接到所述衬底,所述堆叠中的所述半导体装置中的每个半导体装置包含端子和耦接到所述端子的重新分布层结构,并且其中所述堆叠中的所述半导体装置的所述端子通过所述重新分布层结构以菊链的形式耦接在一起;以及
电路,所述电路附接到所述衬底并且通过所述导电信号线耦接到半导体装置的所述堆叠中的第一半导体装置。
12.根据权利要求11所述的多管芯装置,其中所述半导体装置中的每个半导体装置进一步包含第一接合焊盘和第二接合焊盘,其中所述第一接合焊盘耦接到所述重新分布层结构的第一部分,并且所述第二接合焊盘耦接到所述重新分布层结构的第二部分。
13.根据权利要求12所述的多管芯装置,其中每个半导体装置的所述第一接合焊盘和所述第二接合焊盘定位于边缘区域处,并且所述端子包含在沿相应半导体装置的中心区域定位的外围电路区中。
14.根据权利要求12所述的多管芯装置,其中所述堆叠中的半导体装置的所述第一接合焊盘和所述第二接合焊盘中的一个通过接合线耦接到所述堆叠中的另一个半导体装置的所述第一接合焊盘和所述第二接合焊盘中的一个。
15.根据权利要求12所述的多管芯装置,其中所述第一部分包含由不同于所述第一接合焊盘和所述端子的导电层形成的第一导电结构,并且其中所述第二部分包含由同一导电层形成的第二导电结构。
16.根据权利要求11所述的多管芯装置,其中附接到所述衬底的所述电路包括寄存器时钟驱动器RCD电路。
17.根据权利要求11所述的多管芯装置,其中所述端子包括数据端子或命令地址端子。
18.根据权利要求11所述的多管芯装置,其中所述重新分布层结构包括U形重新分布层结构。
19.一种设备,其包括:
存储器阵列,所述存储器阵列被配置成存储数据;
端子;
输入/输出电路,所述输入/输出电路被配置成从所述存储器阵列接收数据并提供读取数据,并且接收要存储在所述存储器阵列中的写入数据;
命令和地址输入电路,所述命令和地址输入电路被配置成接收命令和地址信号;
第一接合焊盘和第二接合焊盘;以及
U形导电结构,所述U形导电结构耦接到所述端子并且包含在所述端子与所述第一接合焊盘之间延伸并耦接到所述端子和所述第一接合焊盘的第一部分,并且进一步包含在所述端子与所述第二接合焊盘之间延伸并耦接到所述端子和所述第二接合焊盘的第二部分。
20.根据权利要求19所述的设备,其中所述输入/输出电路耦接到所述端子并且被配置成向所述端子提供所述读取数据并且被配置成从所述端子接收所述写入数据。
21.根据权利要求19所述的设备,其中所述命令和地址输入电路耦接到所述端子并且被配置成从所述端子接收命令和地址信号。
22.根据权利要求19所述的设备,其中所述U形导电结构进一步包含耦接到所述第一部分和所述第二部分并进一步耦接到所述端子的第三部分。
23.根据权利要求19所述的设备,其中所述端子包括包含在外围电路区中的管芯焊盘。
24.根据权利要求19所述的设备,其中所述第一接合焊盘和所述第二接合焊盘定位于边缘处,并且所述端子定位于沿着安置在所述存储器阵列的存储器单元阵列区之间的中心区域的区中。
25.一种方法,其包括:
将第一半导体装置的接合焊盘耦接到第一U形导电结构;
将第二半导体装置的接合焊盘耦接到第二U形导电结构;
将第三半导体装置的接合焊盘耦接到第三U形导电结构;
将所述第一U形导电结构的第二部分耦接到所述第二U形导电结构的第一部分;以及
将所述第二U形导电结构的第二部分耦接到所述第三U形导电结构的第一部分,其中将所述第一U形导电结构的第一部分耦接到电路,并且其中将所述第三U形导电结构的第二部分耦接到第四半导体装置。
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