CN113359582A - High-resolution processing system and method for sampled data based on DSP direct averaging - Google Patents
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Abstract
The invention discloses a high-resolution processing system and a high-resolution processing method for sampled data based on DSP direct averaging, wherein the system comprises an analog conditioning channel, an ADC device, an FPGA and a control center; the analog conditioning channel, the ADC device and the FPGA are sequentially in communication connection, and the FPGA is also in communication connection with the control center; the invention adopts a digital processing mode to carry out arithmetic mean on adjacent N sampling points of a waveform acquired by an analog conditioning channel, thereby effectively reducing random noise components in signals and further improving the effective vertical resolution digit of an acquisition system.
Description
Technical Field
The invention belongs to the technical field of signal sampling processing, and particularly relates to a high-resolution processing system and method for sampled data based on DSP direct averaging.
Background
Resolution is an important indicator of a test metrology system, particularly for accurate measurement of signal details. The resolution of the data acquisition system is related to the vertical resolution of an ADC device used by the system and noise in an acquisition channel of the system, and the quantization noise means that when the ADC quantizes a signal, the signal is continuously changed from amplitude to discrete amplitude, so that the introduced quantization error cannot be avoided. The rounding quantization is equivalent to introducing a digital frequency domain with probability density distribution of [ -division value/2, division value/2 ] to uniformly distribute white Gaussian noise on [ -pi, pi ]. In the signal acquisition process, the power of noise is only related to the quantization resolution of the ADC, and the power of the signal and the noise in the system is unchanged no matter how the sampling rate is changed. However, if the sampling rate of the system is increased, the digital bandwidth of the signal is reduced, and if the out-of-band noise is filtered, the signal-to-noise ratio of the acquisition system can be improved. The signal-to-noise ratio (SNR) is the ratio of the signal to the noise power falling within the bandwidth and can be expressed in the acquisition system by the following equation:
SNR＝6.02N+1.76+10lg(fs/2fin) (1)
wherein f issRepresenting the system sampling frequency, fmRepresenting the system input signal frequency and N being the acquisition system resolution. When the system with higher sampling rate is in the over-sampling state, the system signal-to-noise ratio calculation is converted into:
when the system is over-sampled, the system signal-to-noise ratio is improved when the system sampling rate is improved, and the acquisition equivalent resolution can be improved according to the formula (2). The digital bandwidth of the signal becomes lower as the sampling rate increases, and noise falling out of band can be removed by low pass filtering to improve the system signal-to-noise ratio. Wherein, low-pass arithmetic mean filtering is adopted to filter out the out-of-band noise.
When the high-speed data acquisition system sends data into the digital rear end after finishing data acquisition, the high-speed data acquisition system has larger data volume, and the ADC sampling rate is higher, so the data needs to be subjected to snapshot processing, and the conventional snapshot mode is to directly lose redundant data according to the required data volume so as to meet the data required by upper computer software. However, the resolution and signal-to-noise ratio of the acquisition system cannot be improved by adopting the direct point-missing mode.
Disclosure of Invention
In order to overcome the defects in the prior art, the sampling data high-resolution processing system and method based on DSP direct averaging provided by the invention improve the resolution of the acquisition system.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: the high-resolution processing system of the sampled data based on the DSP direct averaging comprises an analog conditioning channel, an ADC device, an FPGA and a control center; the analog conditioning channel, the ADC device and the FPGA are sequentially in communication connection, and the FPGA is also in communication connection with the control center;
the analog conditioning channel is used for transmitting an analog signal to the ADC device; the ADC device is used for sampling an analog signal and transmitting the sampled digital signal to the FPGA; the FPGA is used for enhancing the resolution of the sampled signal; the control center is used for sending a high-resolution mode enabling signal for starting the high-resolution sampling mode.
Further: the FPGA comprises 4 levels of addition trees, a shift averager, an enabling counter, an accumulator, a divider, a data retainer and an FIFO;
the 4-stage addition tree, the shift averager, the accumulator, the divider, the data retainer and the FIFO are sequentially in communication connection, and the enabling counter is respectively connected with the accumulator and the divider.
The beneficial effects of the above further scheme are: the FPGA can start a high-resolution sampling mode according to the requirement of a control center, and carries out processing such as average filtering, parallel-serial conversion and the like on the sampled data, so that the resolution of the whole sampling system is improved.
Further: and a self-decreasing counter is arranged in the accumulator.
The beneficial effects of the above further scheme are: the self-decreasing counter can control the accumulator to accumulate serial average data and send the serial average data to the divider by receiving an initial accumulation count value sent by the enabling counter.
Further: a high-resolution processing method of high-speed sampling data based on DSP direct averaging comprises the following steps:
s1, collecting analog signals transmitted by the analog conditioning channel through an ADC (analog to digital converter) device to obtain sampling data, and transmitting the sampling data to a 4-level addition tree;
s2, converting the sampling data into serial average data with the same resolution through a 4-level addition tree, and transmitting the serial average data to an accumulator;
s3, when the high-resolution sampling mode is started, transmitting a high-resolution mode enabling signal to an accumulator through an enabling counter, and transmitting an initial value of accumulated count to the accumulator and a divider respectively;
s4, based on the serial average data, the high-resolution mode enabling signal and the initial value of the accumulation count received by the accumulator, transmitting a single accumulation result obtained by accumulating the serial average data and the generated delay ready signal to the divider together, and clearing the accumulator after the transmission is finished;
s5, generating a single high-resolution mode calculation value and an enabling signal based on the initial accumulation count value, the single accumulation result and the delay ready signal received by the divider, and transmitting the single high-resolution mode calculation value and the enabling signal to a data holder;
s6, generating a new single high resolution mode calculation value based on the single high resolution mode calculation value and the enable signal received by the data holder, adding it to the parallel data, and holding the parallel data output;
s7, repeating the steps S2-S6 according to the number of parallel paths required by the control center, and writing the parallel data into FIFO when the number of the parallel paths of the parallel data reaches the preset number;
and S8, reading the data in the FIFO through the control center, and finishing the high-resolution processing of the sampled data.
Further: the step S2 specifically includes:
using T-log by 4-level addition tree2And M sums the sampling data of the parallel M paths to obtain summed data, then shifts the summed data left by T bits to obtain serial average data with the same resolution as the sampling data, and transmits the serial average data to an accumulator.
The beneficial effects of the above further scheme are: the 4-level addition tree can realize the addition operation of a large amount of data and can optimize the data processing of the system.
Further: the step S4 includes the following sub-steps:
s41, accumulating the input serial average data based on the high resolution mode enabling signal received by the accumulator to generate a single accumulation result; meanwhile, based on the initial value of the accumulated count received by the self-decreasing counter, the initial value of the accumulated count is self-decreased, and when the self-decreasing counter is decreased to 0, a ready signal is generated;
s42, delaying the ready signal to align with the single accumulation result to generate a delayed ready signal;
and S43, transmitting the delay ready signal and the single accumulation result to the divider through the accumulator, and clearing the accumulator after the transmission is finished.
The beneficial effects of the above further scheme are: the accumulator controls the starting work through a high-resolution mode enabling signal; the self-decreasing counter controls the accumulator to output a single accumulation result according to the initial accumulation value, and realizes the input and output of control data.
Further: the step S5 includes the following sub-steps:
s51, starting the divider to work based on the delay ready signal received by the divider;
s52, taking the received single accumulation result as a dividend, obtaining the divisor by shifting the accumulation counting initial value to the left by T bits, completing the calculation of the division by a divider to obtain a single high resolution mode calculation value, and generating an enabling signal;
s53, transmitting the single high resolution mode calculation value to the data keeper together with the enable signal.
The beneficial effects of the above further scheme are: the divider can be controlled to start to work by a delay ready signal generated by the accumulator, so that the normal work of the system is ensured, and the generation of errors is reduced.
Further: the step S6 specifically includes:
s61, truncating the single high resolution mode calculation value through a data retainer, reserving a bit width which is the same as the resolution of the ADC device, removing a decimal part, and generating a new single high resolution mode calculation value;
s62, adding the new single high resolution mode calculation value to the parallel data based on the enable signal, and keeping the parallel data output.
The beneficial effects of the above further scheme are: the data keeper can convert serial data into parallel data, ultimately enabling high resolution processing of sampled data.
The invention has the beneficial effects that:
(1) the digital processing mode makes the arithmetic mean of the adjacent N sampling points of a waveform acquired by the ADC device, effectively reduces the random noise component in the sampling data, and thus improves the effective vertical resolution digit of the acquisition system.
(2) The 4-level addition tree can maintain the generated serial data at the same resolution as the sampled data and realize the average processing of the sampled data.
(3) The control center can start a high-resolution sampling mode through the FPGA, average filtering is carried out on the sampled data, and the sampled data are written into the FIFO in parallel, so that the resolution of the whole sampling system is improved.
Drawings
FIG. 1 is a block diagram of the system of the present invention.
Fig. 2 is a diagram of a resolution enhancement filter logic implementation.
FIG. 3 is a flow chart of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
As shown in fig. 1, in one embodiment of the present invention, a DSP-direct averaging-based sampled data high resolution processing system includes an analog conditioning channel, an ADC device, an FPGA, and a control center; the analog conditioning channel, the ADC device and the FPGA are sequentially in communication connection, and the FPGA is also in communication connection with the control center;
the analog conditioning channel is used for transmitting an analog signal to the ADC device; the ADC device is used for sampling an analog signal and transmitting the sampled digital signal to the FPGA; the FPGA is used for enhancing the resolution of the sampled signal; the control center is used for sending a high-resolution mode enabling signal for starting the high-resolution sampling mode.
The FPGA comprises 4 levels of addition trees, a shift averager, an enabling counter, an accumulator, a divider, a data retainer and an FIFO;
the 4-stage addition tree, the shift averager, the accumulator, the divider, the data retainer and the FIFO are sequentially in communication connection, and the enabling counter is respectively connected with the accumulator and the divider.
The 4-level addition tree is used for converting parallel sampling data into serial average data; the shift averager is used for shifting the serial average data to the right by T bits, where T is 3 in this embodiment; the enabling counter is used for receiving the extraction multiple value and sending a high-resolution mode enabling signal and an accumulation counting initial value according to the extraction multiple value; the accumulator is used for accumulating the input serial average data; the divider is used for calculating the single accumulation result for quotient calculation; a data keeper for holding parallel data outputs; the FIFO is used for writing parallel data and can be used for the control center to read.
The accumulator is provided with a self-decreasing counter, and the self-decreasing counter can control the accumulator to accumulate serial average data and send the serial average data to the divider by receiving an accumulation count initial value sent by the enabling counter.
The invention is realized based on a single-channel 12-bit resolution 5Gsps sampling rate data acquisition system. The analog signal is sampled by the front-end ADC device and input to the FPGA, and is input to the high-resolution module through internal processing of the FPGA to form 16 paths of 312.5MHz data streams.
The working process of the system in the embodiment is as follows: as shown in fig. 2, the enhanced resolution mode is turned on, and the control center sends the decimation factor value to the FPGA according to the frequency of the analog signal acquired by the ADC; an enabling counter in the FPGA reduces the extraction multiple value by X times according to the received extraction multiple value as an initial accumulation count value, wherein X is the number of paths to be paralleled by a 4-level addition tree, and X is 16 in the embodiment; the initial value of the accumulated count is sent to an accumulator and a divider, the enabling counter also sends a high-resolution mode enabling signal to the accumulator, and the accumulator is controlled to start accumulation; when the accumulator receives a high-resolution mode enabling signal, accumulating the serial average data to obtain a single accumulation result, starting self-reduction from an accumulation counting initial value by the self-reduction counter, when the self-reduction counter is reduced to 0, disabling the high-resolution mode enabling signal of the accumulator, generating a ready signal, delaying to obtain a delayed ready signal, and then sending the delayed ready signal and the single accumulation result to the divider; when the divider receives the delay ready signal, the divider is started, the divider takes an input single accumulation result as a dividend, and shifts an accumulation counting initial value to the left by T bits as a divisor, wherein T is 3 in the embodiment, the calculated quotient is taken as a single high resolution mode calculation value, an enable signal is generated, and the enable signal and the single high resolution mode calculation value are respectively sent to the data retainer; the data retainer intercepts the single high-resolution mode calculation value to reserve the bit width which is the same as the ADC resolution, removes the decimal part to obtain a new single high-resolution mode calculation value, adds the new single high-resolution mode calculation value into parallel data, outputs and retains the parallel data by using an enabling signal output by the divider, continuously sends the extraction multiple value according to the number of parallel paths required by the control center until the parallel data meets the requirement, writes the parallel data into the FIFO, and the control center can read the parallel data in the FIFO for display to finish the high-resolution processing of the sampling data.
In an embodiment of the present invention, as shown in fig. 3, a method for high resolution processing of sampled data based on DSP direct averaging includes the following steps:
s1, collecting analog signals transmitted by the analog conditioning channel through an ADC (analog to digital converter) device to obtain sampling data, and transmitting the sampling data to a 4-level addition tree;
s2, converting the sampling data into serial average data with the same resolution through a 4-level addition tree, and transmitting the serial average data to an accumulator;
s3, when the high-resolution sampling mode is started, transmitting a high-resolution mode enabling signal to an accumulator through an enabling counter, and transmitting an initial value of accumulated count to the accumulator and a divider respectively;
s4, based on the serial average data, the high-resolution mode enabling signal and the initial value of the accumulation count received by the accumulator, transmitting a single accumulation result obtained by accumulating the serial average data and the generated delay ready signal to the divider together, and clearing the accumulator after the transmission is finished;
s5, generating a single high-resolution mode calculation value and an enabling signal based on the initial accumulation count value, the single accumulation result and the delay ready signal received by the divider, and transmitting the single high-resolution mode calculation value and the enabling signal to a data holder;
s6, generating a new single high resolution mode calculation value based on the single high resolution mode calculation value and the enable signal received by the data holder, adding it to the parallel data, and holding the parallel data output;
s7, repeating the steps S2-S6 according to the number of parallel paths required by the control center, and writing the parallel data into FIFO when the number of the parallel paths of the parallel data reaches the preset number;
and S8, reading the parallel data in the FIFO through the control center, and finishing the high-resolution processing of the sampled data.
The step S2 specifically includes:
using T-log by 4-level addition tree2And M sums the sampling data of the parallel M paths to obtain summed data, then shifts the summed data left by T bits to obtain serial average data with the same resolution as the sampling data, and transmits the serial average data to an accumulator. The 4-level addition tree can be realized to be largeThe addition operation of the volume data can optimize the data processing of the system.
The step S4 includes the following sub-steps:
s41, accumulating the input serial average data based on the high resolution mode enabling signal received by the accumulator to generate a single accumulation result; meanwhile, based on the initial value of the accumulated count received by the self-decreasing counter, the initial value of the accumulated count is self-decreased, and when the self-decreasing counter is decreased to 0, a ready signal is generated;
s42, delaying the ready signal to align with the single accumulation result to generate a delayed ready signal;
and S43, transmitting the delay ready signal and the single accumulation result to the divider through the accumulator, and clearing the accumulator after the transmission is finished.
The accumulator controls the starting work through a high-resolution mode enabling signal; the self-decreasing counter controls the accumulator to output a single accumulation result according to the initial accumulation value, and realizes the input and output of control data.
The step S5 includes the following sub-steps:
s51, starting the divider to work based on the delay ready signal received by the divider;
s52, taking the received single accumulation result as a dividend, obtaining the divisor by shifting the accumulation counting initial value to the left by T bits, completing the calculation of the division by a divider to obtain a single high resolution mode calculation value, and generating an enabling signal;
s53, transmitting the single high resolution mode calculation value to the data keeper together with the enable signal.
The divider can be controlled to start to work by a delay ready signal generated by the accumulator, so that the normal work of the system is ensured, and the generation of errors is reduced.
The step S6 specifically includes:
s61, truncating the single high resolution mode calculation value through a data retainer, reserving a bit width which is the same as the resolution of the ADC device, removing a decimal part, and generating a new single high resolution mode calculation value; removing a decimal part to generate a new single high-resolution mode calculation value;
s62, adding the new single high resolution mode calculation value to the parallel data based on the enable signal, and keeping the parallel data output.
The data keeper can convert serial data into parallel data, ultimately enabling high resolution processing of sampled data.
The invention has the beneficial effects that: the digital processing mode makes the arithmetic mean of the adjacent N sampling points of a waveform acquired by the analog conditioning channel, effectively reduces the random noise component in the sampling data, and thus improves the effective vertical resolution digit of the acquisition system. The 4-level addition tree can maintain the generated serial data at the same resolution as the sampled data and realize the average processing of the sampled data.
The control center can start a high-resolution sampling mode through the FPGA, average filtering is carried out on the sampled data, and the sampled data are written into the FIFO in parallel, so that the resolution of the whole sampling system is improved.
In the description of the present invention, it is to be understood that the terms "center", "thickness", "upper", "lower", "horizontal", "top", "bottom", "inner", "outer", "radial", and the like, indicate orientations and positional relationships based on the orientations and positional relationships shown in the drawings, and are used merely for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or an implicit indication of the number of technical features. Thus, features defined as "first", "second", "third" may explicitly or implicitly include one or more of the features.
Claims (8)
1. The high-resolution processing system of the sampled data based on the DSP direct averaging is characterized by comprising an analog conditioning channel, an ADC device, an FPGA and a control center; the analog conditioning channel, the ADC device and the FPGA are sequentially in communication connection, and the FPGA is also in communication connection with the control center;
the analog conditioning channel is used for transmitting an analog signal to the ADC device; the ADC device is used for sampling an analog signal and transmitting the sampled digital signal to the FPGA; the FPGA is used for enhancing the resolution of the sampled signal; the control center is used for sending a high-resolution mode enabling signal for starting the high-resolution sampling mode.
2. The DSP direct averaging-based sampled data high resolution processing system of claim 1 wherein the FPGA comprises 4 stages of an addition tree, a shift averager, an enable counter, an accumulator, a divider, a data holder, and a FIFO;
the 4-stage addition tree, the shift averager, the accumulator, the divider, the data retainer and the FIFO are sequentially in communication connection, and the enabling counter is respectively connected with the accumulator and the divider.
3. The DSP direct averaging-based sampled data high resolution processing system of claim 2 wherein a self-decreasing counter is provided in the accumulator.
4. The high-resolution processing method of the sampling data based on the DSP direct averaging is characterized by comprising the following steps:
s1, collecting analog signals transmitted by the analog conditioning channel through an ADC (analog to digital converter) device to obtain sampling data, and transmitting the sampling data to a 4-level addition tree;
s2, converting the sampling data into serial average data with the same resolution through a 4-level addition tree, and transmitting the serial average data to an accumulator;
s3, when the high-resolution sampling mode is started, transmitting a high-resolution mode enabling signal to an accumulator through an enabling counter, and transmitting an initial value of accumulated count to the accumulator and a divider respectively;
s4, based on the serial average data, the high-resolution mode enabling signal and the initial value of the accumulation count received by the accumulator, transmitting a single accumulation result obtained by accumulating the serial average data and the generated delay ready signal to the divider together, and clearing the accumulator after the transmission is finished;
s5, generating a single high-resolution mode calculation value and an enabling signal based on the initial accumulation count value, the single accumulation result and the delay ready signal received by the divider, and transmitting the single high-resolution mode calculation value and the enabling signal to a data holder;
s6, generating a new single high resolution mode calculation value based on the single high resolution mode calculation value and the enable signal received by the data holder, adding it to the parallel data, and holding the parallel data output;
s7, repeating the steps S2-S6 according to the number of parallel paths required by the control center, and writing the parallel data into FIFO when the number of the parallel paths of the parallel data reaches the preset number;
and S8, reading the parallel data in the FIFO through the control center, and finishing the high-resolution processing of the sampled data.
5. The DSP-direct-averaging-based sample data high-resolution processing method according to claim 4, wherein the step S2 specifically comprises:
using T-log by 4-level addition tree2And M sums the sampling data of the parallel M paths to obtain summed data, then shifts the summed data left by T bits to obtain serial average data with the same resolution as the sampling data, and transmits the serial average data to an accumulator.
6. The DSP direct averaging-based high resolution processing method for sampled data according to claim 4, wherein the step S4 comprises the following substeps:
s41, accumulating the input serial average data based on the high resolution mode enabling signal received by the accumulator to generate a single accumulation result; meanwhile, based on the initial value of the accumulated count received by the self-decreasing counter, the initial value of the accumulated count is self-decreased, and when the self-decreasing counter is decreased to 0, a ready signal is generated;
s42, delaying the ready signal to align with the single accumulation result to generate a delayed ready signal;
and S43, transmitting the delay ready signal and the single accumulation result to the divider through the accumulator, and clearing the accumulator after the transmission is finished.
7. The DSP direct averaging-based high resolution processing method for sampled data according to claim 4, wherein the step S5 comprises the following substeps:
s51, starting the divider to work based on the delay ready signal received by the divider;
s52, taking the received single accumulation result as a dividend, obtaining the divisor by shifting the accumulation counting initial value to the left by T bits, completing the calculation of the division by a divider to obtain a single high resolution mode calculation value, and generating an enabling signal;
s53, transmitting the single high resolution mode calculation value to the data keeper together with the enable signal.
8. The DSP-direct-averaging-based sample data high-resolution processing method according to claim 4, wherein the step S6 specifically comprises:
s61, truncating the single high resolution mode calculation value through a data retainer, reserving a bit width which is the same as the resolution of the ADC device, removing a decimal part, and generating a new single high resolution mode calculation value;
s62, adding the new single high resolution mode calculation value to the parallel data based on the enable signal, and keeping the parallel data output.
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