CN106788435B - Quantify sampling noise-reduction method - Google Patents
Quantify sampling noise-reduction method Download PDFInfo
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- CN106788435B CN106788435B CN201611144307.4A CN201611144307A CN106788435B CN 106788435 B CN106788435 B CN 106788435B CN 201611144307 A CN201611144307 A CN 201611144307A CN 106788435 B CN106788435 B CN 106788435B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0854—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of quantisation noise
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
Abstract
Quantify sampling noise-reduction method, quantization noise reduction system carries out noise reduction process to quantifying sampled data, and the quantization noise reduction system includes digital processing unit, analog-digital converter and digital analog converter；The digital processing unit includes being used for the noise generating unit for producing digital noise sequence；The noise data that noise generating unit produces is exported to digital analog converter all the way, and digital analog converter data through analog-digital converter after analog signal source data progress simulation trial with being transferred to digital processing unit；Another way is exported to digital processing unit, after being transferred to the data progress digital operation of digital processing unit with analog-digital converter, as subsequent treatment.It is different from conventional method, noise data is introduced the front-end and back-end of analog-digital converter (sampled data) by the present invention respectively, superposition and exclusive or processing is respectively adopted, Double-noise-reduction processing has been carried out equivalent to sampled data, the precision of Noise reducing of data processing can be greatly improved.
Description
Technical field
The invention belongs to sampled-data processing technical field, is related to a kind of data noise reduction, specifically, is related to one kind
Applied to the noise-reduction method for quantization sampled data for quantifying sampling system.
Background technology
Quantizing noise is present in the sampled data for quantifying sampling system.
By taking the data acquisition of near surface FDEM observation systems (near surface frequency domain electromagnetic methods observation system) as an example, such system
The data packet of system collection contains quantizing noise.It is due to number since the quantizing noise of this observation system is a kind of special noise
Caused by quantization sampling according to analog-digital commutator (ADC) when collection, therefore, how to filter all cannot be good
Solve the problems, such as this, and, in the prior art, rarely having people to study reduces the problem of quantifying sampling system quantizing noise.
The content of the invention
The present invention provides a kind of data processing method being applied in quantization sampling system, it is therefore an objective to, reduce and quantify sampling
In system, due to quantifying quantizing noise caused by sampling.
In order to achieve the above object, the present invention provides following technical scheme：Quantify sampling noise-reduction method, quantization noise reduction system pair
Quantify sampled data and carry out noise reduction process, quantization noise reduction system includes digital processing unit, analog-digital converter and digital simulation
Converter；
Digital processing unit includes being used for the noise generating unit for producing digital noise sequence；
The noise data that noise generating unit produces is exported to digital analog converter, digital analog converter data all the way
With being transferred to digital processing unit through analog-digital converter after analog signal source data progress simulation trial；Another way is exported to number
Word processing device, after being transferred to the data progress digital operation of digital processing unit with analog-digital converter, as subsequent treatment.
Preferably：Digital analog converter output termination operational amplifier and low-pass filter, through operation amplifier and filtering
Data afterwards are with after the data investigation of simulation signal generator transmission, being transferred to analog-digital converter.
Preferably：Noise generating unit includes clock trigger element, the n-bit register A for storing noise sequence, is used for
1 bit register B of data buffer storage, for 1 bit register D, 1 bit register E and the 1 bit register F of output data caching, noise
Sequence series is n, and data format is A=(A1,A2,...An)；After clock trigger element obtains clock signal, update and generate number
Word noise, step include：
S1：Initially make An=1, A1, A2... ... An-1It is 0；
S2：Register B is data cached, B=A1；
S3：After clock trigger element obtains clock signal, noise data is calculated as follows in digital processing unit,An=An-1, An-1=An-2... ..., A3=A2, A2=B；
S4：Make data D=A in register Di, wherein 1≤i≤n, makes register E data E=D × C, makes register F numbers
According to F=D, C is integer quotient；
S5：Register E data output noises are overlapped place to digital analog converter, and with analog signal source data
Reason；
S6：After interval time T, register F data are exported to digital processing unit and analog-digital converter and inputted to numeral
The data lowest order of processor carries out XOR operation, overflows bit loss, the last position that data replace former data is obtained, as follow-up place
Reason；
S7：Following clock trigger signal arrives, repeat step S2 to S6；Otherwise, noise reduction process is terminated.
Preferably：C be equal to digital analog converter minimum quantization with the minimum quantization of analog-digital converter ratio
The result of round off rounding.
Preferably：The set-up times of analog-digital converter are added with the hold times, calculating simulation digital quantizer
Time delay, interval time T be equal to analog-digital converter time delay.
Preferably：Analog-digital converter gathered data is simultaneously transferred to digital processing unit, and while transmitting data, clock touches
Bill member is triggered.
Preferably：N is the integer between 4~7.
Beneficial effects of the present invention are：
(1) it is different from conventional method the present invention provides a kind of noise-reduction method for quantifying sampled data, it is of the invention by noise
Data introduce the front-end and back-end of analog-digital converter (sampled data) respectively, superposition and exclusive or processing are respectively adopted, quite
In having carried out Double-noise-reduction processing to sampled data, the precision of Noise reducing of data processing can be greatly improved.
(2) invention further provides a kind of noise-reduction method of the quantization sampled data based on noise sequence, there is provided
A kind of production method of noise sequence.With reference to the characteristics of quantizing noise, noise sequence can realize accurate denoising.
(3) due to adding time delay, it is ensured that the noise of computing is both from same before and after analog-digital converter
The data of one group of noise sequence, so as to reduce error introducing, ensure computational accuracy.
Brief description of the drawings
Fig. 1 is quantization noise reduction system structure diagram.
Fig. 2 is quantization noise reduction flow chart of data processing figure.
Embodiment
The embodiment of the present invention is clearly fully described by below with reference to attached drawing.Obviously, it is embodied
Mode described embodiment is only the part of the embodiment of the present invention, instead of all the embodiments.Based in the present invention
Embodiment, those of ordinary skill in the art's all other embodiments obtained on the premise of creative work is not made,
Belong to protection scope of the present invention.
Quantify sampling noise-reduction method, the method for referring to reduce quantizing noise in sampling system, quantization noise reduction system is to quantifying
Sampled data carries out noise reduction process.
As shown in Figure 1, the wherein described quantization noise reduction system includes digital processing unit, analog-digital converter sum number type matrix
Intend converter；Wherein digital processing unit can use FPGA, ARM, DSP etc., and the bit wide of digital processing unit needs sufficiently large, guarantee
Be not in the situation for losing low data in digital process, analog-digital converter selects more than 24 resolution ratio as far as possible
Chip.
Digital processing unit includes being used for the noise generating unit for producing digital noise sequence；Quantization noise reduction processing uses
Dither digital noises sequence carries out data operation with pending data, realizes noise reduction process.
The Dither noise sequences that noise generating unit produces are exported to digital analog converter, digital-to-analogue conversion all the way
Device data through analog-digital converter after analog signal source data progress simulation trial with being transferred to digital processing unit；Another way is defeated
Go out to digital processing unit, after being transferred to the data progress digital operation of digital processing unit with analog-digital converter, as follow-up
Processing.
Specifically, the analogue data of above analog signal source data, that is, pending.Seen with the system near surface FDEM
Exemplified by the concrete application of examining system (near surface frequency domain electromagnetic methods observation system), analog signal source data makes finger FDEM observations system
Pending analogue data in system.Digital noise sequence divides two-way application, and all the way through digital analog converter, digital noise is believed
Number analogue noise signal is converted to, the analog signal Date1 with being extracted near surface FDEM observation systems is overlapped processing, folds
Data Date2, Date2 are obtained after adding using as the input of analog-digital converter, after being changed, obtains digital signal
Date3, the input as digital processing unit.Another way Dither digital noises sequence signal will be directly output to digital processing unit
In, digital operation, the most final data are carried out with digital signal Date3, as follow-up data processing.
More preferably designed as one kind, digital analog converter output termination operational amplifier and low-pass filter, simulation
Signal Date2 is transferred to simulation numeral after the data investigation of operation amplifier and filtered data with simulation signal generator transmission
Converter.Amplifier and the process of filtering can increase data precision.
Hereinafter, the present embodiment further provides for the production method and tool of digital noise sequence signal in a kind of digital processing unit
The method of the quantization sampled data noise reduction process of body.
Noise generating unit includes clock trigger element, the n-bit register for storing noise sequence in digital processing unit
A, the 1 bit register B for data buffer storage, 1 bit register D, 1 bit register E and 1 bit register for output data caching
F, noise sequence series are n, and data format is A=(A1,A2,...An)；After clock trigger element obtains clock signal, renewal is simultaneously
Digital noise is generated, step includes：
S1：Initially make An=1, A1, A2... ... An-1It is 0；
S2：Register B is data cached, B=A1；
S3：After clock trigger element obtains clock signal, noise data is calculated as follows in digital processing unit,An=An-1, An-1=An-2... ..., A3=A2, A2=B；Specifically with analog-digital converter to digital processing
Device is sent subject to the time of data to trigger the generation of noise sequence, and analog-digital converter gathered data is simultaneously transferred to digital place
Device is managed, while transmitting data, clock trigger element is triggered；
S4：Make data D=A in register Di, wherein 1≤i≤n, makes register E data E=D × C, makes register F numbers
According to F=D, C is integer quotient；The effect of wherein register E is to keep in output to the noise data of analog digital converting unit, is posted
The effect of storage F is to keep in output to digital processing unit, the noise handled with the data that D/A conversion unit is sent
Data；
S5：Register E data output noises are overlapped place to digital analog converter, and with analog signal source data
Reason；
S6：After interval time T, register F data are exported to digital processing unit and analog-digital converter and inputted to numeral
The data lowest order of processor carries out XOR operation, overflows bit loss, the last position that data replace former data is obtained, as follow-up place
Reason；
S7：Following clock trigger signal arrives, repeat step S2 to S6；Otherwise, noise reduction process is terminated.
Above in each step calculating process, n is the integer between 4~7.In view of the application field of digital noise, near surface
Exemplified by the application of FDEM observation systems (near surface frequency domain electromagnetic methods observation system)：According to general near surface FDEM observation systems
ADC acquisition precisions, using the high-precision adc of 24bit, wherein significance bit is 20bit or so, if resolution ratio is more than 24bit,
Then resolution ratio subtracts the result that significance bit obtains and is greater than 4, and current ADC highests digit is not higher than 32bit, and resolution ratio subtracts
The difference of significance bit is not more than 7bit, and according to the calculating digit of current digital processing unit, when general subsequent treatment is not more than
The loss precision of 7bit.Therefore designed according to the requirement, digital noise sequence using 4 to 7 grades.
More than in each step calculating process, C be equal to the minimum quantization of digital analog converter with analog-digital converter most
Low amounts the result than round off rounding.The effect of proportionality coefficient C is to combine analog-digital converter sum number type matrix
Intend the transfer characteristic of converter, coordinate the adjustment for carrying out noise data, avoid introducing noise excessive or too small, cause data to lose
Very.
Above in each step calculating process, by the set-up times (settling time) of analog-digital converter and hold times
(retention time) is added, and the time delay of calculating simulation digital quantizer, interval time T is equal to the delay of analog-digital converter
Time.
5, i is taken to take exemplified by 5 with n to specifically describe the noise reduction process of above quantized data.
S1：Initially make A5=1, A1, A2, A3, A4It is 0；I.e. noise sequence is A=(0,0,0,0,1)；
S2：Register B is data cached, B=A1=0；
S3：Analog-digital converter gathered data is simultaneously transferred to digital processing unit, and while transmitting data, clock triggering is single
Member is triggered；Noise data is calculated as follows in digital processing unit,A5=A4, A4=A3, A3=A2, A2=B；Obtain
The noise sequence obtained is A=(1,0,0,0,0)；
S4：Make data D=A in register D5=0, make register E data E=A5× C, makes register F data F=0, its
In, according to the minimum quantization of digital analog converter and analog-digital converter minimum quantization than round off rounding
Result；
S5：Register E data output noise data are overlapped to digital analog converter, and with analog signal source data
Processing；
S6：After interval time T, register F data are exported to digital processing unit and analog-digital converter and inputted to numeral
The data lowest order of processor carries out XOR operation, overflows bit loss, the last position that data replace former data is obtained, as follow-up place
Reason；
S7：Following clock trigger signal arrives, repeat step S2 to S6；Otherwise, noise reduction process is terminated.
During repetitive noise sequence calculates, the data in noise sequence are shifted or computing again, for example, second
During computing repeatedly, B=A1=1, for the A in last calculating process1Value,A5=A4=0, A4=A3
=0, A3=A2=0, A2=B=1, the noise sequence of acquisition is A=(0,1,0,0,0), and so on.
Claims (6)
1. quantify sampling noise-reduction method, it is characterised in that：Quantization noise reduction system carries out noise reduction process to quantifying sampled data, described
Quantization noise reduction system includes digital processing unit, analog-digital converter and digital analog converter；
The digital processing unit includes being used for the noise generating unit for producing digital noise sequence；
The noise data that noise generating unit produces is exported to digital analog converter, digital analog converter data and mould all the way
Intend signal number and be transferred to digital processing unit through analog-digital converter according to after progress simulation trial；Another way is exported to numeral
Device is managed, after being transferred to the data progress digital operation of digital processing unit with analog-digital converter, as subsequent treatment；
Noise generating unit includes clock trigger element, the n-bit register A for storing noise sequence, 1 for data buffer storage
Bit register B, for 1 bit register D, the 1 bit register E and 1 bit register F of output data caching, the noise sequence level
Number is n, and data format is A=(A1,A2,...An)；After clock trigger element obtains clock signal, update and generate numeral and make an uproar
Sound, step include：
S1：Initially make An=1, A1, A2... ... An-1It is 0；
S2：Register B is data cached, B=A1；
S3：After clock trigger element obtains clock signal, noise data is calculated as follows in digital processing unit,An
=An-1, An-1=An-2... ..., A3=A2, A2=B；
S4：Make data D=A in register Di, wherein 1≤i≤n, makes register E data E=D × C, make register F data F=
D, the C are integer quotient；
S5：Register E data output noises are overlapped processing to digital analog converter, and with analog signal source data；
S6：After interval time T, register F data are exported to digital processing unit and analog-digital converter and inputted to digital processing
The data lowest order of device carries out XOR operation, overflows bit loss, the last position that data replace former data is obtained, as subsequent treatment；
S7：Following clock trigger signal arrives, repeat step S2 to S6.
2. as claimed in claim 1 quantify sampling noise-reduction method, it is characterized in that, digital analog converter output termination computing is put
Big device and low-pass filter, after the data investigation of operation amplifier and filtered data with simulation signal generator transmission, are transferred to
Analog-digital converter.
3. as claimed in claim 1 quantify sampling noise-reduction method, it is characterized in that, the C is equal to digital analog converter most
The low minimum quantization of quantized value and analog-digital converter the result than round off rounding.
4. as claimed in claim 1 quantify sampling noise-reduction method, it is characterized in that, by the set-up times of analog-digital converter
It is added with the hold times, the time delay of calculating simulation digital quantizer, the interval time T is equal to analog-digital converter
Time delay.
5. the quantization sampling noise-reduction method as described in claim 1 or 3 or 4, it is characterized in that, analog-digital converter gathered data
And digital processing unit is transferred to, while transmitting data, clock trigger element is triggered.
6. as claimed in claim 1 quantify sampling noise-reduction method, it is characterized in that, the n is the integer between 4~7.
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| US9871534B2 (en) * | 2016-06-03 | 2018-01-16 | Mediatek Inc. | Analog-to-digital converter with embedded noise-shaped truncation, embedded noise-shaped segmentation and/or embedded excess loop delay compensation |
| CN109495087A (en) * | 2018-12-14 | 2019-03-19 | 深圳先进技术研究院 | Numerical model analysis adaptive notch filter |
| CN113640888B (en) * | 2021-09-24 | 2022-10-14 | 山东大学 | External noise suppression method and system based on frequency domain cross-correlation of transmitted and received signals |
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| CN103560800A (en) * | 2013-11-04 | 2014-02-05 | 中国电子科技集团公司第四十一研究所 | Jitter producing device and jitter producing method for improving flexibility of ADC+FPGA digital receiving system |
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