CN109495087A - Numerical model analysis adaptive notch filter - Google Patents
Numerical model analysis adaptive notch filter Download PDFInfo
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- CN109495087A CN109495087A CN201811540501.3A CN201811540501A CN109495087A CN 109495087 A CN109495087 A CN 109495087A CN 201811540501 A CN201811540501 A CN 201811540501A CN 109495087 A CN109495087 A CN 109495087A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H21/00—Adaptive networks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H21/00—Adaptive networks
- H03H21/0001—Analogue adaptive filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H21/00—Adaptive networks
- H03H21/0012—Digital adaptive filters
- H03H21/002—Filters with a particular frequency response
- H03H21/0021—Notch filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H21/00—Adaptive networks
- H03H21/0012—Digital adaptive filters
- H03H2021/0085—Applications
- H03H2021/0094—Interference Cancelling
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H21/00—Adaptive networks
- H03H2021/0098—Adaptive filters comprising analog and digital structures
Abstract
The present invention provides a kind of numerical model analysis adaptive notch filters, and first by processing chip digital simulation noisy digit signal, anti-fitting noisy digit signal is obtained after negating；After the anti-fitting noisy digit signal is converted into analog signal by DAC, it is superimposed with original signal, the signal of superposition is converted into be input to processing chip after digital signal by ADC, it handles chip application adaptive algorithm and the weight parameter of anti-fitting noisy digit signal is adjusted to obtain new anti-fitting noisy digit signal according to superimposed digital signal, feeding supercircuit starts new circulation after new anti-fitting noisy digit signal is converted into analog signal, finally to be fitted the noise signal that noisy analog signal gradually approaches in original signal, it realizes and original signal is filtered in analog end.This modulus mixed method avoids amplifier saturation problem caused by big noise, has greatly widened the application range of adaptive notch filter, while also compensating for the wide bandwidth defect of simulation trapper.
Description
Technical field
The present invention relates to signal processing technology fields, more particularly, to a kind of numerical model analysis adaptive notch filter.
Background technique
Due in many application scenarios, such as physiological signal (electrocardiosignal, electromyography signal, pulse wave signal etc.) is adopted
Collection process, the bandwidth and 50Hz Hz noise of physiological signal are very close, or even overlapping, since simulation trapper is with biggish
Bandwidth, thus be difficult to be filtered out by the method for analog filter, and increase often may require that by the method for common mode inhibition
One electrode, such as the right leg drive electrode of ecg signal acquiring.
Inhibit single-frequency noise it is maximally efficient be trapper, in traditional digital trap design, in order to make
A certain frequency number obtains sufficiently large decaying, and common practice is exactly that the sufficiently high of order choosing is reached very big decaying but same
When calculation amount also become much larger.And the process of design is complicated, is unfavorable for dynamically adjusting.Adaptive notch filter is with regard to good
It solves the problems, such as above-mentioned.
At present when the signal-to-noise ratio in collected original signal is very low (signal is very weak, and noise is very big), original
Signal will reach saturation by prime analogue amplifier.Therefore it in many application scenarios, needs in analog end just to specific
Noise, such as Hz noise, are effectively inhibited.Since existing adaptive notch filter is all to pass through algorithm logarithm in digital end
Word signal is handled, so that adaptive notch filter can not be suitable for the low-down application scenarios of signal-to-noise ratio, is significantly limited
The application range of adaptive notch filter.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of numerical model analysis adaptive notch filters, at signal
Amplifier saturation problem caused by big noise, widens the application range of adaptive notch filter when reason.
In a first aspect, the embodiment of the invention provides a kind of numerical model analysis adaptive notch filters, comprising: supercircuit, mould
Number converter ADC, digital analog converter DAC and processing chip；Wherein, the supercircuit includes first input end, the second input
End and output end；The output end of the supercircuit is connected to the input terminal of the processing chip by the ADC；The processing
The output end of chip is connected to the second input terminal of the supercircuit by the DAC；
The processing chip digital simulation noisy digit signal, and the fitting noisy digit signal is negated to obtain
Anti-fitting noisy digit signal；The anti-fitting noisy digit signal is converted into anti-fitting noise simulation letter by the DAC
Number；
The original signal of outside acquisition is input to the first input end of the supercircuit, the original signal includes
Imitate signal and noise signal；The anti-fitting noisy analog signal is input to the second input terminal of the supercircuit；
The supercircuit exports the superposed signal of the original signal and the anti-fitting noisy analog signal, and passes through
The superposed signal is converted to superimposed digital signal by ADC, and the superimposed digital signal is input to the processing chip；
The processing chip adjusts several weight parameters of the fitting noisy digit signal by adaptive algorithm；According to
Several weight parameters after adjusting calculate new anti-fitting noisy digit signal, with reduce the anti-fitting noisy digit signal with
The correlation of the superimposed digital signal；And export the input terminal of the new anti-fitting noisy digit signal to the DAC.
With reference to first aspect, the embodiment of the invention provides the first possible embodiments of first aspect, wherein institute
Stating processing chip includes timer；
The processing chip initializes the timer, is the timer setting timing and Interruption
Time is sampled with controlling the ADC and the DAC according to the output of the timer.
The possible embodiment of with reference to first aspect the first, the embodiment of the invention provides second of first aspect
Possible embodiment, wherein the ADC is identical as the sample frequency of the DAC.
With reference to first aspect, the embodiment of the invention provides the third possible embodiments of first aspect, wherein institute
It states processing chip to be also used to: according to the frequency of known noise signal, determining several sinusoidal signals and several cosine signals；It is every
A sinusoidal signal and each cosine signal configure initial weight parameter；According to several sinusoidal signals, several cosine signals and
Weight coefficient obtains initial fitting noisy digit signal；The initial fitting noisy digit signal is negated, is obtained
Initial anti-fitting noisy digit signal；
The DAC is also used to for initial anti-fitting noisy digit signal being converted into initial anti-fitting noise simulation letter
Number, and the initial anti-fitting noisy analog signal is input to the second input terminal of the supercircuit.
The third possible embodiment with reference to first aspect, the embodiment of the invention provides the 4th kind of first aspect
Possible embodiment, wherein the processing chip is also used to: each sine in the fitting noisy digit signal is stored in advance
Component and the cosine component value at each sampled point in one cycle.
With reference to first aspect, the embodiment of the invention provides the 5th kind of possible embodiments of first aspect, wherein institute
Stating supercircuit includes first resistor and second resistance；
First input end of the first end of the first resistor as the supercircuit；
Second input terminal of the first end of the second resistance as the supercircuit；
The second end of the first resistor connects the second end of the second resistance, the second end of the first resistor and institute
State output end of the tie point between the second end of second resistance as supercircuit.
With reference to first aspect, the embodiment of the invention provides the 6th kind of possible embodiments of first aspect, wherein institute
Stating supercircuit includes analogue amplifier；
First input end of the anode of the analogue amplifier as the supercircuit；
Second input terminal of the cathode of the analogue amplifier as the supercircuit；
Output end of the output end of the analogue amplifier as the supercircuit.
With reference to first aspect, the embodiment of the invention provides the 7th kind of possible embodiments of first aspect, wherein institute
Stating adaptive algorithm includes lowest mean square LMS algorithm and recursive least-squares RLS algorithm.
With reference to first aspect, the embodiment of the invention provides the 8th kind of possible embodiments of first aspect, wherein institute
It states processing chip to be also used to: the obtained superimposed digital signal is converted into voltage signal.
With reference to first aspect, the embodiment of the invention provides the 9th kind of possible embodiments of first aspect, wherein institute
Stating fitting noisy digit signal indicates are as follows:
Y (n)=W (1) × sin (2 π ω0n)+W(2)×cos(2πω0n)+W(3)×sin(2πω1n)+W(4)×cos
(2πω1n)
Wherein, n is positive integer, ω0And ω1For the frequency of known noise signal, W (1), W (2), W (3) and W (4) are power
Weight parameter.
The embodiment of the present invention bring it is following the utility model has the advantages that
In embodiments of the present invention, which includes supercircuit, analog-digital converter ADC, number
Mode converter DAC and processing chip；First by the processing chip digital simulation noisy digit signal of digital end, you and noise to this
Digital signal obtains anti-fitting noisy digit signal after negating, wherein fitting noisy digit signal is the noise number to be filtered out of fitting
Word signal；After the anti-fitting noisy digit signal is converted into analog signal by DAC, pass through the folded of analog end with original signal
Power-up road is overlapped, and the signal of superposition is converted into be input to processing chip after digital signal by ADC, is answered by processing chip
The weight parameter for adjusting fitting noisy digit signal according to superimposed digital signal with adaptive algorithm, to obtain new anti-fitting
Noisy digit signal, feeding supercircuit starts new follow after which is converted into analog signal
Ring, to make to handle the noisy digit signal that chip adjusts fitting by adaptive algorithm repeatedly, so that fitting noise simulation letter
Number noise signal in original signal is gradually approached, so that desired useful signal is obtained after the two is superimposed by supercircuit,
It realizes and original signal is filtered in analog end；The saturation problem of analogue amplifier caused by big noise is avoided, this makes adaptive
Trapper is answered to be possibly realized the acquisition of the lower signal of signal-to-noise ratio, compared with the prior art, this modulus mixed method is very big
Widened the application range of adaptive notch filter, while compensate for simulation trapper wide bandwidth defect.
Other features and advantages of the present invention will illustrate in the following description, also, partly become from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention are in specification, claims
And specifically noted structure is achieved and obtained in attached drawing.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram of numerical model analysis adaptive notch filter provided in an embodiment of the present invention；
Fig. 2 is that a kind of signal processing flow of numerical model analysis adaptive notch filter provided in an embodiment of the present invention illustrates signal
Figure；
Fig. 3 is the structural schematic diagram of another numerical model analysis adaptive notch filter provided in an embodiment of the present invention；
Filtering front and back signal contrast schematic diagram when Fig. 4 is a kind of practical application provided in an embodiment of the present invention；
The Fast Fourier Transform (FFT) result of filtering front and back signal when Fig. 5 is a kind of practical application provided in an embodiment of the present invention
Contrast schematic diagram.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with attached drawing to the present invention
Technical solution be clearly and completely described, it is clear that described embodiments are some of the embodiments of the present invention, rather than
Whole embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative work premise
Under every other embodiment obtained, shall fall within the protection scope of the present invention.
At present since there is simulation trapper biggish bandwidth to be difficult to carry out collected original signal noise filtering, one
As using adaptive notch filter carry out denoising.But it when the signal-to-noise ratio in original signal is very low, needs in analog end
Just to specific noise, such as Hz noise, effectively inhibited.Since existing adaptive notch filter is passed through in digital end
Algorithm handles digital signal, so that adaptive notch filter can not be suitable for the low-down application scenarios of signal-to-noise ratio, greatly
Limit the application range of adaptive notch filter.
Based on this, a kind of numerical model analysis adaptive notch filter provided in an embodiment of the present invention be may be implemented in analog end pair
Collected original signal filtering；The saturation problem of analogue amplifier caused by big noise is avoided, this makes adaptive notch
Device is possibly realized the acquisition of the lower signal of signal-to-noise ratio, and compared with the prior art, this modulus mixed method is greatly widened
The application range of adaptive notch filter；The wide bandwidth defect of simulation trapper is also compensated for simultaneously.
Embodiment one
Fig. 1 shows a kind of structural schematic diagram of numerical model analysis adaptive notch filter provided in an embodiment of the present invention.Such as Fig. 1
Shown, which includes: supercircuit, analog-digital converter ADC (Analog to Digital
Converter), digital analog converter DAC (Digital to Analog Converter) and processing chip；Wherein, superposition electricity
Road includes first input end, the second input terminal and output end；The output end of supercircuit is connected to the defeated of processing chip by ADC
Enter end；The output end of processing chip is connected to the second input terminal of supercircuit by DAC.
Wherein processing chip can be at MCU (Microcontroller Unit, micro-control unit) or other numbers
Device is managed, it is specific such as Atmel SAM4S Xplained Pro development board.
In the course of work of the adaptive notch filter, specifically includes the following steps:
It is fitted noise calculation step: processing chip digital simulation noisy digit signal, and to the fitting noisy digit signal
It negates to obtain anti-fitting noisy digit signal, and exports to DAC；Wherein the fitting noisy digit signal is making an uproar wait filter out for fitting
Sound digital signal.
Digital-to-analogue conversion step: by the way that anti-fitting noisy digit signal is converted to anti-fitting noisy analog signal, and will be upper
State the second input terminal that anti-fitting noisy analog signal is input to supercircuit；
New anti-fitting noisy digit signal is converted to new anti-fitting noisy analog signal by above-mentioned DAC；This is new
Anti-fitting noisy analog signal is input to the second input terminal of supercircuit again.
Signal averaging step: the original signal of outside acquisition is input to the first input end of supercircuit, wherein original
Signal is the analog signal acquired in analog end, specifically includes useful signal and noise signal.The original signal, which can be, to be passed through
The noisy signal of the related collected band of sensing element, such as with noisy electrocardiosignal, electromyography signal, pulse signal
Deng.
Analog-to-digital conversion step: supercircuit exports the superposed signal of above-mentioned original signal and anti-fitting noisy analog signal,
And the superposed signal is converted to by superimposed digital signal by ADC, superimposed digital signal is input to processing chip.
Parameter tuning step: processing chip adjusts the fitting noisy digit signal at current sampling point by adaptive algorithm
Several weight parameters, to reduce the correlation of anti-fitting noisy digit signal with superimposed digital signal.Then it again and calculates
New anti-fitting digital signal is simultaneously exported to DAC, that is, re-executes above-mentioned fitting noise calculation step.
Pass through the loop formed in above-mentioned numerical model analysis adaptive notch filter, the numerical model analysis adaptive notch filter meeting in this way
It is repeated in and executes above-mentioned fitting noise calculation step, digital-to-analogue conversion step, Signal averaging step, analog-to-digital conversion step, parameter
Set-up procedure, so that weight parameter is constantly adjusted, so that anti-fitting noisy analog signal gradually approaches negative in original signal make an uproar
Acoustical signal.
Numerical model analysis adaptive notch filter based on the embodiment of the present invention, processing chip pass through adaptive algorithm repeatedly
The noisy digit signal of fitting is adjusted, so that fitting noisy analog signal gradually approaches noise signal in original signal, thus
After the two is superimposed by supercircuit, desired useful signal is obtained, realizes and original signal is filtered in analog end；It avoids big
The saturation problem of analogue amplifier caused by noise, this becomes adaptive notch filter to the acquisition of the lower signal of signal-to-noise ratio
May, compared with the prior art, this modulus mixed method has greatly widened the application range of adaptive notch filter, while more
The wide bandwidth defect of simulation trapper is mended.
Embodiment two
The embodiment of the present application provides another numerical model analysis adaptive notch filter, on the basis of the above embodiment 1,
Referring to fig. 2, the supercircuit of above-mentioned analog end may include first resistor and second resistance；The first end of first resistor is as folded
It is powered on the first input end on road；Second input terminal of the first end of second resistance as supercircuit；The second end of first resistor
The second end for connecting second resistance, the tie point between the second end of first resistor and the second end of second resistance, which is used as, is superimposed electricity
The output end on road.
In addition, can use amplifier also in above-mentioned supercircuit to substitute above-mentioned first resistor and second resistance.Base
In this, above-mentioned supercircuit can also include analogue amplifier (not shown)；The anode of the analogue amplifier is as supercircuit
First input end；Second input terminal of the cathode of analogue amplifier as supercircuit；The output end conduct of analogue amplifier
The output end of supercircuit.
Referring to Fig. 3, in actual application, above-mentioned processing chip includes timer.The numerical model analysis adaptive notch
Before carrying out signal processing, initialization step is first carried out, which includes initializing ADC, DAC and timer,
For timer setting timing and Interruption time, sampled with controlling the ADC and DAC according to the output of timer,
Wherein, ADC is identical as the sample frequency of DAC.Specific timing and Interruption time can be according to actual sampling frequencies
Rate demand is configured.
Then noise signal is fitted by processing chip, for offsetting the noise signal in original signal.Based on this, known
In original signal after the frequency of noise signal, which is also used to: according to the frequency of known noise signal, being determined several
Sinusoidal signal and several cosine signals；Initial weight parameter is configured for each sinusoidal signal and each cosine signal；If according to this
Dry sinusoidal signal, several cosine signals and weight coefficient, obtain initial fitting noisy digit signal；To initial fitting noise
Digital signal is negated, and initial anti-fitting noisy digit signal is obtained.
Intend for example, processor fits noise to be filtered out by the weighted array of sine wave, cosine wave to get to initial
Close noisy digit signal.Assuming that the frequency of known noise signal is ω0And ω1, then the fitting noisy digit signal can indicate
Are as follows:
Y (n)=W (1) × sin (2 π ω0n)+W(2)×cos(2πω0n)+W(3)×sin(2πω1n)+W(4)×cos
(2πω1n) (1)
Wherein, n is positive integer, and W (1), W (2), W (3) and W (4) are weight parameter.The initial value of the weight parameter can be with
But it is not limited to be set as 1.
According to above-mentioned formula (1), the fitting noise calculation step in above-described embodiment one is executed, and to initial fitting noise
Digital signal is negated to obtain-Y (n).
It should be noted that the value due to needing each sampled point Y (n) in digital simulation noisy digit signal,
It needs that each sinusoidal component of fitting noisy digit signal and cosine component is stored in advance in one cycle in processing chip
Value at each sampled point.If sampled point is 1000 in a cycle, then when needing record n=1 to 1000, sin (2 π ω0n)、
cos(2πω0n)、sin(2πω1n)、cos(2πω1N) value calls directly so as to subsequent when calculating Y (1) to Y (1000)
?.
In possible implementation, in order to enable fitting noisy digit signal and the noise signal of simulation to be folded
Add, to filter out the noise signal in original signal, needs to carry out digital-to-analogue conversion to the fitting noisy digit signal, it at this time should-Y
(n) it is scaled the corresponding input value of DAC.For example, the DAC is B, then conversion formula indicates are as follows:
D (n)=- Y (n) × 2B-1+2B-1 (2)
The D (n) is that in actual use, processing chip exports initial anti-fitting noisy digit signal, and by the D (n)
DAC is input to by the channel DAC.
Then DAC executes the digital-to-analogue conversion step in above-described embodiment one, and above-mentioned initial anti-fitting noisy digit is believed
Number D (n) is converted into initial anti-fitting noisy analog signal D (t), and the initial anti-fitting noisy analog signal D (t) is defeated
Enter to the second input terminal of supercircuit.
So that supercircuit executes the Signal averaging step in above-described embodiment one: by the d (t) and first input end
The original signal x (t) of input is overlapped to obtain superposed simulation signal e (t).Wherein x (t) is useful signal s (t) and noise letter
The adduction of number n (t), can be expressed as x (t)=s (t)+n (t), thus e (t)=d (t)+s (t)+n (t).
After obtaining superposed simulation signal e (t), ADC executes the analog-to-digital conversion step in above-described embodiment one: according to preparatory
The Sampling interrupt time of setting samples to above-mentioned, and above-mentioned superposed simulation signal e (t) is converted to superimposed digital signal E
(n), which is input to processing chip by ADC channel.
After processing chip receives above-mentioned E (n), execute above-mentioned parameter set-up procedure: processing chip passes through adaptive algorithm,
Such as lowest mean square LMS algorithm and recursive least-squares RLS algorithm, the weight parameter in above-mentioned formula (1) is adjusted, it is anti-quasi- to reduce
The correlation for closing noisy digit signal and superimposed digital signal, even if d (t) gradually approaches-n (t), thus obtained after superposition
E (t) is desired useful signal s (t).
Then it is adjusted to repeat fitting noise calculation step, calculating parameter in above-described embodiment one for the processing chip
The new anti-fitting digital signal is input to DAC after obtaining new anti-fitting digital signal by new anti-fitting digital signal
Input terminal.
After DAC receives new anti-fitting digital signal, the digital-to-analogue conversion step in above-described embodiment one is repeated: will
New anti-fitting noisy digit signal is converted to new anti-fitting noisy analog signal；By the new anti-fitting noisy analog signal
It is input to the second input terminal of supercircuit again.
It, can be with so according to the timer terminal time of setting due to the circuit in the numerical model analysis adaptive notch filter
Circulation executes above-mentioned Signal averaging step, analog-to-digital conversion step, parameter tuning step and digital-to-analogue conversion step, so that fitting noise
The digital signal gradually noise signal in original signal, to fall the noise signal in original signal after superimposing, thus real
Present analog end realizes the filtering to original signal to the denoising process of the original signal.Therefore, compared with the prior art,
Numerical model analysis adaptive notch filter provided by the invention can in real time be filtered analog signal, and its filtering parameter energy
According to the variation real-time perfoming adjustment of noise in original signal.
Wherein, in above-mentioned parameter set-up procedure, after obtaining superimposed digital signal E (n), voltage is converted by the E (n)
Signal, the voltage signal are to obtain the useful signal s (n) of number after denoising.And the superposition mould exported in Signal averaging step
Quasi- signal is the useful signal s (t) of the simulation obtained after denoising.
In conclusion technical solution provided by the invention, realizes adaptive algorithm by way of numerical model analysis, it will be certainly
The fitting noise that adaptive algorithm generates reversely is converted into analog signal by DAC again, realizes original signal by analog circuit
With being superimposed for inverse noise, noise is filtered out from the most original end of analog signal.And filtering parameter can make an uproar according in signal
The variation real-time perfoming of sound adjusts.
In structure, compared to digital adaptation trapper, do not increase many structures, ADC and DAC are conventional micro- places
The own structure of device is managed, and in analog circuit, only need to add two resistance is implemented with technical solution of the present invention, structure
Simply, it is easy to accomplish.In addition can real-time implementation the analog end of original signal is filtered, simulated so as to avoid caused by big noise
The saturation of amplifier, this to acquire the signal that signal-to-noise ratio is negative；While the numerical model analysis adaptive notch filter is more
The wide bandwidth defect of simulation trapper is mended.In addition, the characteristics of according to adaptive algorithm, filtering parameter can be according to noise in signal
Variation real-time perfoming dynamic adjust.
Technical solution of the present invention is verified on Atmel SAM4S Xplained Pro development board, as a result as schemed
Shown in 4, dotted line is original signal x (t) in figure, and solid line is the filtered signal e (t) of numerical model analysis adaptive notch filter, can be with
Find out after the numerical model analysis adaptive notch filter, signal has obtained significantly inhibiting.Fig. 5 is above-mentioned two signal
For FFT (fast Fourier transform) as a result, can calculate from figure, the attenuation of the numerical model analysis adaptive notch filter is 33.7dB.
Numerical model analysis adaptive notch filter provided in an embodiment of the present invention, with the numerical model analysis provided in above-described embodiment one
Adaptive notch filter technical characteristic having the same reaches identical technical effect so also can solve identical technical problem.
It is apparent to those skilled in the art that for convenience and simplicity of description, the digital-to-analogue of foregoing description
The specific work process of mixed self-adapting trapper can refer in the numerical model analysis adaptive notch filter of previous embodiment one
Corresponding process, details are not described herein.
In addition, term " first ", " second ", " third " are used for description purposes only, it is not understood to indicate or imply phase
To importance.Unless specifically stated otherwise, the opposite step of the component and step that otherwise illustrate in these embodiments, digital table
It is not limit the scope of the invention up to formula and numerical value.
In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, it can be with
It realizes by another way.The apparatus embodiments described above are merely exemplary, for example, the division of the unit,
Only a kind of logical function partition, there may be another division manner in actual implementation, in another example, multiple units or components can
To combine or be desirably integrated into another system, or some features can be ignored or not executed.Another point, it is shown or beg for
The mutual coupling, direct-coupling or communication connection of opinion can be through some communication interfaces, device or unit it is indirect
Coupling or communication connection can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.
Finally, it should be noted that embodiment described above, only a specific embodiment of the invention, to illustrate the present invention
Technical solution, rather than its limitations, scope of protection of the present invention is not limited thereto, although with reference to the foregoing embodiments to this hair
It is bright to be described in detail, those skilled in the art should understand that: anyone skilled in the art
In the technical scope disclosed by the present invention, it can still modify to technical solution documented by previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of technical solution of the embodiment of the present invention, should all cover in protection of the invention
Within the scope of.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. a kind of numerical model analysis adaptive notch filter characterized by comprising supercircuit, analog-digital converter ADC, digital-to-analogue turn
Parallel operation DAC and processing chip；Wherein, the supercircuit includes first input end, the second input terminal and output end；The superposition
The output end of circuit is connected to the input terminal of the processing chip by the ADC；The output end of the processing chip passes through institute
State the second input terminal that DAC is connected to the supercircuit；
The processing chip digital simulation noisy digit signal, and counter intended is negated to the fitting noisy digit signal
Close noisy digit signal；The anti-fitting noisy digit signal is converted into anti-fitting noisy analog signal by the DAC；
The original signal of outside acquisition is input to the first input end of the supercircuit, the original signal includes effectively believing
Number and noise signal；The anti-fitting noisy analog signal is input to the second input terminal of the supercircuit；
The supercircuit exports the superposed signal of the original signal and the anti-fitting noisy analog signal, and passes through ADC
The superposed signal is converted into superimposed digital signal, the superimposed digital signal is input to the processing chip；
The processing chip adjusts several weight parameters of the fitting noisy digit signal by adaptive algorithm；According to adjusting
Several weight parameters afterwards calculate new anti-fitting noisy digit signal, with reduce the anti-fitting noisy digit signal with it is described
The correlation of superimposed digital signal；And export the input terminal of the new anti-fitting noisy digit signal to the DAC.
2. numerical model analysis adaptive notch filter according to claim 1, which is characterized in that the processing chip includes timing
Device；
The processing chip initializes the timer, when being the timer setting timing and Interruption
Between, it is sampled with controlling the ADC and the DAC according to the output of the timer.
3. numerical model analysis adaptive notch filter according to claim 2, which is characterized in that the ADC is adopted with the DAC's
Sample frequency is identical.
4. adaptive notch filter according to claim 1, which is characterized in that the processing chip is also used to: according to known
Noise signal frequency, determine several sinusoidal signals and several cosine signals；For each sinusoidal signal and each cosine signal
Configure initial weight parameter；According to several sinusoidal signals, several cosine signals and weight coefficient, obtains initial fitting and make an uproar
Sound digital signal；The initial fitting noisy digit signal is negated, initial anti-fitting noisy digit signal is obtained；
The DAC is also used to initial anti-fitting noisy digit signal being converted into initial anti-fitting noisy analog signal, and
The initial anti-fitting noisy analog signal is input to the second input terminal of the supercircuit.
5. numerical model analysis adaptive notch filter according to claim 4, which is characterized in that the processing chip is also used to:
Each sinusoidal component and cosine component is stored in advance in the fitting noisy digit signal in one cycle at each sampled point
Value.
6. numerical model analysis adaptive notch filter according to claim 1, which is characterized in that the supercircuit includes the first electricity
Resistance and second resistance；
First input end of the first end of the first resistor as the supercircuit；
Second input terminal of the first end of the second resistance as the supercircuit；
The second end of the first resistor connects the second end of the second resistance, the second end of the first resistor and described the
Output end of the tie point as supercircuit between the second end of two resistance.
7. numerical model analysis adaptive notch filter according to claim 1, which is characterized in that the supercircuit includes that simulation is put
Big device；
First input end of the anode of the analogue amplifier as the supercircuit；
Second input terminal of the cathode of the analogue amplifier as the supercircuit；
Output end of the output end of the analogue amplifier as the supercircuit.
8. numerical model analysis adaptive notch filter according to claim 1, which is characterized in that the adaptive algorithm includes minimum
Square LMS algorithm and recursive least-squares RLS algorithm.
9. numerical model analysis adaptive notch filter according to claim 1, which is characterized in that the processing chip is also used to: will
The obtained superimposed digital signal is converted to voltage signal.
10. numerical model analysis adaptive notch filter according to claim 1, which is characterized in that the fitting noisy digit letter
Number indicate are as follows:
Y (n)=W (1) × sin (2 π ω0n)+W(2)×cos(2πω0n)+W(3)×sin(2πω1n)+W(4)×cos(2πω1n)
Wherein, n is positive integer, ω0And ω1For the frequency of known noise signal, W (1), W (2), W (3) and W (4) are weight ginseng
Number.
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