CN113348562B - Oxide semiconductor thin film, thin film transistor, and sputtering target - Google Patents

Oxide semiconductor thin film, thin film transistor, and sputtering target Download PDF

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CN113348562B
CN113348562B CN202080007374.XA CN202080007374A CN113348562B CN 113348562 B CN113348562 B CN 113348562B CN 202080007374 A CN202080007374 A CN 202080007374A CN 113348562 B CN113348562 B CN 113348562B
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oxide semiconductor
semiconductor layer
thin film
atomic number
number ratio
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CN113348562A (en
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寺前裕美
西山功兵
越智元隆
后藤裕史
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Kobe Steel Ltd
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Abstract

The invention relates to an oxide semiconductor thin film, a thin film transistor and a sputtering target. The oxide semiconductor film has a first oxide semiconductor layer and a second oxide semiconductor layer containing In, ga, zn, sn and O, respectively, the first oxide semiconductor layer satisfying 0.05≦In/In+Ga+Zn+Sn≦0.25、0.20≦Ga/In+Ga+Zn+Sn≦0.60、0.20≦Zn/In+Ga+Zn+Sn≦0.60、0.05≦Sn/In+Ga+Zn+Sn≦0.15, the second oxide semiconductor layer satisfying 0.20≦In/In+Ga+Zn+Sn≦0.60、0.05≦Ga/In+Ga+Zn+Sn≦0.25、0.15≦Zn/In+Ga+Zn+Sn≦0.60、0.01≦Sn/In+Ga+Zn+Sn≦0.20.

Description

Oxide semiconductor thin film, thin film transistor, and sputtering target
The present application is based on japanese patent application (japanese patent application publication No. 2019-02463) filed on 13/2/2019, the content of which is incorporated by reference into the present application.
Technical Field
The present invention relates to an oxide semiconductor thin film and a thin film transistor (Thin Film Transistor, TFT) including an oxide semiconductor layer including the oxide semiconductor thin film. More particularly, the present invention relates to a thin film transistor and an oxide semiconductor thin film contained in the thin film transistor, which are suitably used for a display device such as a liquid crystal display or an organic Electroluminescence (EL) display. In addition, the present invention also relates to a sputtering target (sputtering target) for forming an oxide semiconductor layer including the oxide semiconductor thin film.
Background
Amorphous (amorphous) oxide semiconductors have a high carrier concentration compared to general amorphous silicon (a-Si), and thus are expected to be applied to next-generation displays requiring large-scale/high-resolution/high-speed driving. Further, since an amorphous oxide semiconductor has a large optical band gap (band gap) and can be formed at a low temperature, it can be formed on a resin substrate having low heat resistance, and thus it is expected to be applied to a light and transparent display.
As the amorphous oxide semiconductor described above, for example, as shown In patent document 1, an In-Ga-Zn amorphous oxide semiconductor (hereinafter, sometimes simply referred to as "IGZO") including indium (In), gallium (Ga), zinc (Zn), and oxygen (O) is known.
Prior art literature
Patent literature
Patent document 1: japanese patent application laid-open No. 2010-219538
Disclosure of Invention
Problems to be solved by the invention
However, although the field effect mobility (carrier mobility) of a thin film transistor including an oxide semiconductor layer including IGZO is higher than that of general amorphous silicon, it is about 10cm 2/Vs, and a material having higher field effect mobility is demanded in order to cope with an increase in screen size, high definition, or high-speed driving of a display device.
In addition, a thin film transistor using an oxide semiconductor layer including IGZO is required to have excellent resistance to stress (stress resistance) such as light irradiation or voltage application. That is, the threshold variation of the thin film transistor is required to be small by applying an equal stress to light irradiation or voltage. For example, when a voltage is continuously applied to the gate electrode or light in a blue range that causes absorption is continuously irradiated to the semiconductor layer, charge (charge) is trapped at the interface between the gate insulating film of the thin film transistor and the semiconductor layer, and the threshold voltage may be greatly changed (shift) to the negative side due to a change in charge inside the semiconductor layer. As a result, the switching characteristics of the thin film transistor were changed.
Further, when the liquid crystal panel is driven, when the pixel is turned on by applying a negative bias (bias) to the gate electrode, or the like, light leaking from the liquid crystal cell is irradiated to the TFT, but the light causes stress to the thin film transistor, which causes uneven image or deterioration of characteristics. When a thin film transistor is actually used, if the switching characteristics change due to stress caused by light irradiation or voltage application, the reliability of the display device itself is reduced.
In addition, in the organic EL display, light leakage from the light-emitting layer is similarly irradiated to the semiconductor layer, and there is a problem that a value such as a threshold voltage is deviated.
Such a shift in threshold voltage is highly desirable to improve stress tolerance (i.e., to reduce the amount of change before and after stress application) because it causes a decrease in reliability of a display device itself such as a liquid crystal display or an organic EL display including a thin film transistor.
In addition, the structure of a thin film transistor including the oxide semiconductor layer described above is roughly classified into a Back CHANNEL ETCH, BCE type which has no etching stopper and an etching stop (Etch Stopper Layer, ESL) type which has an etching stopper. Among them, a BCE type structure without an etching stopper is recommended from the viewpoint of simplification of the production steps of the thin film transistor.
In addition, as an electrode material for a gate electrode, a source electrode, a drain electrode, or the like of a thin film transistor, a material having a lower resistance is demanded in order to further improve the performance of a display device. In order to meet such a demand, cu electrodes or Cu alloy electrodes have been used instead of Al alloy electrodes used before, and when forming these wirings, etching solutions such as hydrogen peroxide are used.
However, when a Cu electrode or a Cu alloy electrode is used for a thin film transistor having a BCE structure, the oxide semiconductor layer may be damaged and the thin film transistor characteristics may be degraded because the oxide semiconductor layer is exposed to an etching solution such as a hydrogen peroxide system used in wet etching of the source/drain electrode.
The present invention has been made in view of the above problems, and an object of the present invention is to provide an oxide semiconductor thin film which can obtain a thin film transistor having excellent stress resistance.
In addition, an object of the present invention is to provide a thin film transistor including an oxide semiconductor layer including the oxide semiconductor thin film and capable of maintaining high field effect mobility, and a sputtering target for forming the oxide semiconductor layer.
Technical means for solving the problems
The present inventors have repeatedly studied and found that: the present invention has been completed by solving the above problems by using an oxide semiconductor containing In, ga, zn, sn, and O as metal elements and appropriately controlling the composition of these metal elements. In addition, it was found that: the above problems can be solved by using the oxide semiconductor thin film for a thin film transistor, and the present invention has been completed.
That is, the object of the present invention can be achieved by the following configurations of [1] and [2] in relation to an oxide semiconductor thin film.
[1] An oxide semiconductor film having a first oxide semiconductor layer and a second oxide semiconductor layer,
The first oxide semiconductor layer and the second oxide semiconductor layer contain In, ga, zn, and Sn, and O as metal elements, respectively,
The atomic number ratio of each metal element In the first oxide semiconductor layer to the total of In, ga, zn and Sn is as follows
0.05≦In/(In+Ga+Zn+Sn)≦0.25
0.20≦Ga/(In+Ga+Zn+Sn)≦0.60
0.20≦Zn/(In+Ga+Zn+Sn)≦0.60
0.05≦Sn/(In+Ga+Zn+Sn)≦0.15，
The atomic number ratio of each metal element In the second oxide semiconductor layer to the total of In, ga, zn and Sn is as follows
0.20≦In/(In+Ga+Zn+Sn)≦0.60
0.05≦Ga/(In+Ga+Zn+Sn)≦0.25
0.15≦Zn/(In+Ga+Zn+Sn)≦0.60
0.01≦Sn/(In+Ga+Zn+Sn)≦0.20，
In the first oxide semiconductor layer, the atomic number ratio of In to the sum of In and Sn satisfies
0.30≦In/(In+Sn)≦(101/152)。
[2] An oxide semiconductor film having a first oxide semiconductor layer and a second oxide semiconductor layer,
The first oxide semiconductor layer and the second oxide semiconductor layer contain In, ga, zn, and Sn as metal elements, respectively, and O,
The atomic number ratio of each metal element In the first oxide semiconductor layer to the total of In, ga, zn and Sn is as follows
0.05≦In/(In+Ga+Zn+Sn)≦0.25
0.20≦Ga/(In+Ga+Zn+Sn)≦0.60
0.20≦Zn/(In+Ga+Zn+Sn)≦0.60
0.05≦Sn/(In+Ga+Zn+Sn)≦0.15，
The atomic number ratio of each metal element In the second oxide semiconductor layer to the total of In, ga, zn and Sn is as follows
0.20≦In/(In+Ga+Zn+Sn)≦0.60
0.05≦Ga/(In+Ga+Zn+Sn)≦0.25
0.15≦Zn/(In+Ga+Zn+Sn)≦0.60
0.01≦Sn/(In+Ga+Zn+Sn)≦0.20，
In the first oxide semiconductor layer, the atomic number ratio of In to the sum of In and Sn satisfies
0.30≦In/(In+Sn)≦0.60。
In addition, a preferred embodiment of the present invention related to the oxide semiconductor thin film relates to the following [3].
[3] The oxide semiconductor thin film according to [1] or [2], wherein an atomic number ratio of each metal element In the first oxide semiconductor layer to a total of the In, ga, zn, and Sn satisfies
0.05≦In/(In+Ga+Zn+Sn)≦0.10
0.20≦Ga/(In+Ga+Zn+Sn)≦0.60
0.20≦Zn/(In+Ga+Zn+Sn)≦0.60
0.07≦Sn/(In+Ga+Zn+Sn)≦0.15。
The object of the present invention can be achieved by the following configuration of [4] in relation to a thin film transistor.
[4] A thin film transistor comprising, in order on a substrate, a gate electrode, a gate insulating film, an oxide semiconductor layer comprising the oxide semiconductor thin film according to [1] or [2], a source/drain electrode, and a protective film.
In addition, a preferred embodiment of the present invention related to a thin film transistor relates to the following [5].
[5] The thin film transistor according to [4], wherein the source/drain electrode includes Cu or a Cu alloy.
The object of the present invention can be achieved by the following configurations of [6] and [7] in relation to a sputtering target.
[6] A sputtering target for forming the first oxide semiconductor layer in the thin film transistor according to [4], wherein the first oxide semiconductor layer is formed by a sputtering method
The sputtering target contains In, ga, zn and Sn as metal elements, and O,
The atomic number ratio of each metal element to the total of In, ga, zn and Sn is as follows
0.05≦In/(In+Ga+Zn+Sn)≦0.25
0.20≦Ga/(In+Ga+Zn+Sn)≦0.60
0.20≦Zn/(In+Ga+Zn+Sn)≦0.60
0.05≦Sn/(In+Ga+Zn+Sn)≦0.15，
The atomic number ratio of In to the sum of In and Sn is as follows
0.30≦In/(In+Sn)≦(101/152)。
[7] A sputtering target for forming the first oxide semiconductor layer in the thin film transistor according to [4], and
The sputtering target contains In, ga, zn and Sn as metal elements, and O,
The atomic number ratio of each metal element to the total of In, ga, zn and Sn is as follows
0.05≦In/(In+Ga+Zn+Sn)≦0.25
0.20≦Ga/(In+Ga+Zn+Sn)≦0.60
0.20≦Zn/(In+Ga+Zn+Sn)≦0.60
0.05≦Sn/(In+Ga+Zn+Sn)≦0.15，
The atomic number ratio of In to the sum of In and Sn is as follows
0.30≦In/(In+Sn)≦0.60。
ADVANTAGEOUS EFFECTS OF INVENTION
According to the present invention, an oxide semiconductor film which can obtain a thin film transistor having excellent stress tolerance can be provided.
In addition, according to the present invention, a thin film transistor including an oxide semiconductor layer including the oxide semiconductor thin film and capable of maintaining high field effect mobility, and a sputtering target to form the oxide semiconductor layer can be provided.
Drawings
Fig. 1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention.
[ Description of symbols ]
1: Substrate board
2: Gate electrode
3: Gate insulating film
4: Oxide semiconductor layer
4A: first oxide semiconductor layer
4B: a second oxide semiconductor layer
5: Source/drain electrode
6: Protective film
7: Contact hole
8: Transparent conductive film
Detailed Description
Hereinafter, an oxide semiconductor thin film and a thin film transistor according to an embodiment (this embodiment) of the present invention will be described.
The oxide semiconductor film of the present embodiment has a first oxide semiconductor layer and a second oxide semiconductor layer, each of which contains In, ga, zn, and Sn as metal elements, and O,
The atomic number ratio of each metal element In the first oxide semiconductor layer to the total of In, ga, zn and Sn satisfies
0.05≦In/(In+Ga+Zn+Sn)≦0.25
0.20≦Ga/(In+Ga+Zn+Sn)≦0.60
0.20≦Zn/(In+Ga+Zn+Sn)≦0.60
0.05≦Sn/(In+Ga+Zn+Sn)≦0.15。
The thin film transistor of the present embodiment includes, in order on a substrate, a gate electrode, a gate insulating film, an oxide semiconductor layer including the oxide semiconductor thin film, source/drain electrodes, and a protective film.
In this embodiment, the oxide formed of In, ga, zn, sn and O is sometimes referred to as IZGTO. The total content (atomic ratio) of In, ga, zn, and Sn with respect to all metal elements (In, ga, zn, and Sn) other than O may be referred to as In atomic ratio, ga atomic ratio, zn atomic ratio, and Sn atomic ratio, respectively.
< First oxide semiconductor layer in oxide semiconductor film >)
[0.05≦In/(In+Ga+Zn+Sn)≦0.25]
In is an element that contributes to improvement of electrical conductivity. Since the conductivity of the oxide semiconductor thin film increases as the atomic number ratio of In is larger, that is, as the amount of In all metal elements is larger, the field-effect mobility of the thin film transistor increases when the oxide semiconductor thin film of the present embodiment is used as an oxide semiconductor layer (channel layer) of the thin film transistor.
In order to effectively exert the above-described effect, the In atomic number ratio needs to be 0.05 or more. The In atomic number ratio is preferably 0.08 or more. However, if the In atomic number ratio is too large, there are problems such as an excessive increase In carrier density and a decrease In threshold voltage, and therefore the In atomic number ratio is set to 0.25 or less. The In atomic number ratio is preferably 0.20 or less, more preferably 0.15 or less, and still more preferably 0.10 or less.
[0.20≦Ga/(In+Ga+Zn+Sn)≦0.60]
Ga is an element that helps to reduce oxygen vacancies and control carrier density. The higher the Ga atomic number ratio, that is, the larger the amount of Ga in all metal elements, the higher the electrical stability of the oxide semiconductor thin film, and when the oxide semiconductor thin film of the present embodiment is used as an oxide semiconductor layer (channel layer) of a thin film transistor, the effect of suppressing excessive generation of carriers of the thin film transistor is exhibited. Further, ga is also an element that inhibits etching by a hydrogen peroxide Cu etching solution. Therefore, the larger the Ga atomic number ratio, the more the selection ratio with respect to the hydrogen peroxide-based etching solution used in the etching process of the Cu electrode as the source/drain electrode is, the less likely to be damaged.
In order to effectively exert the above-described effect, it is necessary to set the Ga atomic number ratio to 0.20 or more. The Ga atomic number ratio is preferably 0.25 or more. However, if the Ga atomic number ratio is too large, the conductivity of the oxide semiconductor thin film decreases, and the field-effect mobility tends to decrease. In addition, the conductivity of a sputtering target for forming an oxide semiconductor layer is reduced, and it is difficult to stably continue dc discharge. Therefore, the Ga atomic number ratio is set to 0.60 or less. The Ga atomic number ratio is preferably 0.45 or less, more preferably 0.35 or less, and still more preferably 0.30 or less.
[0.20≦Zn/(In+Ga+Zn+Sn)≦0.60]
The Zn is not as sensitive to the thin film transistor characteristics as other metal elements, but the larger the Zn atomic number ratio, that is, the larger the amount of Zn in all metal elements, the more easily amorphized, and therefore, when a thin film transistor having a first oxide semiconductor layer including the oxide semiconductor thin film of the present embodiment is manufactured, it is easily etched by an etching solution of an organic acid or an inorganic acid.
In order to effectively exert the above-described effect, the Zn atomic number ratio needs to be 0.20 or more. The Zn atomic number ratio is preferably 0.30 or more, more preferably 0.40 or more, and still more preferably 0.50 or more. However, if the Zn atomic number ratio is too large, the solubility of the oxide semiconductor thin film with respect to the source/drain electrode etchant becomes high, and as a result, the following may occur: the wet etching resistance tends to be poor, or the field effect mobility tends to be low due to a relative decrease In, or the electrical stability of the oxide semiconductor thin film tends to be low due to a relative decrease In Ga. Therefore, the Zn atomic number ratio is set to 0.60 or less. The Zn atomic number ratio is preferably 0.55 or less.
[0.05≦Sn/(In+Ga+Zn+Sn)≦0.15]
Sn is an element that inhibits etching by an acidic chemical solution. Therefore, the larger the Sn atomic number ratio, that is, the larger the amount of Sn occupied in all metal elements, the more difficult the etching process by the etching solution containing the organic acid or the inorganic acid used for patterning of the first oxide semiconductor layer of the oxide semiconductor thin film of the present embodiment is. However, the oxide semiconductor to which Sn is added exhibits an increase in carrier density by hydrogen diffusion, and thus field effect mobility increases, and if the amount of Sn added is moderate, the reliability of the thin film transistor with respect to optical stress increases.
In order to effectively exert the above-described effect, the Sn atomic number ratio needs to be 0.05 or more. The Sn atomic number ratio is preferably 0.07 or more. On the other hand, if the Sn atomic ratio is too large, the resistance of the oxide semiconductor thin film to the etching solution of an organic acid or an inorganic acid increases to a necessary extent or more, and processing of the oxide semiconductor thin film itself becomes difficult. In addition, there is a concern that the reliability against optical stress is lowered due to the strong influence of hydrogen diffusion. Therefore, the Sn atomic number ratio is set to 0.15 or less. The Sn atomic number ratio is preferably 0.10 or less.
Further, the oxide semiconductor film preferably has an atomic ratio of In to the sum of In and Sn of
0.30≦In/(In+Sn)≦0.75。
If In/(in+sn) In the relation between the amounts of In and Sn is less than 0.30, the carrier density decreases, the conductivity decreases, and the field effect mobility of the thin film transistor tends to decrease. On the other hand, if In/(in+sn) exceeds 0.75 In the relation between the amounts of In and Sn added, the reliability against stress is lowered.
In/(in+sn) In the relation between the amounts of In and Sn added is more preferably 0.40 or more. In/(in+sn) is more preferably 0.67 or less, and still more preferably 0.60 or less.
Further, the oxide semiconductor thin film preferably has a atomic number ratio of Ga to the sum of Ga and Sn of
0.75≦Ga/(Ga+Sn)≦0.99。
When the oxide semiconductor thin film of the present embodiment is used as an oxide semiconductor layer of a thin film transistor, if the Ga content in the oxide semiconductor thin film is increased, the carrier density decreases, the conductivity decreases, and the field effect mobility of the thin film transistor tends to decrease. However, on the other hand, the wet etching resistance to the hydrogen peroxide etching solution is improved. In addition, if the addition amount of Sn is increased, the effect of hydrogen diffusion from the protective film becomes remarkable, and the carrier density and conductivity tend to increase due to hydrogen diffusion.
In addition, when the In addition amount is to be increased In order to cope with a decrease In field effect mobility, which is a disadvantage of increasing the Ga addition amount, or a decrease In conductivity of the sputtering target, there is a concern that a decrease In reliability of the thin film transistor with respect to optical stress, a shift In threshold voltage to a negative voltage side, or the like may occur.
On the other hand, when the Sn addition amount is increased instead of In, the decrease In field effect mobility is suppressed, and the conductivity of the sputtering target is improved. In addition, when the Sn addition amount is increased, the threshold voltage tends to be stabilized around 0V. Therefore, it is considered that In the case of increasing the Ga addition amount, it is effective to increase the Sn addition amount instead of increasing the In addition amount.
However, the addition amount of Sn has a proper addition range, and if the addition range is exceeded, deterioration of the optical stress tolerance of the thin film transistor becomes remarkable. Therefore, by adding Ga so as to satisfy the relationship between the amounts of Ga and Sn, a highly reliable oxide semiconductor can be obtained.
Further, ga/(ga+sn) in the relation of the addition amounts of Ga and Sn is more preferably 0.80 or more, and still more preferably 0.85 or more. Further, ga/(ga+sn) is more preferably 0.95 or less, and still more preferably 0.90 or less.
The thickness of the first oxide semiconductor layer is not particularly limited, but is preferably 15nm or more because the selectivity at the time of etching of the source/drain electrode is excellent if it is 10nm or more. In addition, in terms of maintaining high field effect mobility, it is preferably 40nm or less, for example.
Thin film transistor
Next, the thin film transistor according to this embodiment will be described in further detail.
Hereinafter, embodiments of the thin film transistor according to the present invention will be described in further detail with reference to the accompanying drawings. However, these are merely examples of preferred embodiments, and the present invention is not limited to these embodiments.
As shown in fig. 1, a gate electrode 2 and a gate insulating film 3 are formed on a substrate 1, and a (first) oxide semiconductor layer 4 is formed thereon. A source/drain electrode 5 is formed on the (first) oxide semiconductor layer 4, and a protective film (insulating film) 6 is formed thereon, and the transparent conductive film 8 is electrically connected to the source/drain electrode 5 via a contact hole 7. Since the (first) oxide semiconductor layer 4 includes the oxide semiconductor thin film, the atomic number of the metal element in the (first) oxide semiconductor layer 4 is as described in the oxide semiconductor thin film of the present embodiment.
The method for forming the gate electrode 2 and the gate insulating film 3 on the substrate 1 is not particularly limited, and a commonly used method can be adopted. The types of metals forming the gate electrode 2 and the gate insulating film 3 are not particularly limited, and common metals may be used. For example, in forming the gate electrode 2, a metal such as Al or Cu having low resistivity, a high melting point metal such as Mo, cr, ti having high heat resistance, or an alloy of these metals may be preferably used.
Further, the gate electrode 2 may be a stacked layer including a plurality of layers. In addition, siO x、SiNx or the like can be typically used in forming the gate insulating film 3. Oxides such as Al 2O3 and Y 2O3 may be used, or these may be laminated.
The gate insulating film 3 may be, for example, a stacked gate insulating film in which a SiO x film and a SiN x film are formed continuously. Since the SiN x film has a higher film formation rate and a higher dielectric constant than those of the SiO x film, the total film thickness can be made thinner by using such a laminated gate insulating film.
Then, the (first) oxide semiconductor layer 4 having the composition is formed. The (first) oxide semiconductor layer 4 can be formed by, for example, a Direct Current (DC) sputtering method or a Radio Frequency (RF) sputtering method using a sputtering target having the same composition as that of the (first) oxide semiconductor layer 4 to be formed. Alternatively, the film may be formed by a co-sputtering (co-sputtering) method using a plurality of sputtering targets.
The (first) oxide semiconductor layer 4 is subjected to wet etching with an organic acid such as oxalic acid or an inorganic acid, and then patterned. In order to improve the film quality of the (first) oxide semiconductor layer 4, it is preferable to perform heat treatment (pre-annealing) immediately after patterning. Accordingly, on-current and field-effect mobility, which are transistor characteristics, are increased, and thus thin film transistor performance is improved. Examples of the pre-annealing conditions include the temperature: about 250 ℃ to 400 ℃ for the time of: about 10 minutes to 1 hour, etc.
Source/drain electrodes 5 are formed after pre-annealing. In this embodiment, as shown in fig. 1, the source/drain electrode 5 is directly bonded to the (first) oxide semiconductor layer 4 except for the channel region.
The type of the source/drain electrode 5 is not particularly limited, and a common source/drain electrode may be used. For example, a metal or alloy such as Al, mo, cu, ti can be used similarly to the gate electrode 2. Among these, cu or a Cu alloy is preferably used because of its low resistivity.
As a method for forming the source/drain electrode 5, for example, after forming a metal thin film by a magnetron sputtering (magnetron sputtering) method, patterning is performed by photolithography (photolithography), and wet etching is performed by a hydrogen peroxide-based or phosphoric acid nitric acid acetic acid-based etching solution, thereby forming an electrode.
Next, a protective film (insulating film) 6 is formed on the (first) oxide semiconductor layer 4 by a chemical vapor deposition (Chemical Vapor Deposition, CVD) method or the like. Further, the surface of the (first) oxide semiconductor layer 4 is easily turned on by plasma damage (PLASMA DAMAGE) caused by CVD (presumably because oxygen vacancies generated at the surface of the oxide semiconductor become electron donors), and thus N 2 O plasma irradiation may be performed before the formation of the protective film 6. The irradiation conditions of the N 2 O plasma may be those described in the following documents.
J. Park (j. Park) et al, applied physical express (appl. Phys. Lett.), 93,053505 (2008)
Here, in the present embodiment, the protective film 6 contains SiO x. The SiO x is formed in an oxidizing atmosphere, and thus there is a concern that the source/drain electrode 5 including Cu or Cu alloy is oxidized. Therefore, a Cu alloy having high oxidation resistance may be used for the source/drain electrode 5, or a cap layer (e.g., mo or Mo alloy film) formed of a high melting point metal may be laminated on the source/drain electrode 5 to prevent oxidation, or a resin layer or SiN x may be formed thin before forming SiO x. In order to prevent the influence of moisture absorption from the outside, a resin layer or SiN x film may be further stacked on the protective film 6 containing SiO x.
Next, a contact hole 7 is formed by a method generally used, and an indium tin oxide film (ITO film) or the like is further formed, whereby a transparent conductive film 8 electrically connected to the source/drain electrode 5 via the contact hole 7 is formed. The type of the transparent conductive film 8 is not particularly limited, and a commonly used transparent conductive film can be used.
Next, a preferred embodiment of the thin film transistor of the present invention will be described with reference to fig. 2. As shown in fig. 2, in the thin film transistor of the present embodiment, a gate electrode 2, a gate insulating film 3, a second oxide semiconductor layer (channel forming layer) 4B, a first oxide semiconductor layer (back channel layer) 4A, source/drain electrodes 5, and a protective film 6 are sequentially stacked on a substrate 1, and a transparent conductive film 8 is electrically connected to the source/drain electrodes 5 via contact holes 7. The first oxide semiconductor layer 4A in the thin film transistor of the present embodiment is the same as the oxide semiconductor layer 4 in the thin film transistor of the embodiment shown in fig. 1, and an oxide semiconductor layer having the above-described composition is used.
Note that, in the second oxide semiconductor layer 4B, IGZTO is used similarly to the first oxide semiconductor layer 4A, but the metal element ratio may be different from IGZTO used in the first oxide semiconductor layer 4A. More specifically, when the atomic number ratios of In, ga to the total of In, ga, zn, and Sn In the first oxide semiconductor layer 4A are respectively [ In1] and [ Ga1], and the atomic number ratios of In, ga to the total of In, ga, zn, and Sn In the second oxide semiconductor layer 4B are respectively [ In2] and [ Ga2], it is preferable that the conditions are satisfied
[In1]≦[In2]、
[Ga1]≧[Ga2]。
Here, as described above, the first oxide semiconductor layer 4A directly exposed to the etching liquid for source/drain electrode processing is excellent in wet etching resistance, and thus damage to the surface of the oxide semiconductor layer at the time of source/drain electrode processing is small, and thus good thin film transistor characteristics are easily obtained. In addition, the reliability of the first oxide semiconductor layer 4A with respect to optical stress is also high.
On the other hand, the second oxide semiconductor layer 4B satisfying the relationship can obtain high field-effect mobility, and by forming the second oxide semiconductor layer 4B under the first oxide semiconductor layer 4A, the field-effect mobility as a whole of the oxide semiconductor layer can be maintained high while having excellent wet etching resistance.
Further, in terms of achieving higher field effect mobility as the whole oxide semiconductor layer, it is preferable that the atomic number ratio of each metal element In the second oxide semiconductor layer 4B with respect to the total of In, ga, zn, and Sn satisfies
0.20≦In/(In+Ga+Zn+Sn)≦0.60
0.05≦Ga/(In+Ga+Zn+Sn)≦0.25
0.15≦Zn/(In+Ga+Zn+Sn)≦0.60
0.01≦Sn/(In+Ga+Zn+Sn)≦0.20。
The first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B have different ratios of the respective metal elements, but are the same In terms of containing In, ga, zn, and Sn as the metal elements constituting the respective layers. In general, when the oxide semiconductor layer is formed in a stacked structure, there is a problem that, depending on the type or content of metal, the amount of undercut (SIDE ETCHING) in the first layer and the second layer is different when forming the wiring pattern, and patterning into a desired shape is not possible. However, in this embodiment, even if the oxide semiconductor layers are stacked, the etching rates of the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B can be set to be substantially equal. As a result, the laminated structure can be etched integrally by being soluble in the wet etching liquid for oxide processing.
Further, by using the same composition system for the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B, disorder of the composition in the lamination interface is reduced, and abrupt change in depth distribution of each metal element is prevented, so that peeling, segregation, abnormal grain growth, and the like of the film when subjected to thermal history in the manufacturing step can also be prevented.
< Sputtering target >)
The present embodiment also relates to a sputtering target for forming the first oxide semiconductor layer 4A in the thin film transistor. As the sputtering target, a sputtering target containing the above-described element and having the same composition as that of the desired oxide semiconductor layer is preferably used, and thus, the oxide semiconductor layer having a desired composition can be formed with little composition difference.
Specifically, the sputtering target of the present embodiment contains In, ga, zn, and Sn, and O as metal elements,
The atomic number ratio of each metal element to the total of In, ga, zn and Sn is as follows
0.05≦In/(In+Ga+Zn+Sn)≦0.25
0.20≦Ga/(In+Ga+Zn+Sn)≦0.60
0.20≦Zn/(In+Ga+Zn+Sn)≦0.60
0.05≦Sn/(In+Ga+Zn+Sn)≦0.15。
The preferred numerical ranges and reasons for limiting the In, ga, zn, and Sn In the sputtering target according to the present embodiment are the same as those described In the above-mentioned oxide semiconductor thin film.
Examples
The present invention will be described in more detail with reference to examples and comparative examples, but the present invention is not limited to these examples.
Examples 1 to 4
The thin film transistor having the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B is manufactured by the following procedure.
As shown in fig. 2, first, a Mo thin film (film thickness 100 nm) as a gate electrode 2 was formed on a glass substrate 1 (Eagle XG, diameter 100nm×thickness 0.7 mm) manufactured by Corning, inc, and patterned into the shape of the gate electrode 2 by photolithography. Then, a SiO x film (film thickness 250 nm) was formed as the gate insulating film 3. The gate electrode 2 is formed by sputtering using a Mo sputtering target. The gate insulating film 3 is formed by a plasma CVD method. The film formation conditions of the gate electrode 2 and the gate insulating film 3 are shown below.
(Film Forming conditions of Gate electrode)
Film formation temperature: room temperature
Film forming power: 300W
Carrier gas: ar (Ar)
Gas pressure: 2mTorr
(Conditions for forming Gate insulating film)
Carrier gas: mixed gas of SiH 4 and N 2 O
Film forming power: 300W
Film formation temperature: 320 DEG C
Next, in is formed on the gate insulating film 3: ga: zn: sn=4: 1:4: an oxide semiconductor layer composed of 1 was used as the second oxide semiconductor layer 4B (film thickness 40 nm). Then, an oxide semiconductor layer having various compositions described in table 1 below was formed as a first oxide semiconductor layer 4A (film thickness 40 nm) over 4B. The first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B are formed by sputtering. The sputtering apparatus used in sputtering was "CS-200" manufactured by Alfa (ULVAC) (Inc.), and sputtering conditions for forming the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B were as follows.
(Sputtering conditions for Forming the first oxide semiconductor layer and the second oxide semiconductor layer)
Substrate temperature: room temperature
Gas pressure: 1mTorr
Partial pressure of oxygen: 100×o 2/(Ar+O2) =4%
After the oxide semiconductor layer 4A and the oxide semiconductor layer 4B including IGZTO are formed in this manner, patterning is performed by photolithography and wet etching. As the wet etching liquid, "ITO-07N" manufactured by Kanto chemical Co., ltd., which is an etching liquid containing oxalic acid, was used, and the liquid temperature was set to room temperature.
As described above, after patterning the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B, a pre-annealing treatment is performed to improve the film quality of the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B. The pre-annealing treatment was carried out in an atmospheric environment and at 400 ℃ for 1 hour.
Next, source/drain electrodes 5 are formed. Specifically, a MoNb film having a film thickness of 35nm and a Cu film having a film thickness of 300nm are continuously formed, and patterning is performed by photolithography and wet etching using a hydrogen peroxide-based chemical solution, thereby forming the source/drain electrode 5 having a laminated structure. In patterning, an inorganic etching solution of hydrogen peroxide water (H 2O2) was used. By patterning the source/drain electrode 5, the channel length of the TFT was set to 10 μm and the channel width was set to 200 μm.
After the source/drain electrodes 5 were formed in the above-described manner, a SiO x film was formed at a film thickness of 200nm by a plasma CVD method using "PD-220NL" manufactured by SAMCO (SAMCO), and further a SiN x film was formed at a film thickness of 150nm, whereby the protective film 6 including a SiO x film and a SiN x film was formed. The film formation conditions of the SiO x film and the SiN x film are shown below.
(Film Forming conditions of SiO x film)
Carrier gas: mixed gas of SiH 4 and N 2 O
Film forming power: 100W
Film formation temperature: 230 DEG C
(Conditions for film formation of SiN x film)
Carrier gas: mixed gas of NH 3、N2 and N 2 O
Film forming power: 100W
Film formation temperature: 150 DEG C
Further, for the protective film 6, an annealing treatment was performed in the atmosphere at 300 ℃ for 1 hour, a photo-setting resin was formed on the protective film 6 with a film thickness of 600nm using a spin coater, then a via hole pattern was formed by photolithography, and a contact hole 7 was formed in the protective film 6 by a reactive ion etching (Reactive Ion Etching, RIE) plasma etching apparatus.
Finally, a post-annealing (post-annealing) treatment was carried out under nitrogen atmosphere and at 250 ℃ for 30 minutes. The thin film transistor was manufactured by the above procedure.
Comparative example 1
Except that Sn-free and composition In: ga: zn=1: 2:1 as an oxide semiconductor layer 4A (film thickness 40 nm), a thin film transistor of comparative example 1 was produced in the same manner as in example.
Comparative example 2
Except that Sn-free and composition In: ga: zn=1: 3:3 as an oxide semiconductor layer 4A (film thickness 40 nm), a thin film transistor of comparative example 2 was produced in the same manner as in example.
Comparative example 3
A thin film transistor of comparative example 3 was manufactured in the same manner as in example, except that the oxide semiconductor layer 4A was not formed, that is, only the second oxide semiconductor layer 4B was formed.
With respect to each thin film transistor obtained in the above manner, the thin film transistor characteristics and stress tolerance were evaluated under the following conditions.
[ Measurement of transistor characteristics ]
A semiconductor parameter analyzer (semiconductor parameter analyzer) of "HP4156C" manufactured by agilent technology (Agilent Technologies) was used for measuring transistor characteristics (drain current-gate voltage characteristics, I d-Vg characteristics).
The detailed measurement conditions are as follows.
Source voltage: 0V
Drain voltage: 10V
Gate voltage: -30V (measurement interval: 0.25V)
Substrate temperature: room temperature
< Field effect mobility >)
The field effect mobility (μ FE) is derived in the saturation region of V g>Vd-Vth according to the TFT characteristics. In the saturation region, V g is set to a gate voltage, V d is set to a drain voltage, I d is set to a drain current, L, W is set to a channel length and a channel width of the TFT element, C i is set to an electrostatic capacity of the gate insulating film, and μ FE is set to field effect mobility. Mu FE is derived from the following equation.
[ Number 1]
In this embodiment, the field-effect mobility μ FE is derived from the slope rate satisfying the drain current-gate voltage characteristic (I d-Vg characteristic) in the vicinity of the gate voltage of the line-shaped region. In the present example and comparative example, the field-effect mobility was determined to be high when the field-effect mobility was 20.0cm 2/Vs or more.
< Threshold Voltage >
The threshold voltage (V th) is a value of the gate voltage when the transistor is shifted from an off state (a state in which the drain current is low) to an on state (a state in which the drain current is high). In this example, the gate voltage at which the drain current of the thin film transistor became 10 -9 a was defined as the threshold voltage, and the threshold voltage (V) of each thin film transistor was measured.
< S value (subthreshold swing) >)
The S value is the minimum value of the amount of change in gate voltage required to raise the drain current by 1 bit, and the scale of switching off of the TFT can be evaluated by measuring the S value. In this example, the S value was 0.5 (V/decade) or less, and the characteristics were judged to be good.
[ Stress tolerance ]
In this example, a stress application test was performed in which a positive bias was continuously applied to the gate electrode for 2 hours, and the variation value (threshold voltage shift amount: Δv th) of the threshold voltage (V th) before and after the stress application test was used as an index of stress tolerance in the TFT characteristics.
The conditions of the stress application test are as follows.
Gate voltage: +20V
Source/drain voltage: 0.1V
Substrate temperature: 60 DEG C
Stress application time: for 2 hours
In the present example and comparative example, the offset (Δv th) of the threshold voltage (V th) before and after the stress application test was determined to be 3.0V or less, and the stress tolerance was determined to be excellent.
The composition of the first oxide semiconductor layer in examples 1 to 4 is shown in table 1 below, and the evaluation results in examples 1 to 4 and comparative examples 1 to 3 are shown in table 2 below.
TABLE 1
TABLE 2
As shown in tables 1 and 2, the composition of each metal element in the oxide semiconductor layer used in the thin film transistor of each example was within the range defined in the present invention, and as a result, the field-effect mobility was 20.0cm2/Vs or more, the S value was 0.5 (V/decade) or less, and the offset (Δv th) of the threshold voltage (V th) before and after the stress application test was 3.0V or less, and the coexistence of high field-effect mobility, a small S value, and excellent stress tolerance was realized.
In comparative examples 1 and 2, the atomic number ratio of In, ga and Zn was within the range of the present invention, but since Sn was not contained, the evaluation results of stress tolerance and S value were poor.
In comparative example 3, the oxide semiconductor layer 4A was not formed but only the second oxide semiconductor layer 4B was formed, but the second oxide semiconductor layer was damaged and the S value was high because the second oxide semiconductor layer was exposed to the etching liquid although the field effect mobility was excellent.
While various embodiments have been described above with reference to the drawings, the present invention is not limited to the examples. It is obvious to those skilled in the art that various modifications and corrections are conceivable within the scope of the appended claims, and it is understood that these are naturally also within the technical scope of the present invention. The components of the above-described embodiments may be arbitrarily combined within a range not departing from the gist of the invention.

Claims (16)

1. An oxide semiconductor film having a first oxide semiconductor layer and a second oxide semiconductor layer,
The first oxide semiconductor layer and the second oxide semiconductor layer contain In, ga, zn, and Sn as metal elements, respectively, and O,
The atomic number ratio of each metal element In the first oxide semiconductor layer to the total of In, ga, zn and Sn is as follows
0.05≦In/（In+Ga+Zn+Sn）≦0.25
0.20≦Ga/（In+Ga+Zn+Sn）≦0.60
0.20≦Zn/（In+Ga+Zn+Sn）≦0.60
0.05≦Sn/（In+Ga+Zn+Sn）≦0.15，
The atomic number ratio of each metal element In the second oxide semiconductor layer to the total of In, ga, zn and Sn is as follows
0.20≦In/（In+Ga+Zn+Sn）≦0.60
0.05≦Ga/（In+Ga+Zn+Sn）≦0.25
0.15≦Zn/（In+Ga+Zn+Sn）≦0.60
0.01≦Sn/（In+Ga+Zn+Sn）≦0.20，
In the first oxide semiconductor layer, the atomic number ratio of In to the sum of In and Sn satisfies
0.30≦In/（In+Sn）≦（101/152），
In the first oxide semiconductor layer, the atomic number ratio of Ga to the sum of Ga and Sn satisfies
0.75≦Ga/（Ga+Sn）≦0.99。
2. The oxide semiconductor thin film according to claim 1, wherein an atomic number ratio of each metal element In the first oxide semiconductor layer to a total of the In, ga, zn, and Sn satisfies
0.05≦In/（In+Ga+Zn+Sn）≦0.10
0.20≦Ga/（In+Ga+Zn+Sn）≦0.60
0.20≦Zn/（In+Ga+Zn+Sn）≦0.60
0.07≦Sn/（In+Ga+Zn+Sn）≦0.15。
3. A thin film transistor having a gate electrode, a gate insulating film, the oxide semiconductor thin film according to claim 1, source/drain electrodes, and a protective film in this order on a substrate.
4. The thin film transistor of claim 3, wherein the source/drain electrode comprises Cu or a Cu alloy.
5. A sputtering target for forming the first oxide semiconductor layer in the thin film transistor according to claim 3, and
The sputtering target contains In, ga, zn and Sn as metal elements, and O,
The atomic number ratio of each metal element to the total of In, ga, zn and Sn is as follows
0.05≦In/（In+Ga+Zn+Sn）≦0.25
0.20≦Ga/（In+Ga+Zn+Sn）≦0.60
0.20≦Zn/（In+Ga+Zn+Sn）≦0.60
0.05≦Sn/（In+Ga+Zn+Sn）≦0.15，
The atomic number ratio of In to the sum of In and Sn is as follows
0.30≦In/（In+Sn）≦（101/152），
The atomic number ratio of Ga to the sum of Ga and Sn is satisfied
0.75≦Ga/（Ga+Sn）≦0.99。
6. The sputtering target according to claim 5, wherein the atomic number ratio of each metal element to the sum of In, ga, zn and Sn is as follows
0.05≦In/（In+Ga+Zn+Sn）≦0.10
0.20≦Ga/（In+Ga+Zn+Sn）≦0.60
0.20≦Zn/（In+Ga+Zn+Sn）≦0.60
0.07≦Sn/（In+Ga+Zn+Sn）≦0.15。
7. A sputtering target for forming the first oxide semiconductor layer in the thin film transistor according to claim 3, and
The sputtering target contains In, ga, zn and Sn as metal elements, and O,
The atomic number ratio of each metal element to the total of In, ga, zn and Sn is as follows
0.05≦In/（In+Ga+Zn+Sn）≦0.25
0.20≦Ga/（In+Ga+Zn+Sn）≦0.60
0.20≦Zn/（In+Ga+Zn+Sn）≦0.60
0.05≦Sn/（In+Ga+Zn+Sn）≦0.15，
The atomic number ratio of In to the sum of In and Sn is as follows
0.30≦In/（In+Sn）≦0.60，
The atomic number ratio of Ga to the sum of Ga and Sn is satisfied
0.75≦Ga/（Ga+Sn）≦0.99。
8. The sputtering target according to claim 7, wherein an atomic number ratio of each metal element to a total of the In, ga, zn and Sn satisfies
0.05≦In/（In+Ga+Zn+Sn）≦0.10
0.20≦Ga/（In+Ga+Zn+Sn）≦0.60
0.20≦Zn/（In+Ga+Zn+Sn）≦0.60
0.07≦Sn/（In+Ga+Zn+Sn）≦0.15。
9. An oxide semiconductor film having a first oxide semiconductor layer and a second oxide semiconductor layer,
The first oxide semiconductor layer and the second oxide semiconductor layer contain In, ga, zn, and Sn as metal elements, respectively, and O,
The atomic number ratio of each metal element In the first oxide semiconductor layer to the total of In, ga, zn and Sn is as follows
0.05≦In/（In+Ga+Zn+Sn）≦0.25
0.20≦Ga/（In+Ga+Zn+Sn）≦0.60
0.20≦Zn/（In+Ga+Zn+Sn）≦0.60
0.05≦Sn/（In+Ga+Zn+Sn）≦0.15，
The atomic number ratio of each metal element In the second oxide semiconductor layer to the total of In, ga, zn and Sn is as follows
0.20≦In/（In+Ga+Zn+Sn）≦0.60
0.05≦Ga/（In+Ga+Zn+Sn）≦0.25
0.15≦Zn/（In+Ga+Zn+Sn）≦0.60
0.01≦Sn/（In+Ga+Zn+Sn）≦0.20，
In the first oxide semiconductor layer, the atomic number ratio of In to the sum of In and Sn satisfies
0.30≦In/（In+Sn）≦0.60，
In the first oxide semiconductor layer, the atomic number ratio of Ga to the sum of Ga and Sn satisfies
0.75≦Ga/（Ga+Sn）≦0.99。
10. The oxide semiconductor thin film according to claim 9, wherein an atomic number ratio of each metal element In the first oxide semiconductor layer to a total of the In, ga, zn, and Sn satisfies
0.05≦In/（In+Ga+Zn+Sn）≦0.10
0.20≦Ga/（In+Ga+Zn+Sn）≦0.60
0.20≦Zn/（In+Ga+Zn+Sn）≦0.60
0.07≦Sn/（In+Ga+Zn+Sn）≦0.15。
11. A thin film transistor having a gate electrode, a gate insulating film, the oxide semiconductor thin film according to claim 9, source/drain electrodes, and a protective film in this order over a substrate.
12. The thin film transistor of claim 11, wherein the source/drain electrode comprises Cu or a Cu alloy.
13. A sputtering target for forming the first oxide semiconductor layer in the thin film transistor according to claim 11, and
The sputtering target contains In, ga, zn and Sn as metal elements, and O,
The atomic number ratio of each metal element to the total of In, ga, zn and Sn is as follows
0.05≦In/（In+Ga+Zn+Sn）≦0.25
0.20≦Ga/（In+Ga+Zn+Sn）≦0.60
0.20≦Zn/（In+Ga+Zn+Sn）≦0.60
0.05≦Sn/（In+Ga+Zn+Sn）≦0.15，
The atomic number ratio of In to the sum of In and Sn is as follows
0.30≦In/（In+Sn）≦（101/152），
The atomic number ratio of Ga to the sum of Ga and Sn is satisfied
0.75≦Ga/（Ga+Sn）≦0.99。
14. The sputtering target according to claim 13, wherein an atomic number ratio of each metal element to a total of the In, ga, zn, and Sn satisfies
0.05≦In/（In+Ga+Zn+Sn）≦0.10
0.20≦Ga/（In+Ga+Zn+Sn）≦0.60
0.20≦Zn/（In+Ga+Zn+Sn）≦0.60
0.07≦Sn/（In+Ga+Zn+Sn）≦0.15。
15. A sputtering target for forming the first oxide semiconductor layer in the thin film transistor according to claim 11, and
The sputtering target contains In, ga, zn and Sn as metal elements, and O,
The atomic number ratio of each metal element to the total of In, ga, zn and Sn is as follows
0.05≦In/（In+Ga+Zn+Sn）≦0.25
0.20≦Ga/（In+Ga+Zn+Sn）≦0.60
0.20≦Zn/（In+Ga+Zn+Sn）≦0.60
0.05≦Sn/（In+Ga+Zn+Sn）≦0.15，
The atomic number ratio of In to the sum of In and Sn is as follows
0.30≦In/（In+Sn）≦0.60，
The atomic number ratio of Ga to the sum of Ga and Sn is satisfied
0.75≦Ga/（Ga+Sn）≦0.99。
16. The sputtering target according to claim 15, wherein an atomic number ratio of each metal element to a total of the In, ga, zn, and Sn is as follows
0.05≦In/（In+Ga+Zn+Sn）≦0.10
0.20≦Ga/（In+Ga+Zn+Sn）≦0.60
0.20≦Zn/（In+Ga+Zn+Sn）≦0.60
0.07≦Sn/（In+Ga+Zn+Sn）≦0.15。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016035554A1 (en) * 2014-09-02 2016-03-10 株式会社神戸製鋼所 Oxide semiconductor thin film of thin film transistor, thin film transistor and sputtering target
CN105917450A (en) * 2014-01-15 2016-08-31 株式会社神户制钢所 Thin-film transistor
CN108987482A (en) * 2017-05-31 2018-12-11 乐金显示有限公司 Thin film transistor (TFT), including its gate drivers and including the display device of the gate drivers

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2246894B2 (en) 2004-03-12 2018-10-10 Japan Science and Technology Agency Method for fabricating a thin film transistor having an amorphous oxide as a channel layer
JP5244331B2 (en) * 2007-03-26 2013-07-24 出光興産株式会社 Amorphous oxide semiconductor thin film, manufacturing method thereof, thin film transistor manufacturing method, field effect transistor, light emitting device, display device, and sputtering target
JP5522889B2 (en) * 2007-05-11 2014-06-18 出光興産株式会社 In-Ga-Zn-Sn-based oxide sintered body and target for physical film formation
JP2010118407A (en) * 2008-11-11 2010-05-27 Idemitsu Kosan Co Ltd Thin-film transistor having etching resistance, and production method thereof
US8912537B2 (en) * 2010-04-23 2014-12-16 Hitachi, Ltd. Semiconductor device, RFID tag using the same and display device
JP6043244B2 (en) * 2012-06-06 2016-12-14 株式会社神戸製鋼所 Thin film transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105917450A (en) * 2014-01-15 2016-08-31 株式会社神户制钢所 Thin-film transistor
WO2016035554A1 (en) * 2014-09-02 2016-03-10 株式会社神戸製鋼所 Oxide semiconductor thin film of thin film transistor, thin film transistor and sputtering target
CN108987482A (en) * 2017-05-31 2018-12-11 乐金显示有限公司 Thin film transistor (TFT), including its gate drivers and including the display device of the gate drivers

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