JP2020161700A - Oxide semiconductor device and oxide semiconductor target - Google Patents

Abstract

To provide an oxide semiconductor device capable of ensuring a stable threshold potential by solving problems peculiar to a technology for achieving high mobility by a laminated structure.SOLUTION: An oxide semiconductor device has: a first channel layer, in contact with a source electrode but not in contact with a drain electrode; and a second channel layer, in contact with the drain electrode but not in contact with the source electrode. One end of the first channel layer is deviated by a predetermined shift amount from one end of the drain electrode.SELECTED DRAWING: Figure 2

Description

The present invention relates to oxide semiconductor devices and oxide semiconductor targets.

In a liquid crystal display using a thin film transistor as a pixel switch, a liquid crystal display in which amorphous silicon (amorphous silicon) is used for the channel layer of the thin film transistor (TFT) is the mainstream. However, as the display becomes finer at 4K and 8K, the pixel size has to be miniaturized, and of course, the thin film transistor is also miniaturized.

This means that the current value per unit area is increased, and the channel layer using amorphous silicon lacks on-characteristics (mobility and on-current), which makes it difficult to deal with it. On the other hand, low-temperature polysilicon (LTPS), which has excellent on-characteristics, is capable of sufficiently high definition. However, since process technology such as laser annealing is used, it is technically and costly difficult to manufacture a large screen, and a semiconductor material that realizes high on-characteristics and large area manufacturing corresponding to high definition is required. Therefore, in recent years, oxide semiconductor materials have been attracting attention as thin film semiconductor materials covering this region. In recent years, it has also been put into practical use as a thin film transistor for a backplane of an organic EL (electroluminescence) which is a self-luminous device and requires a large current drive.

Oxide semiconductors can be formed by a sputtering method, unlike amorphous silicon, which is formed by a chemical vapor deposition method (CVD). Therefore, the uniformity of the film is excellent, and it is possible to meet the demand for larger display size and higher definition. In addition, oxide semiconductors have better on-characteristics than amorphous silicon, and are advantageous for high brightness, high contrast, and high-speed driving. Furthermore, the leakage current when off is low, and power consumption reduction (power saving) can be expected. Further, the sputtering method can form a highly uniform film on a large area, and can form a film at a lower temperature than the chemical vapor deposition method. Therefore, there is an advantage that a material having low heat resistance can be selected as the material constituting the thin film transistor.

As an oxide semiconductor suitable for the channel layer of a TFT for a display, for example, indium gallium zinc composite oxide (hereinafter referred to as “IGZO”) and the like are known, and a semiconductor device using IGZO is also known (hereinafter referred to as “IGZO”). For example, see Patent Document 1).

IGZO has poor resistance to the electrode processing process and poor resistance to the protective film forming process. Therefore, it is difficult to manufacture at low cost because it is necessary to form an etch stop layer. On the other hand, oxide semiconductor materials having high resistance to electrode processing processes such as indium tin-zinc composite oxide (hereinafter referred to as ITZO) and zinc-tin composite oxide (hereinafter referred to as ZTO) have also been proposed. (See, for example, Patent Documents 2 and 3). In particular, ZTO is a promising oxide semiconductor material from the viewpoint of cost and sustainability because it does not use rare metals or elements with high industrial utilization rate.

Japanese Unexamined Patent Publication No. 2006-165532 JP-A-2008-243928 Japanese Unexamined Patent Publication No. 2012-03369

It is known that the following problems exist when trying to manufacture a liquid crystal display or an organic EL display by using a high mobility thin film transistor made of an oxide semiconductor material by using a conventional technique.

Generally, in an oxide semiconductor having high mobility characteristics, although high mobility is realized, it is difficult to control the threshold potential. In addition, it is easily affected by the process and the surrounding environment, and it becomes difficult to secure threshold potential stability. Therefore, it is practically impossible to stably use these as a pixel switch.

On the other hand, there is also a method of stacking oxide semiconductor layers having different mobilities to realize threshold potential control and high mobility. However, even if this method is used, a stable threshold potential can be secured up to a mobility of about 50 cm ² / Vs, and further technical improvement is required to realize an ultra-high mobility exceeding this.

The cause of the threshold potential fluctuation in this laminated TFT is considered to be the leakage current. Due to this leakage current, the current-voltage characteristic is observed as depleted. Such characteristics are extremely unsuitable as a pixel switch for a high-definition display or a driver for an OLED display. Therefore, there has been a demand for oxide semiconductor materials and device technologies capable of stable and ultra-high mobility operation by controlling threshold potential fluctuations to appropriate values.

The above-mentioned problem is a problem peculiar to an oxide semiconductor thin film transistor that realizes ultra-high mobility, particularly a technique for realizing high mobility by a laminated structure.
Patent Documents 1 to 3 do not mention the above-mentioned specific problem and the means for solving the above-mentioned specific problem.

An object of the present invention is to provide an oxide semiconductor device capable of securing a stable threshold potential by solving a problem peculiar to a technique for realizing high mobility by a laminated structure.

The oxide semiconductor device according to one aspect of the present invention includes a gate electrode, a first electrode provided on one end side of the gate electrode, a second electrode provided on the other end side of the gate electrode, and the above. It has a first channel layer that is in contact with the first electrode but not the second electrode, and at least a second channel layer that is in contact with the second electrode, and one end of the first channel layer is A predetermined shift amount is deviated from one end of the second electrode, the first channel layer is composed of an oxide semiconductor containing indium, and the second channel layer does not contain indium. It is characterized by being composed of an oxide semiconductor containing zinc and tin.

According to one aspect of the present invention, it is possible to solve a problem peculiar to a technique for realizing high mobility by a laminated structure and secure a stable threshold potential.

It is a figure explaining the cause of the threshold potential fluctuation in the related oxide semiconductor device (laminated TFT). It is a figure which shows the structure of the oxide semiconductor apparatus of Example 1. FIG. It is a figure which shows the structure of the oxide semiconductor apparatus of Example 2. It is a figure explaining the correlation between the Zn composition of a ZTO-based material and the etching property. It is a figure which shows the manufacturing method of the oxide semiconductor apparatus of Example 1. It is a figure which shows the manufacturing method of the oxide semiconductor apparatus of Example 1. It is a figure which shows the manufacturing method of the oxide semiconductor apparatus of Example 1. It is a figure which shows the manufacturing method of the oxide semiconductor apparatus of Example 2. It is a figure which shows the manufacturing method of the oxide semiconductor apparatus of Example 2. It is a figure which shows the structure of the oxide semiconductor apparatus of Example 3. It is a figure which shows the structure of the oxide semiconductor apparatus of Example 4. It is a figure which shows the structure of the oxide semiconductor apparatus of Example 5. It is a figure which shows the structure of the oxide semiconductor apparatus of Example 6. It is a schematic diagram which looked at the oxide semiconductor apparatus of Examples 1 to 6 from the upper surface. It is a figure explaining the current-voltage characteristic of IZO / ZTO (Zn composition 88%, Al 0.04 at% equivalent addition). It is a figure explaining the correlation of a channel layer shift amount and a threshold potential / mobility. It is a figure explaining the current-voltage characteristic of ITO / ZTO (Zn composition 92%, Ga8at% equivalent addition). It is a figure explaining the current-voltage characteristic of IZO / ITZO / ZTO (Zn composition 74%, W1at% equivalent addition).

First, an embodiment will be described with reference to the drawings.

The cause of the threshold potential fluctuation in the related oxide semiconductor device (laminated TFT) will be described with reference to FIG. In FIG. 1, the gate insulating film is omitted for convenience of explanation.

As shown in FIG. 1, the gate electrode 2 is provided in contact with the substrate 1. A first channel layer 3 is provided on the gate electrode 2. A second channel layer 4 is provided in contact with the first channel layer 3. A source electrode 5a is provided on one end side of the gate electrode 2. A drain electrode 5b is provided on the other end side of the gate electrode 2. Here, the second channel layer 4 is provided on the entire surface of the first channel layer 3. Here, the first channel layer 3 is an oxide semiconductor layer (containing In). The second channel layer 4 is an oxide semiconductor layer (ZTO system) containing no In.

In such a configuration, as shown by the arrow in FIG. 1, a leak current flows from the end of the laminated channel. As a result, the current-voltage characteristic is observed as depleted. Such characteristics are not suitable as a pixel switch for a high-definition display or a driver for an OLED display. Therefore, an oxide semiconductor device capable of controlling the threshold potential fluctuation to an appropriate value and capable of stable and ultra-high mobility operation is desired.

The above-mentioned problem is a problem peculiar to an oxide semiconductor thin film transistor that realizes ultra-high mobility, particularly a technique for realizing high mobility by a laminated structure. The embodiment solves this peculiar problem and secures a stable threshold potential.

In order to solve the above problems, the embodiment is a TFT having a laminated channel structure for achieving ultra-high mobility, for example, an oxide containing In such as IZO or ITO as the first channel layer in contact with the gate insulating film. A layer is used, and an In-free ZTO layer is used as the second channel layer laminated on the first channel layer.

In the conventional structure, the connection to the source / drain electrode is connected via the ZTO which is the second channel layer. In the embodiment, a structure is adopted in which the first channel layer and the second channel layer are shifted (channel shift structure) and connected to different ones of the source and drain electrodes. For example, when the first channel layer is connected to the source electrode, the second channel layer is connected to the drain electrode. When the first channel layer is connected to the drain electrode, the second channel layer is connected to the source electrode. When the number of laminated channels is three or more, the channel layer closest to the gate insulating film and the channel layer closest to the source / drain electrode are connected to different layers of the source electrode or the drain electrode. ..

By adopting the above structure, the leakage current from the end of the channel layer is suppressed, and the second channel layer is surely depleted. As a result, both high mobility and threshold potential control can be controlled, and high mobility exceeding 50 cm ² / Vs can be realized. Specifically, the first channel region and the second channel region (the bottom channel layer and the top channel layer in the case of a laminated structure of three or more layers) are set to a length of 10% to 75% of the thin film transistor gate length. A sufficient threshold potential control effect can be obtained by shifting in the gate length direction.

In the definition of the shift amount, paying attention to the channel layer structure overlapping with the gate electrode 12 in FIG. 2, the side closest to the first channel layer 13 or the gate electrode 12 with respect to the gate length (L _g ) 16. The shortness (L _s ) 17 of the channel layer is shown as a ratio, and the shift amount S = L _s / L _g × 100 (%). For example, the shift amount S is the amount of deviation between one end of the first channel layer 13 and one end of the drain electrode 15b.

The structure is the same for the second channel layer 14 or the channel layer closest to the source / drain electrodes 15a and 15b in a structure connected to both the source / drain electrodes 15a and 15b (see FIG. 3). The effect is obtained. Simply, the first channel layer 13 or the channel layer closest to the gate insulating film is directly connected to the source electrode 15a or the drain electrode 15b, and the length in the gate length direction is short. This is also easier on the top. Further, in the case of this structure, the IZO layer, which is vulnerable to the PAN-based etching solution, is not exposed on the surface and is protected by the ZTO-based material which is resistant to the PAN-based etching solution. Therefore, it is more effective to realize a low-cost process such as a channel etch structure.

However, in order to realize these structures, when the channel layer is processed with the oxalic acid-based etching solution, the second channel layer 14 is used rather than the high mobility oxide layer containing In, which is the first channel layer 13. The etching rate of a certain In-free ZTO-based oxide layer needs to be sufficiently high (see FIG. 4A). Otherwise, the first channel layer 12 will not be machined when the second channel layer 14 is machined, making it difficult to fabricate the channel shift structure itself.

On the other hand, when the source / drain electrodes 15a and 15b are subsequently processed with a PAN-based etching solution or the like, it is desirable that these channel layers remain unprocessed because a low-cost channel etching structure can be realized. Therefore, it is desirable that the selection ratio by PAN-based etching is at least 10 or more with respect to the electrode material (see FIG. 4B). From this point of view, the Zn composition of the ZTO-based material needs to be 74 to 92 at%, and the ZTO-based oxide material in this Zn composition range is applied.

As described above, in the embodiment, the leakage current is suppressed, and ultra-high mobility and good threshold potential control are realized by the laminated structure channel.
Hereinafter, examples will be described with reference to the drawings.

The structure of the oxide semiconductor device of the first embodiment will be described with reference to FIG. The oxide semiconductor device of Example 1 is a bottom gate top contact type. In FIG. 2, the gate insulating film is omitted for convenience of explanation.

As shown in FIG. 2, a gate electrode 12 is provided in contact with a substrate (for example, a non-alkali glass substrate) 11. A first channel layer 13 is provided on the gate electrode 12. A second channel layer 14 is provided in contact with the first channel layer 13. A source electrode 15a is provided on one end side of the gate electrode 12. A drain electrode 15b is provided on the other end side of the gate electrode 12. The first channel layer 13 is in contact with the source electrode 15a but not with the drain electrode 15b. The second channel layer 14 is in contact with the drain electrode 15b but not the source electrode 15a. The second channel layer 14 is in contact with a part of the first channel layer 13. One end of the first channel layer 13 is deviated from one end of the drain electrode 15b by a predetermined shift amount.

The first channel layer 13 is made of an oxide semiconductor (IZO-based material) containing indium. The film thickness of the first channel layer 13 is, for example, 5 nm. The second channel layer 14 does not contain indium and is composed of an oxide semiconductor (ZTO-based material) mainly composed of zinc and tin oxides. The film thickness of the second channel layer 114 is, for example, 15 nm.

Next, a method for manufacturing the oxide semiconductor device according to the first embodiment will be described with reference to FIGS. 5 to 7. Here, the gate electrode 12 in FIG. 2 corresponds to the gate electrode 21, the first channel layer 13 in FIG. 2 corresponds to the first channel layer 25, and the second channel layer 14 in FIG. 2 is the second. Corresponding to the channel layer 28, the source electrode 15a in FIG. 2 corresponds to the source electrode 31a, and the drain electrode 15a in FIG. 2 corresponds to the drain electrode 31b.

As shown in FIG. 5A, an electrode layer serving as a gate electrode, for example, a Mo layer or a MoW layer (thickness 100 nm) is formed on the substrate 20 by a DC magnetron sputtering method or the like. After that, a photoresist pattern is formed, and the gate electrode is processed using this as a mask to form the gate electrode pattern 21.

Next, as shown in FIG. 5B, the gate insulating film layer 22 is formed by a PE-CVD method or the like so as to cover the formed gate electrode pattern 21. Here, SiO _x (thickness 100 nm) is formed.

Then, as shown in FIG. 5 (c), the first oxide semiconductor layer 23 containing In, which is the first channel layer 25, is formed by the DC magnetron sputtering method. Here, an IZO layer (thickness 5 nm) is formed. At this time, a target material having a zinc composition of about 10 at% was used, and the film forming conditions were room temperature, a film forming pressure of 0.5 Pa, a sputter gas Ar / O ₂ mixed gas (oxygen addition ratio of about 25%), and a DC power of 50 W. Form a film. A phosphate pattern 24 for processing the first channel region is formed on the oxide layer 23.

Next, as shown in FIG. 5D, the first channel layer is processed using the photoresist pattern 24 as a mask. For processing, for example, an etching solution generally used for ITO processing such as an oxalic acid-based etching solution is used for patterning to form the first channel layer 25.

After that, as shown in FIG. 6A, a second oxide semiconductor layer (ZTO layer having a thickness of 25 nm) 26 to be a second channel layer 28 is first placed on the first channel layer 25. Oxide semiconductor layer 23
It is formed by the DC magnetron sputtering method in the same manner as in the above. Here, ZTO is also used target material zinc composition 88at% (Al amount 0.04At% equivalent), as the film formation conditions, ambient temperature, deposition pressure 0.5 Pa, sputtering gas Ar / _{O 2} mixed gas ( The film is formed with an oxygen addition ratio of about 30%) and a DC power of 50 W.
Next, as shown in FIG. 6B, the photoresist pattern 27 is formed.
Next, as shown in FIG. 6C, the ZTO layer 26 is processed using the photoresist pattern 27 as a mask. As with the first channel layer 25, an oxalic acid-based etching solution or the like is used for processing. The first channel layer 25 and the second channel layer 28 after processing are subjected to an activation annealing treatment for 1 hour under the condition of a temperature of 250 to 350 ° C.

Next, as shown in FIG. 7A, for example, a Mo / Al / Mo layer or a Mo or Mo alloy layer to be the SD electrode layer 29 is formed by magnetron DC sputtering or a vapor deposition method.
After that, as shown in FIG. 7B, the SD electrode layer 29 is further processed into the SD electrode pattern 31 with a PAN-based etching solution or the like using the photoresist pattern 30 as a mask.
After that, as shown in FIG. 7C, a protective film 32 such as SiN _x / SiO _{x is} formed by a PE-CVD method or the like for surface protection. In this way, the oxide semiconductor device of Example 1 (TFT made of an oxide semiconductor material) is completed.

The structure of the oxide semiconductor device of the second embodiment will be described with reference to FIG. The oxide semiconductor device of Example 2 is a bottom gate top contact type. In FIG. 3, the gate insulating film is omitted for convenience of explanation.

As shown in FIG. 3, the gate electrode 12 is provided in contact with the substrate 1. A first channel layer 13 is provided on the gate electrode 12. A second channel layer 14 is provided in contact with the first channel layer 13. A source electrode 15a is provided on one end side of the gate electrode 12. A drain electrode 15b is provided on the other end side of the gate electrode 12. The first channel layer 13 is in contact with the source electrode 15a but not with the drain electrode 15b. The second channel layer is in contact with both the source electrode 15a and the drain electrode 15b. The second channel layer 14 is in contact with all of the first channel layer 13. One end of the first channel layer 13 is deviated from one end of the drain electrode 15b by a predetermined shift amount.

The first channel layer 13 is made of an oxide semiconductor (IZO-based material) containing indium. The film thickness of the first channel layer 13 is, for example, 5 nm. The second channel layer 14 does not contain indium and is composed of an oxide semiconductor (ZTO-based material) mainly composed of zinc and tin oxides. The film thickness of the second channel layer 114 is, for example, 15 nm.

Next, a method for manufacturing the oxide semiconductor device of the second embodiment will be described with reference to FIGS. 8 and 9. Here, since the steps from FIGS. 5A to 5D are the same, the description thereof will be omitted. Here, the gate electrode 12 in FIG. 3 corresponds to the gate electrode 21, the first channel layer 13 in FIG. 3 corresponds to the first channel layer 25, and the second channel layer 14 in FIG. 3 corresponds to the second. Corresponding to the channel layer 28, the source electrode 15a in FIG. 3 corresponds to the source electrode 31a, and the drain electrode 15a in FIG. 3 corresponds to the drain electrode 31b.

As shown in FIG. 8A, a second oxide semiconductor layer (ZTO layer having a thickness of 25 nm) 26 to be a second channel layer 28 is placed on the first channel layer 25 as a first oxide. Like the semiconductor layer 23, it is formed by the DC magnetron sputtering method. Here, ZTO is also used target material zinc composition 88at% (Al amount 0.04At% equivalent), as the film formation conditions, ambient temperature, deposition pressure 0.5 Pa, sputtering gas Ar / _{O 2} mixed gas ( The film is formed with an oxygen addition ratio of about 30%) and a DC power of 50 W.
Next, as shown in FIG. 8B, the photoresist pattern 27 is formed. Here, as the photoresist pattern 27 of Example 2, a pattern larger than the photoresist pattern 27 of Example 1 is used.
Next, as shown in FIG. 8C, the ZTO layer 26 is processed using the photoresist pattern 27 as a mask. As with the first channel layer 25, an oxalic acid-based etching solution or the like is used for processing. The first channel layer 25 and the second channel layer 28 after processing are subjected to an activation annealing treatment for 1 hour under the condition of a temperature of 250 to 350 ° C.

Next, as shown in FIG. 9A, for example, a Mo / Al / Mo layer or a Mo or Mo alloy layer to be the SD electrode layer 29 is formed by magnetron DC sputtering or a vapor deposition method.
Next, as shown in FIG. 9B, the SD electrode layer 29 is further processed into the SD electrode pattern 31 with a PAN-based etching solution or the like using the photoresist pattern 30 as a mask.
After that, as shown in FIG. 9C, a protective film 32 such as SiN _x / SiO _{x is} formed by a PE-CVD method or the like for surface protection. In this way, the oxide semiconductor device of Example 2 (TFT made of an oxide semiconductor material) is completed.

The structure of the oxide semiconductor device of the third embodiment will be described with reference to FIG. The oxide semiconductor device of Example 3 is a bottom gate top contact type. Example 3 shows an example of a laminated channel structure in the case of three layers.

As shown in FIG. 10, the gate electrode 21 is provided in contact with the substrate. A gate insulating film 22 is provided in contact with the gate electrode 21. The first channel layer 25-1 is provided in contact with the gate insulating film 22. A third channel layer 25-2 is provided in contact with the first channel layer 25-1. A second channel layer 28 is provided in contact with the third channel layer 25-2. As described above, the third channel layer 25-2 is provided between the first channel layer 25-1 and the second channel layer 28.

A source electrode 31a is provided on one end side of the gate electrode 21. A drain electrode 31b is provided on the other end side of the gate electrode 21. The first channel layer 25-1 is in contact with the source electrode 31a but not the drain electrode 31b. The second channel layer 28 is in contact with the drain electrode 31b but not the source electrode. The third channel layer 25-2 is in contact with the source electrode 31a but not the drain electrode 31b. The second channel layer 28 is in contact with a part of the third channel layer. One end of the first channel layer 25-1 is deviated from one end of the drain electrode 31b by a predetermined shift amount. One end of the third channel layer 25-2 is deviated from one end of the drain electrode 31b by a predetermined shift amount.

The first channel layer 25-1 and the third channel layer 25-2 are made of an oxide semiconductor (IZO-based material) containing indium. The second channel layer 28 does not contain indium and is composed of an oxide semiconductor (ZTO-based material) mainly composed of zinc and tin oxides.

Example 3 shows an example of a laminated channel structure in the case of three layers, and in the case of further layers, it is only necessary to increase the configurations of the channel layers on the source electrode and drain electrode sides in the same manner. As long as the structure of the contact portion is the same, the effect can be obtained without any problem.

The structure of the oxide semiconductor device of the fourth embodiment will be described with reference to FIG. The oxide semiconductor device of Example 4 is a bottom gate top contact type. Example 4 shows an example of a laminated channel structure in the case of three layers.

As shown in FIG. 11, the gate electrode 21 is provided in contact with the substrate. A gate insulating film 22 is provided in contact with the gate electrode 21. The first channel layer 25-1 is provided in contact with the gate insulating film 22. A third channel layer 25-2 is provided in contact with the first channel layer 25-1. A second channel layer 28 is provided in contact with the third channel layer 25-2. As described above, the third channel layer 25-2 is provided between the first channel layer 25-1 and the second channel layer 28.

A source electrode 31a is provided on one end side of the gate electrode 21. A drain electrode 31b is provided on the other end side of the gate electrode 21. The first channel layer 25-1 is in contact with the source electrode 31a but not the drain electrode 31b. The second channel layer 28 is in contact with both the source electrode 31a and the drain electrode 31b. The third channel layer 25-2 is in contact with the source electrode 31a but not the drain electrode 31b. The second channel layer 28 is in contact with all of the third channel layer 25-2. One end of the first channel layer 25-1 is deviated from one end of the drain electrode 31b by a predetermined shift amount. One end of the third channel layer 25-2 is deviated from one end of the drain electrode 31b by a predetermined shift amount.

The first channel layer 25-1 and the third channel layer 25-2 are made of an oxide semiconductor (IZO-based material) containing indium. The second channel layer 28 does not contain indium and is composed of an oxide semiconductor (ZTO-based material) mainly composed of zinc and tin oxides.

Example 4 shows an example of a laminated channel structure in the case of three layers, and in the case of further layers, it is only necessary to increase the configurations of the channel layers on the source electrode and drain electrode sides in the same manner. As long as the structure of the contact portion is the same, the effect can be obtained without any problem.

The structure of the oxide semiconductor device of the fifth embodiment will be described with reference to FIG. The oxide semiconductor device of Example 5 is a top gate type.

As shown in FIG. 12, the first channel layer 25 is provided in contact with the substrate. A second channel layer 28 is provided in contact with the first channel layer 25. A gate insulating film 22 is provided in contact with the second channel layer 28. The gate electrode 21 is provided in contact with the gate insulating film 22. A source electrode 31a is provided on one end side of the gate electrode 21. A drain electrode 31b is provided on the other end side of the gate electrode 21. The first channel layer 25 is in contact with the source electrode but not the drain electrode 31b. The second channel layer 28 is in contact with the drain electrode 31b but not the source electrode 31a. The second channel layer 28 is in contact with a part of the first channel layer 25. One end of the first channel layer 25 is deviated from one end of the drain electrode 31b by a predetermined shift amount.
The first channel layer 25 is made of an oxide semiconductor containing indium. The second channel layer 28 does not contain indium and is composed of an oxide semiconductor mainly composed of oxides of zinc and tin.

The structure of the oxide semiconductor device of the sixth embodiment will be described with reference to FIG. The oxide semiconductor device of Example 6 is a top gate type.

As shown in FIG. 13, the first channel layer 25 is provided in contact with the substrate. A second channel layer 28 is provided in contact with the first channel layer 25. A gate insulating film 22 is provided in contact with the second channel layer 28. The gate electrode 21 is provided in contact with the gate insulating film 22. A source electrode 31a is provided at one end of the gate electrode 21. A drain electrode 31b is provided at the other end of the gate electrode 21. The first channel layer 25 is in contact with the source electrode 31a but not the drain electrode 31b. The second channel layer 28 is in contact with both the source electrode 31a and the drain electrode 31b. The second channel layer 28 is in contact with all of the first channel layer 25. One end of the first channel layer 25 is deviated from one end of the drain electrode 31b by a predetermined shift amount.

The first channel layer 25 is made of an oxide semiconductor containing indium. The second channel layer 28 does not contain indium and is composed of an oxide semiconductor mainly composed of oxides of zinc and tin.

FIG. 14 is a schematic view of the oxide semiconductor device (TFT) of Examples 1 to 6 as viewed from above.
Oxide semiconductor devices (TFTs) are used for controlling pixel electrodes in displays and the like. FIG. 14 shows an outline of the positional relationship between the thin film transistor 40, the gate line 41, the data line 42, and the pixel electrode 43. In the case of a display, this will be continuously formed in an array.

FIG. 15 is a graph showing the electrical characteristics of the thin film transistor (L / W = 2 μm / 100 μm).

The graph of the current-voltage characteristic shows the data of V _d = 0.1V, 1V, and 10V from the top. (A) shows the result of not shifting the channel layer, and (b) shows the result of shifting the channel layer by 1 μm with respect to the gate length of 2 μm.

In (a), the current-voltage characteristic has a Hamp shape, which is the result of depleting about 20 V. This is due to a current leak from the end of the channel layer, and indicates a situation in which the carriers in the channel layer are not completely controlled by the gate electrode.

On the other hand, in (b) where the channel layer was shifted, good current-voltage characteristics were exhibited, the mobility was 64.7 cm ² / Vs, and the threshold potential was 0.5 V. In the thin film transistor (b), the positive bias stress test and the negative bias test under light irradiation, which show the reliability of the thin film transistor, also showed good results of 0.4 V and -2.4 V, respectively (V _g = ± 15 V). , Light irradiation conditions W-LED 1000lp, 1000s).

In this method, the IZO layer, which is the first channel layer 25, and the ZTO-based semiconductor layer, which is the second channel layer 28, are arranged in a shifted manner, and the first channel layer 25 is connected only to the source electrode 31a. This is because by connecting both the source electrode 31a and the drain electrode 31b to the second channel layer 28, the depletion in the second channel layer 28 effectively acts and the threshold potential control becomes an appropriate state.

FIG. 16 is a graph showing the relationship between the channel layer shift amount, the threshold potential, and the mobility in the thin film transistor.

From FIG. 16, it can be seen that a shift amount of 10% to 75% with respect to the gate length is effective as the shift amount of the channel layer. It should be noted that when the shift amount is 80% or more, the depletion of the threshold potential and the deterioration of the mobility are observed. Is thought to be dominant.

In the same manner, ITO (5 nm) was used as the first channel layer 25, and ZTO (Zn composition 0.92, equivalent to 8 at% of Ga added) was used as the second channel layer 28, and the center wavelength was 254 nm as the annealing treatment. FIG. 17 shows the characteristics of a thin film transistor subjected to UV annealing treatment at 200 ° C. for 1 hour under an irradiation energy of 100 mW / cm ^{2 with} a mercury lamp of.

In this thin film transistor, the ITO layer, which is the first channel layer 25, and the ZTO-based semiconductor layer, which is the second channel layer 28, have a shift amount of 1 μm with respect to a gate length of 3 μm. Further, ITO, which is the first channel layer 25, is connected to the source electrode 31a, and the ZTO-based oxide semiconductor layer, which is the second channel layer 28, is connected to the drain electrode 31b. The current-voltage characteristics of the thin-film transistors that are simply laminated without shifting the channel layer are depleted by about -10V (see FIG. 17A). On the other hand, the thin film transistor having the structure of the present invention showed good characteristics with a mobility of 65.8 cm ² / Vs and a threshold potential of 0.03 V (see FIG. 17 (b)).

Reliability positive bias stress test showing a thin film transistor, each also results in under light irradiation negative bias test became 0.3V, -3.3 V and a good result _{(V g} = ± 15V, illumination condition W-LED 1000 lp, 1000 s).

Further, IZO (5 nm) as the first channel layer 25-1, ITZO (5 nm) as the second channel layer 28 superimposed on it, and ZTO as the third channel layer 25-2 arranged shifted from these two layers. FIG. 18 shows the characteristics of a thin film transistor subjected to annealing treatment in the air at 200 ° C. for 1 hour using a system (Zn composition 0.74, equivalent to 1 at% W addition amount).

The source electrode 31a is connected to the first channel layer 25-1 and the third channel layer 25-2, and the second channel layer 28 is connected to both the source electrode 31a and the drain electrode 31b. The mobility was 79.4 cm ² / Vs, and the threshold potential was 0.02 V, showing good current-voltage characteristics.

Regarding the additive materials such as Al, Ga, and W shown here, aluminum is 0.016 at% to 7 at%, gallium is 4.5 at% to 23 at%, and tungsten is 0.07 at% to 3.8 at%, respectively. If it is within the addition range of, a similarly good effect can be obtained.

Further, in the oxide semiconductor device of the above embodiment, the oxide semiconductor containing indium in the first channel layer 25 is an indium-tin composite oxide, an indium-zinc composite oxide, or an indium-tin-zinc composite oxide. Consists of.

Further, in the oxide semiconductor device of the above embodiment, the oxide semiconductor containing zinc and tin in the second channel layer 28 is zinc / (zinc +) when the total of zinc and tin is 1 in atomic ratio. The ratio of tin) is 0.74 or more and 0.92 or less. At this time, when the oxide semiconductor target used when forming the second channel layer 28 of the oxide semiconductor device by sputtering contains zinc and tin oxides, and the total of zinc and tin is 1 in atomic ratio. In addition, the zinc / (zinc + tin) ratio is 0.74 or more and 0.92 or less.

Further, in the oxide semiconductor device of the above embodiment, the oxide semiconductor containing zinc and tin in the second channel layer 28 contains one or more elements selected from aluminum, gallium, and tungsten, and aluminum: 0. It is composed of a zinc-tin composite oxide mixed at a concentration of .016 at% to 7 at%, gallium: 4.5 at% to 23 at%, and tungsten: 0.07 at% to 3.8 at%. At this time, the oxide semiconductor target used when forming the second channel layer 28 of the oxide semiconductor device by sputtering contains one or more elements selected from aluminum, gallium, and tungsten, and aluminum: 0.016 at. It contains a zinc-tin composite oxide mixed at a concentration of% to 7 at%, gallium: 4.5 at% to 23 at%, and tungsten: 0.07 at% to 3.8 at%.

As a matter of course, the film thickness of the channel layer and the electrode layer, the film forming method, the processing (etching) method, and the like shown in the above examples can be variously changed according to the characteristics required for the device to be manufactured.

Further, in the above embodiment, the DC magnetron sputtering method was used as a typical film forming method, but various film forming methods such as conventional RF, DC sputtering, RF magnetron sputtering, ECR sputtering, ion plating, and reactive vapor deposition method. The same effect can be expected with.
The oxide semiconductor target for forming the oxide semiconductor layer of the present embodiment is, for example, ZnO powder, SnO ₂ powder, Al ₂ O ₃ powder, Ga ₂ O ₃ powder, W ₂ O ₃ powder, WO. ₂ powders and WO ₃ powders are mixed so as to have the above-mentioned composition, and the sintered body obtained by firing the cast-formed molded body at atmospheric pressure is obtained by machining such as cutting and polishing. be able to.

1 Substrate 2 Gate electrode 3 First channel layer 4 Second channel layer 5a Source electrode 5b Drain electrode 11 Substrate 12 Gate electrode 13 First channel layer 14 Second channel layer 15a Source electrode 15b Drain electrode 16 Gate length 17 Shift length 20 Substrate 21 Gate electrode 22 Gate insulating film 23 First oxide semiconductor layer 24 Photoresist 25 First channel layer 26 Second oxide semiconductor layer 27 Photoresist 28 Second channel layer 29 Source / drain electrode layer 30 Photoresist 31a Source electrode 31b Drain electrode 32 Protective film layer 40 Thin film 41 Gate wire 42 Data line 43 Pixel electrode (transparent electrode)

Claims (15)

With the gate electrode
The first electrode provided on one end side of the gate electrode and
A second electrode provided on the other end side of the gate electrode and
A first channel layer that is in contact with the first electrode but not the second electrode,
At least a second channel layer in contact with the second electrode,
Have,
One end of the first channel layer is deviated by a predetermined shift amount from one end of the second electrode.
The first channel layer is composed of an oxide semiconductor containing indium.
The second channel layer is an oxide semiconductor apparatus characterized in that it is composed of an oxide semiconductor containing zinc and tin without containing indium. The oxide semiconductor device according to claim 1, wherein the second channel layer is in contact with both the first electrode and the second electrode. Further having a gate insulating film in contact with the gate electrode,
The oxide semiconductor device according to claim 1, wherein the first electrode and the second electrode form a source electrode or a drain electrode. The first electrode constitutes the source electrode and
The second electrode constitutes the drain electrode and
The first channel layer is in contact with the source electrode and a part of the gate insulating film.
The oxide semiconductor device according to claim 3, wherein the second channel layer is in contact with the drain electrode and a part of the first channel layer. The first electrode constitutes the source electrode and
The second electrode constitutes the drain electrode and
The first channel layer is in contact with the source electrode.
The oxide semiconductor device according to claim 3, wherein the second channel layer is in contact with both the source electrode and the drain electrode and is in contact with all of the first channel layer. With the first channel layer
With the second channel layer
At least with the third channel layer,
The oxide semiconductor device according to claim 1, wherein the oxide semiconductor device has. The third channel layer is
It is provided between the first channel layer and the second channel layer so as to be in contact with the first electrode but not to the second electrode.
The oxide semiconductor device according to claim 6, wherein one end of the third channel layer is deviated from the one end of the front second electrode by the shift amount. The gate electrode is arranged so as to be in contact with the substrate.
The oxide semiconductor apparatus according to claim 1, wherein the first channel layer and the second channel layer are arranged on the gate electrode. The first channel layer is arranged so as to be in contact with the substrate.
The oxide semiconductor apparatus according to claim 1, wherein the gate electrode is arranged on the first channel layer and the second channel layer. The shift amount is defined as the ratio of the shift length (L _s ) from the one end of the second electrode to the gate length (L _g ) of the gate electrode, and the shift amount S = L _s / L _g × 100 (%). The oxide semiconductor device according to claim 1, wherein the shift amount S is 10% to 75% when expressed as. The oxide semiconductor containing the indium in the first channel layer is composed of an indium-tin composite oxide, an indium-zinc composite oxide, or an indium-tin-zinc composite oxide. Item 2. The oxide semiconductor device according to Item 1. The oxide semiconductor containing zinc and tin in the second channel layer has a zinc / (zinc + tin) ratio of 0.74 or more when the total of zinc and tin is 1 in atomic ratio. The oxide semiconductor apparatus according to claim 1, wherein the amount is 92 or less. The oxide semiconductor containing zinc and tin in the second channel layer contains one or more elements selected from aluminum, gallium, and tungsten, and has aluminum: 0.016 at% to 7 at%, gallium: 4. The oxide semiconductor device according to claim 1, wherein the oxide semiconductor device is composed of a zinc-tin composite oxide containing 5 at% to 23 at% and tungsten: 0.07 at% to 3.8 at%. An oxide semiconductor target used when forming the second channel layer of the oxide semiconductor device according to claim 12 by sputtering.
Does not contain indium but contains zinc and tin oxides
An oxide semiconductor target characterized in that the ratio of zinc / (zinc + tin) is 0.74 or more and 0.92 or less when the total of zinc and tin is 1 in atomic ratio. An oxide semiconductor target used when forming the second channel layer of the oxide semiconductor device according to claim 13 by sputtering.
Contains one or more elements selected from aluminum, gallium, and tungsten, in the range of aluminum: 0.016 at% to 7 at%, gallium: 4.5 at% to 23 at%, and tungsten: 0.07 at% to 3.8 at%. An oxide semiconductor target comprising a zinc-tin composite oxide contained therein.

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