CN113345870A - 半导体设备封装和其制造方法 - Google Patents

半导体设备封装和其制造方法 Download PDF

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CN113345870A
CN113345870A CN202011335134.0A CN202011335134A CN113345870A CN 113345870 A CN113345870 A CN 113345870A CN 202011335134 A CN202011335134 A CN 202011335134A CN 113345870 A CN113345870 A CN 113345870A
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substrate
antenna
semiconductor device
disposed
device package
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郑宏祥
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本公开提供了一种半导体设备封装。所述半导体设备封装包含：第一衬底，所述第一衬底具有第一表面和与所述第一表面相对的第二表面；天线模块，所述天线模块安置在所述第一衬底的所述第一表面上；电子组件模块，所述电子组件模块安置在所述第一衬底的所述第一表面上；以及第一封装体，所述第一封装体包封所述天线模块和所述电子组件模块。所述天线模块具有面对所述第一衬底的所述第一表面的第一表面、与所述天线模块的所述第一表面相对的第二表面以及在所述天线模块的所述第一表面与所述天线模块的所述第二表面之间延伸的侧面。所述天线模块的所述侧面面对所述电子组件模块。还提供了一种制备半导体设备封装的方法。

Description

半导体设备封装和其制造方法
技术领域
本公开总体上涉及一种半导体设备封装和其制造方法，并且涉及一种包含天线的半导体设备封装。
背景技术
在具有天线层和射频(RF)路由层的半导体设备封装中，RF路由层通常厚到足以保持整个封装的对称性。然而，随着RF路由层的介电层的数量增加，成品率将降低。另外，天线层的铜铺设率通常低于RF路由层的铜铺设率，并且铜铺设率失配致使加工困难。
发明内容
在一或多个实施例中，一种半导体设备封装包含：第一衬底，所述第一衬底具有第一表面和与所述第一表面相对的第二表面；天线模块，所述天线模块安置在所述第一衬底的所述第一表面上；电子组件模块，所述电子组件模块安置在所述第一衬底的所述第一表面上；以及第一封装体，所述第一封装体包封所述天线模块和所述电子组件模块。所述天线模块具有面对所述第一衬底的所述第一表面的第一表面、与所述天线模块的所述第一表面相对的第二表面以及在所述天线模块的所述第一表面与所述天线模块的所述第二表面之间延伸的侧面。所述天线模块的所述侧面面对所述电子组件模块。
在一或多个实施例中，一种半导体设备封装包含：第一衬底，所述第一衬底具有第一表面和与所述第一表面相对的第二表面；电子组件模块，所述电子组件模块安置在所述第一衬底的所述第一表面上；以及天线模块，所述天线模块安置在所述第一衬底的所述第一表面上并且与所述电子组件模块并排安置。所述天线模块包含第一天线层。所述半导体设备封装进一步包含：封装体，所述封装体包封所述天线模块；以及第二天线层，所述第二天线层安置在所述封装体上并且与所述第一天线层基本上对齐。
在一或多个实施例中，一种制造半导体设备封装的方法包含提供载体并且将天线模块安置在所述载体上。所述天线模块具有天线图案和与所述天线图案连接的馈线。所述方法进一步包含去除所述载体以使所述馈线的一部分暴露。所述方法进一步包含：在去除所述载体之后，形成对应于所述天线图案的接地层。
附图说明
当与附图一起阅读以下详细描述时，可以根据以下详细描述容易地理解本公开的各方面。应当注意的是，各种特征可能不一定按比例绘制。为了讨论的清楚起见，可以任意增大或减小各种特征的尺寸。
图1展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图2展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图3展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图4展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图5A展示了根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图5B展示了根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图5C展示了根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图5D展示了根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图6A展示了根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图6B展示了根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图6C展示了根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
图6D展示了根据本公开的一些实施例的制造半导体设备封装的方法的一或多个阶段。
贯穿附图和详细描述，使用了共同的附图标记来指示相同或类似的元件。根据以下结合附图进行的详细描述，本公开将更加明显。
具体实施方式
以下公开提供了用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述了组件和布置的具体实例。当然，这些仅仅是实例并且不旨在是限制性的。在本公开中，对在第二特征之上或上形成第一特征的引用可以包含将第一特征和第二特征被形成为直接接触的实施例，并且还可以包含可以在第一特征与第二特征之间形成另外的特征使得第一特征和第二特征可以不直接接触的实施例。此外，本公开可以在各个实例中重复附图标记和/或字母。这种重复是为了简单和清晰起见并且本身并不指示所讨论的各个实施例和/或配置之间的关系。
下文详细讨论了本公开的实施例。然而，应当理解的是，本公开提供了许多可以在各种各样的特定上下文中具体化的适用概念。所讨论的具体实施例仅是说明性的，而不限制本公开的范围。
图1展示了根据本公开的一些实施例的半导体设备封装1的横截面视图。半导体设备封装1包含衬底10、天线模块11、天线图案12和13、电子组件模块14、封装体15和电触点16。
衬底10具有表面101和与表面101相对的表面102。衬底10可以为例如印刷电路板，如纸基铜箔层压板、复合铜箔层压板或聚合物浸渍的玻璃纤维基铜箔层压板。衬底10可以包含互连结构，如重新分布层(RDL)10r。RDL 10r可以被介电层覆盖，并且从表面101和表面102部分地暴露。
如图1所示，衬底10可以包含安置在衬底10内的接地层10g。接地层10g安置在天线模块11的外部。在一些实施例中，接地层10g可以形成为对应于天线图案12和/或天线图案13。在一些实施例中，接地层10g可以与天线图案12和/或天线图案13对齐。
在一些实施例中，接地层10g可以安置在天线模块11内。例如，接地层10g可以安置在天线模块11的介电层(例如，一组一或多个介电层11d2中的介电层)中。在此类实施例中，需要添加另一介电层(例如，一组一或多个介电层11d1中的介电层)，以保持天线模块11的对称性。通过将接地层10g安置在天线模块11的外部，可以进一步减少天线模块11的介电层的数量，并且可以减少铜铺设率失配。因此，可以提高成品率。
天线模块11安置在衬底10的表面101上。天线模块11具有背离衬底10的表面111、与表面111相对的表面112以及在表面111与表面112之间延伸的侧面113。
天线模块11的侧面113面对电子组件模块14。换句话说，天线模块11和电子组件模块14并排放置在衬底10上。
天线模块11包含衬底11b、一组一或多个介电层11d1、一组一或多个介电层11d2、导电材料和/或结构以及天线图案12和13。导电材料和/或结构可以包含多条迹线。例如，导电材料和/或结构可以包含馈线11c。
衬底11b具有背离衬底10的表面11b1和与表面11b1相对的表面11b2。所述一组一或多个介电层11d1安置在表面11b1上，并且所述一组一或多个介电层11d2安置在表面11b2上。
所述一组一或多个介电层11d1中的一或多个层的数量和所述一组一或多个介电层11d2中的一或多个层的数量是大于零的整数。在一些实施例中，所述一组一或多个介电层11d1中的一或多个层的数量和所述一组一或多个介电层11d2中的一或多个层的数量可以相同。例如，衬底11b的表面11b1上可以具有4个介电层，并且衬底11b的表面11b2上可以具有4个介电层。例如，衬底11b的表面11b1上可以具有3个介电层，并且衬底11b的表面11b2上可以具有3个介电层。
在一些实施例中，所述一组一或多个介电层11d1的厚度和所述一组一或多个介电层11d2的厚度可以基本上相同。在一些实施例中，在天线模块11的制造工艺中，设置衬底11b，并且然后在衬底11b的相对侧上分别设置所述一组一或多个介电层11d1和所述一组一或多个介电层11d2，以保持天线模块11的对称性。所述一组一或多个介电层11d1和所述一组一或多个介电层11d2的厚度相同可以平衡从一或多个介电层引入的应力并且帮助减轻翘曲。
在一些实施例中，所述一组一或多个介电层11d1和所述一组一或多个介电层11d2中的每一个介电层可以包含但不限于有机材料、阻焊层、聚酰亚胺(PI)、味之素增层膜(ABF)、一或多种模制原料、一或多种预浸渍复合纤维(例如，预浸料)、硼磷硅酸盐玻璃(BPSG)、氧化硅、氮化硅、氮氧化硅、未掺杂硅酸盐玻璃(USG)、其任意组合等。模制原料的实例可以包含但不限于包含分散在其中的填料的环氧树脂。预浸料的实例可以包含但不限于通过堆叠或层压多种预浸渍材料或片材而形成的多层结构。在一些实施例中，所述一组一或多个介电层11d1和所述一组一或多个介电层11d2中的每一个介电层可以包含无机材料，如氧化硅(SiOx)、氮化硅(SiNx)、氧化钽(TaOx)等。在一些实施例中，衬底11b可以具有如上针对所述一组一或多个介电层11d1和所述一组一或多个介电层11d2所列的材料。
天线图案12安置在所述一组一或多个介电层11d1中的至少一个介电层内。例如，天线图案12安置在衬底11b上。例如，天线图案12被所述一组一或多个介电层11d1包封。
天线图案13安置在所述一组一或多个介电层11d1上。天线图案13的侧面可以被保护层13p覆盖或与所述保护层接触。天线图案13可以嵌入在保护层13p内。在一些实施例中，保护层13p可以包含阻焊剂或阻焊层。
天线图案12与天线图案13对齐。在实施例中，可以在天线图案12与天线图案13之间通过耦接传输信号。天线图案12和天线图案13可以是贴片天线。在一些实施例中，天线图案12和13中的每一个天线图案可以包含如金属或金属合金等导电材料。导电材料的实例包含金(Au)、银(Ag)、铝(Al)、铜(Cu)或其合金。在一些实施例中，天线图案12和天线图案13也可以被称为天线层。
在一些实施例中，天线模块11可以仅包含天线图案12，并且可以省略天线图案13。在一些实施例中，与仅具有天线图案12的实施例相比，具有天线图案12和天线图案13的实施例可以实现更高频率的无线传输。
天线图案12通过例如但不限于馈线11c电连接到衬底10(如衬底10的RDL 10r)。在一些实施例中，天线图案12通过例如但不限于馈线11c电连接到电子组件模块14。在一些实施例中，馈线11c可以向天线图案12提供信号。例如，可以在RDL 10r、馈线11c与天线图案12之间传输信号。馈线11c安置在衬底10与天线图案12之间。馈线11c安置在所述一组一或多个介电层11d2内。馈线11c被所述一组一或多个介电层11d2包围。馈线11c穿过所述一组一或多个介电层11d2。
在一些实施例中，衬底10与天线图案12之间通过馈线11c的信号传输路径可以基本上垂直于衬底10的表面101。
在一些实施例中，馈线11c可以包含但不限于金属柱、键合线或堆叠式通孔。在一些实施例中，馈线11c可以包含Au、Ag、Al、Cu或其合金。
电子组件模块14安置在衬底10的表面101上。如所提及的，电子组件模块14和天线模块11并排安置。电子组件模块14和天线模块11定位在衬底10的不同区域处。电子组件模块14与天线模块11侧向间隔开。电子组件模块14与天线模块11侧向实体地隔离。
电子组件模块14包含衬底14s、电子组件14a和14b以及封装体14p。在一些实施例中，衬底14s是扇出型衬底。衬底14s包含互连层14r。在一些实施例中，互连层14r可以包含扇出型结构。在一些实施例中，互连层14r可以用作用于传输信号的RF路由层。
电子组件14a和14b中的每一个电子组件可以通过互连层14r电连接到另一电气组件和衬底10(例如，连接到RDL 10r)中的一个或多个，并且电连接可以通过倒装芯片技术或引线键合技术来实现。封装体14p形成于衬底14s上，以包封电子组件14a和14b。
电子组件14a和14b中的每一个电子组件可以是包含半导体衬底、一或多个集成电路设备和其中的一或多个上覆的互连结构的芯片或管芯。集成电路设备可以包含如晶体管等有源设备和/或如电阻器、电容器、电感器或其组合等无源设备。在一些实施例中，电子组件14a和14b中的每一个电子组件可以是发射器、接收器或收发器。在一些实施例中，电子组件14a和14b中的每一个电子组件可以包含电源管理集成电路(PMIC)。虽然图1中存在两个电子组件，但是电子组件的数量不限于此。在一些实施例中，根据设计要求，电子组件模块14中可以存在任何数量的电子组件。
封装体15形成于衬底10上，以包封电子组件模块14和天线模块11。封装体15还包封电子组件模块14的封装体14p。在一些实施例中，可以观察到封装体15与封装体14p之间的界面。在一些实施例中，封装体15和封装体14p可以包含相同的材料，并且在封装体15与封装体14p之间不存在界面。
在一些实施例中，封装体15包含环氧树脂，所述环氧树脂具有填料、模制原料(例如，环氧树脂模制原料或其它模制原料)、聚酰亚胺、酚类原料或材料、具有分散在其中的硅酮的材料或其组合。在一些实施例中，封装体15的材料不同于所述一组一或多个介电层11d1和所述一组一或多个介电层11d2中的每一个介电层的材料。
电触点16(例如，焊球)安置在衬底10的表面102上，并且可以在半导体封装设备1与外部组件(例如外部电路或电路板)之间提供电连接。在一些实施例中，电触点16包含可控塌陷芯片连接(C4)凸点、球栅阵列(BGA)或平面网格阵列(LGA)。
在对比实施例中，电子组件模块14(连同衬底14s)可以与天线模块11堆叠。例如，电子组件模块14可以安置在天线模块11的表面112上，并且天线模块11利用用于连接到电子组件模块14的RF路由层封装。互连层14r可以与天线模块11的RF路由层的介电层堆叠。在这种堆叠式布置中，需要更多的介电层(与并排布置相比)来保持整个封装的对称性。然而，随着介电层的数量增加，成品率将降低。另外，在具有RF路由层的天线模块11中，天线层与RF路由层之间的铜铺设率失配通常致使加工困难。
通过分别形成电子组件模块14和天线模块11，并且然后将其并排放置在衬底10上，不需要在天线模块11中设置另外的介电层。可以减少介电层的数量，并且可以减少天线模块11的整个厚度，而不影响天线模块11的对称性。另外，通过去除天线模块11外部的RF路由层，可以减少铜铺设率失配。此外，电子组件模块14和天线模块11在安装在载体(如衬底10)上之前可以单独测试。因此，可以提高成品率。
图2展示了根据本公开的一些实施例的半导体设备封装2的横截面视图。图2的半导体设备封装2类似于图1的半导体设备封装1，并且以下描述了其间的差异。
在图2中，天线图案13安置在封装体15上。天线图案12与天线图案13对齐。在实施例中，可以在天线图案12与天线图案13之间通过耦接传输信号。
在一些实施例中，封装体15的材料不同于所述一组一或多个介电层11d1和所述一组一或多个介电层11d2中的每一个介电层的材料。因此，天线模块11的耦接媒体不同于用于支撑馈线11c的媒体。换句话说，衬底10与天线图案12之间的信号传输路径以及天线图案12与天线图案13之间的信号耦接采用不同的材料。
与图1中的半导体设备封装1相比，可以减少介电层的数量，并且因此可以提高成品率。
在一些实施例中，天线模块11可以仅包含天线图案12，并且可以省略天线图案13。在一些实施例中，与不具有天线图案13的实施例相比，具有天线图案12和天线图案13两者的实施例可以实现更高频率的无线传输。
图3展示了根据本公开的一些实施例的半导体设备封装3的横截面视图。图3的半导体设备封装3类似于图1的半导体设备封装1，并且以下描述了其间的差异。
在图3中，半导体设备封装3进一步包含安置在封装体15上的屏蔽层31。屏蔽层31可以用于为电子组件14a和14b提供电磁干扰(EMI)保护。
在一些实施例中，屏蔽层31是导电薄膜，并且可以包含例如Au、Ag、Al、Cu、铬(Cr)、锡(Sn)、镍(Ni)或不锈钢或其混合物、合金或其它组合。屏蔽层14可以包含单个导电层或多个导电层。在一些实施例中，屏蔽层31包含多个导电层，并且所述多个导电层可以包含相同的材料，或者所述多个导电层中的一个导电层可以包含不同的材料，或者所述多个导电层中的每一个导电层可以包含与所述多个导电层中的其它导电层不同的材料。
图4展示了根据本公开的一些实施例的半导体设备封装4的横截面视图。图4的半导体设备封装4类似于图1的半导体设备封装1，并且以下描述了其间的差异。
在图4中，半导体设备封装4进一步包含屏蔽层41，所述屏蔽层安置在封装体14p的外表面上并且覆盖封装体14p以及电气组件14a和14b。
图5A、图5B、图5C和5D是根据本公开的一些实施例的处于不同制造阶段的半导体设备封装的横截面视图。已经简化了这些附图中的至少一些附图，以便更好地理解本公开的方面。
参照图5A，通过粘性层51将天线模块11和电子组件模块14设置在载体50上。天线模块11具有背离载体50的表面111、与表面111相对的表面112以及在表面111与表面112之间延伸的侧面113。天线模块11的侧面113面对电子组件模块14。
天线模块11包含衬底11b、一组一或多个介电层11d1、一组一或多个介电层11d2、馈线11c。在所述一组一或多个介电层11d1中的至少一个介电层内安置有天线图案12。在所述一组一或多个介电层11d1上安置有天线图案13并且所述天线图案与天线图案12对齐。
电子组件模块14包含衬底14s、电子组件14a和14b以及封装体14p。衬底14s包含互连层14r。
参照图5B，在载体50上安置封装体15，以包封天线模块11和电子组件模块14。封装体15可以通过如传递模制或压缩模制等模制技术形成。
参照图5C，从封装体15去除载体50和粘性层51。馈线11c从天线模块11的表面112暴露。互连层14r从电子组件模块14的下表面暴露。天线模块11、电子组件模块14和封装体15翻转，如图5C所示。
参照图5D，在天线模块11和电子组件模块14上设置衬底10。衬底10设置在馈线11c和互连层14r上。衬底10具有电连接到馈线11c和互连层14r的RDL 10r。在一些实施例中，在去除载体50和粘性层51之后，在天线模块11和电子组件模块14上设置接地层10g。在一些实施例中，接地层10g被设置成对应于天线图案12和/或天线图案13。在一些实施例中，接地层10g与天线图案12和/或天线图案13对齐。可以在衬底10的表面102上设置电触点(如图1中的电触点16)。通过图5A、图5B、图5C和5D中所展示的操作制造的结构可以类似于图1中的半导体设备封装1。
在一些实施例中，由于RDL 10r和接地层10g在模制之后形成，因此如图5B中所展示的，RDL 10r和接地层10g通常可以是均匀的。例如，在图5D中，可以在不考虑天线模块11和电子组件模块14的重力的情况下形成RDL 10r和接地层10g。
图6A、图6B、图6C和6D是根据本公开的一些实施例的处于不同制造阶段的半导体设备封装的横截面视图。已经简化了这些附图中的至少一些附图，以便更好地理解本公开的方面。图6A、图6B、图6C和6D的操作类似于图5A、图5B、图5C和5D的操作，并且以下描述了其间的差异。
在图6A、图6B、图6C和6D的操作中，在如图6C中所展示的模制操作之前形成RDL10r和接地层10g。
参照图6A，通过粘性层51将包含RDL 10r和接地层10g的衬底10安置在载体50上。
参照图6B，将天线模块11和电子组件模块14设置在衬底10上。
参照图6C，在衬底10上安置封装体15，以包封天线模块11和电子组件模块14。
参照图6D，从衬底10去除载体50和粘性层51。可以在衬底10的表面102上设置电触点(如图1中的电触点16)。通过图6A、图6B、图6C和6D中所展示的操作制造的结构可以类似于图1中的半导体设备封装1。
在一些实施例中，由于RDL 10r和接地层10g是在如图6C中所展示的模制操作之前形成的，因此RDL 10r和接地层10g的光刻操作(如图6A中的操作)在需要时可以返工，而无需弃去天线模块11和电子组件模块14。因此，可以提高成品率。
在本文中可以为了便于描述而使用如“之下”、“下方”、“下部”、“上方”、“上部”、“左侧”、“右侧”等空间相对术语来描述如附图所示的一个元件或特征与另一或多个元件或特征的关系。除了在附图中描绘的朝向之外，空间相对术语还旨在涵盖设备在使用时或运行时的不同朝向。可以以其它方式朝向装置(旋转90度或处于其它朝向)，并且同样可以以相应的方式解释本文中使用的空间相对描述语。应理解，当元件被称为“连接到”或“耦接到”另一元件时，其可以直接连接到或耦接到另一元件，或者可以存在中间元件。
如本文所使用的，术语“大约”、“基本上”、“基本”和“约”用于描述和解释小的变化。当结合事件或情形使用时，所述术语可以指代事件或情形精确发生的实例以及事件或情形接近发生的实例。如本文关于给定值或范围所使用的，术语“约”总体上意指处于给定值或范围的±10％、±5％、±1％或±0.5％内。本文中可以将范围表示为一个端点到另一个端点或介于两个端点之间。本文公开的所有范围都包含端点，除非另外指明。术语“基本上共面”可以指两个表面沿同一平面定位的位置差处于数微米(μm)内，如沿同一平面定位的位置差处于10μm内、5μm内、1μm内或0.5μm内。当将数值或特性称为“基本上”相同时，所述术语可以指处于所述值的平均值的±10％、±5％、±1％或±0.5％内的值。
前述内容概述了几个实施例的特征和本公开的详细方面。本公开中描述的实施例可以容易地用作设计或修改其它工艺和结构以便于实施相同或类似目的和/或实现本文介绍的实施例的相同或类似优点的基础。此类等同构造不背离本公开的精神和范围，并且在不背离本公开的精神和范围的情况下，可以作出各种改变、替代和变更。

Claims (20)

1.一种半导体设备封装，其包括：
第一衬底，所述第一衬底具有第一表面和与所述第一表面相对的第二表面；
天线模块，所述天线模块安置在所述第一衬底的所述第一表面上，所述天线模块具有面对所述第一衬底的所述第一表面的第一表面、与所述天线模块的所述第一表面相对的第二表面以及在所述天线模块的所述第一表面与所述天线模块的所述第二表面之间延伸的侧面；
电子组件模块，所述电子组件模块安置在所述第一衬底的所述第一表面上，其中所述天线模块的所述侧面面对所述电子组件模块；以及
第一封装体，所述第一封装体包封所述天线模块和所述电子组件模块。
2.根据权利要求1所述的半导体设备封装，其中所述天线模块进一步包括：
第二衬底，所述第二衬底具有背离所述第一衬底的第一表面和与所述第一表面相对的第二表面；
第一组介电层，所述第一组介电层安置在所述第二衬底的所述第一表面上；以及
第一天线图案，所述第一天线图案安置在所述第一组介电层中的至少一个介电层内。
3.根据权利要求2所述的半导体设备封装，其中所述天线模块进一步包括：
第二组介电层，所述第二组介电层安置在所述第二衬底的所述第二表面上；以及
馈线，所述馈线安置在所述第二组介电层中的至少一个介电层内并且电连接到所述天线图案和所述第一衬底。
4.根据权利要求3所述的半导体设备封装，其中所述第一组介电层中的层的数量与所述第二组介电层中的层的数量相同。
5.根据权利要求3所述的半导体设备封装，其中所述第一组介电层的厚度与所述第二组介电层的厚度基本上相同。
6.根据权利要求2所述的半导体设备封装，其中所述天线模块进一步包含安置在所述第一组介电层上的第二天线图案，其中所述第二天线图案与所述第一天线图案基本上对齐。
7.根据权利要求2所述的半导体设备封装，其进一步包括第三天线图案，所述第三天线图案安置在所述第一封装体上，其中所述第三天线图案与所述第一天线图案基本上对齐。
8.根据权利要求2所述的半导体设备封装，其中所述第一组介电层的材料不同于所述第一封装体的材料。
9.根据权利要求1所述的半导体设备封装，其进一步包括屏蔽层，所述屏蔽层安置在所述第一封装体上。
10.根据权利要求1所述的半导体设备封装，其中所述电子组件模块进一步包括：
第三衬底；
电子组件，所述电子组件安置在所述第三衬底上并且通过所述第三衬底连接到所述第一衬底；以及
第二封装体，所述第二封装体包封所述电子组件。
11.根据权利要求10所述的半导体设备封装，其中所述电子组件模块的所述第三衬底通过所述第一封装体与空气隔离。
12.根据权利要求10所述的半导体设备封装，其进一步包括屏蔽层，所述屏蔽层安置在所述第二封装体上。
13.根据权利要求2所述的半导体设备封装，其中所述第一衬底进一步包括接地层，所述接地层与所述第一天线图案至少基本上对齐。
14.一种半导体设备封装，其包括：
第一衬底，所述第一衬底具有第一表面和与所述第一表面相对的第二表面；
电子组件模块，所述电子组件模块安置在所述第一衬底的所述第一表面上；
天线模块，所述天线模块安置在所述第一衬底的所述第一表面上并且与所述电子组件模块并排安置，所述天线模块包含第一天线层；
封装体，所述封装体包封所述天线模块；以及
第二天线层，所述第二天线层安置在所述封装体上并且与所述第一天线层基本上对齐。
15.根据权利要求14所述的半导体设备封装，其中所述天线模块进一步包括：
载体，所述载体具有第一表面和与所述第一表面相对的第二表面；
第一介电层，所述第一介电层安置在所述载体的所述第一表面上，第一天线图案安置在所述第一介电层上；
第二介电层，所述第二介电层安置在所述载体的所述第二表面上；以及
馈线，所述馈线安置在所述第二介电层内并且电连接到所述第一天线图案和所述第一衬底。
16.根据权利要求15所述的半导体设备封装，其中所述第一介电层的厚度与所述第二介电层的厚度基本上相同。
17.根据权利要求14所述的半导体设备封装，其中所述封装体进一步包封所述电子组件模块。
18.根据权利要求14所述的半导体设备封装，其中所述第一衬底进一步包括接地层，所述接地层与所述第一天线层至少基本上对齐。
19.一种制造半导体设备封装的方法，所述方法包括：
提供载体；
将天线模块安置在所述载体上，其中所述天线模块具有天线图案和与所述天线图案连接的馈线；
去除所述载体以使所述馈线的一部分暴露；以及
在去除所述载体之后，形成对应于所述天线图案的接地层。
20.根据权利要求19所述的方法，其进一步包括：
形成互连结构，所述互连结构用于电连接到所述馈线的所暴露部分。
CN202011335134.0A 2020-03-02 2020-11-25 半导体设备封装和其制造方法 Pending CN113345870A (zh)

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