CN113328012B - PERC battery and manufacturing method for reducing composite rate - Google Patents

PERC battery and manufacturing method for reducing composite rate Download PDF

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Publication number
CN113328012B
CN113328012B CN202110702939.2A CN202110702939A CN113328012B CN 113328012 B CN113328012 B CN 113328012B CN 202110702939 A CN202110702939 A CN 202110702939A CN 113328012 B CN113328012 B CN 113328012B
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layer
polishing
silicon substrate
polishing layer
alkali
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CN113328012A (en
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应小卡
福井健次
习冬勇
夏吉东
陈议文
李贵勇
陈刚
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Zhejiang Aiko Solar Energy Technology Co Ltd
Guangdong Aiko Technology Co Ltd
Tianjin Aiko Solar Energy Technology Co Ltd
Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
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Zhejiang Aiko Solar Energy Technology Co Ltd
Guangdong Aiko Technology Co Ltd
Tianjin Aiko Solar Energy Technology Co Ltd
Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The application is suitable for the technical field of solar cells, and provides a manufacturing method of a PERC cell for reducing a composite rate and the PERC cell. The manufacturing method of the PERC battery for reducing the recombination rate comprises the following steps: performing texturing treatment on the silicon substrate to form a polishing layer and a textured layer which is separated by the polishing layer on the textured silicon substrate; performing diffusion treatment on the silicon substrate after texturing to form a diffusion layer; etching the diffused silicon substrate; annealing the etched silicon substrate to form a silicon oxide layer; depositing a back surface film layer and a front surface film layer on the annealed silicon substrate; and manufacturing a circuit on the silicon substrate on which the back surface film layer and the front surface film layer are deposited, wherein the circuit comprises an electrode which is arranged on the polishing layer. Therefore, the reflectivity of sunlight can be reduced through the suede layer, and the surface recombination rate of the electrode contact area can be reduced through the polishing layer, so that the photoelectric conversion efficiency of the solar cell can be improved.

Description

PERC battery and manufacturing method for reducing composite rate
Technical Field
The application belongs to the technical field of solar cells, and particularly relates to a manufacturing method of a PERC cell for reducing a composite rate and the PERC cell.
Background
In the related art, the reason why the photoelectric conversion efficiency of the PERC battery is greatly improved is mainly that the passivation performance of the back surface is enhanced, and the recombination rate of the back surface is effectively reduced. However, the current bottleneck of improving the photoelectric conversion efficiency of the PERC battery is increasingly applied, and the improvement of the efficiency is urgent. Based on this, how to reduce the recombination rate to improve the photoelectric conversion efficiency of the PERC battery becomes a technical problem to be solved urgently.
Disclosure of Invention
The application provides a manufacturing method of a PERC battery capable of reducing a recombination rate and the PERC battery, and aims to solve the problem of how to reduce the recombination rate so as to improve the photoelectric conversion efficiency of the PERC battery.
In a first aspect, the present application provides a method for manufacturing a PERC battery with reduced recombination rate, including:
performing texturing treatment on a silicon substrate to form a polishing layer and a textured layer which is separated by the polishing layer on the textured silicon substrate;
performing diffusion treatment on the silicon substrate after texturing to form a diffusion layer;
etching the diffused silicon substrate;
annealing the etched silicon substrate to form a silicon oxide layer;
depositing a back surface film layer and a front surface film layer on the annealed silicon substrate;
and manufacturing a circuit on the silicon substrate on which the back surface film layer and the front surface film layer are deposited, wherein the circuit comprises an electrode, and the electrode is arranged on the polishing layer.
Optionally, performing a texturing process on the silicon substrate to form a polishing layer and a textured layer spaced apart by the polishing layer on the textured silicon substrate, including:
treating a silicon substrate by using a texturing alkali liquor to form a texture surface to be patterned on the surface of the silicon substrate;
and polishing the suede to be patterned according to a preset pattern to form the suede layer and the polishing layer.
Optionally, polishing the pile surface to be patterned according to a preset pattern to form the pile surface layer and the polishing layer, including:
covering an alkali-resistant etching-resistant ink mask on the suede layer to be patterned to cover the region corresponding to the suede layer and expose the region corresponding to the polishing layer;
polishing the texture surface to be patterned exposed from the alkali-resistant etching-resistant ink mask by using polishing alkali liquor;
and removing the alkali-resistant etching-resistant ink mask on the polished silicon substrate.
Optionally, the pile surface to be patterned is formed on the front surface and the back surface of the silicon substrate, the polishing layer comprises a front polishing layer and a back polishing layer, the pile surface layer is positioned on the front surface of the silicon substrate, and the pile surface layer is separated by the front polishing layer; covering an alkali-resistant and etching-resistant ink mask on the suede to be patterned to cover the region corresponding to the suede layer and expose the region corresponding to the polishing layer, wherein the method comprises the following steps:
and covering an alkali-resistant etching-resistant ink mask on the front surface of the silicon substrate to cover the area corresponding to the suede layer and expose the area corresponding to the front polishing layer and the area corresponding to the back polishing layer.
Optionally, covering an alkali-resistant etching-resistant ink mask on the suede to be patterned to cover an area corresponding to the suede layer and expose an area corresponding to the polishing layer, including:
and covering an alkali-resistant anti-etching ink mask on the suede to be patterned by utilizing screen printing.
Optionally, in the step of polishing the texture surface to be patterned exposed from the alkali-resistant etching-resistant ink mask with a polishing alkali solution, the polishing alkali solution includes a KOH solution and/or a NaOH solution, and the volume concentration of the polishing alkali solution is in a range of 5% -10%.
Optionally, in the step of polishing the texture surface to be patterned exposed from the alkali-resistant etching-resistant ink mask with a polishing alkali solution, the polishing temperature ranges from 75 ℃ to 85 ℃.
Optionally, in the step of polishing the texture surface to be patterned exposed from the alkali-resistant etching-resistant ink mask by using a polishing alkali solution, the polishing duration is in a range of 100s to 600s.
In a second aspect, the application provides a PERC battery made by the method of any one of the above.
In a third aspect, the present application provides a PERC battery comprising, in order: the silicon oxide film comprises a front surface film layer, a silicon oxide layer, a diffusion layer, a silicon substrate and a back surface film layer; the PERC battery also comprises a circuit, a polishing layer and a suede layer which is separated by the polishing layer, wherein the suede layer and the polishing layer are both arranged on the silicon substrate, the circuit comprises an electrode, and the electrode is arranged on the polishing layer.
According to the manufacturing method of the PERC battery and the PERC battery for reducing the recombination rate, the polishing layer and the textured layer spaced by the polishing layer are formed on the silicon substrate after texturing, and the electrode is arranged on the polishing layer, so that the reflectivity of sunlight can be reduced through the textured layer, the surface recombination rate of the electrode contact area can be reduced through the polishing layer, the open-circuit voltage is improved, and the photoelectric conversion efficiency of the solar battery is improved.
Drawings
FIG. 1 is a flow chart of a method of fabricating a PERC cell with reduced recombination rate in accordance with an embodiment of the present application;
fig. 2 is a schematic structural view of a PERC battery according to an embodiment of the application;
FIG. 3 is a flow chart of a method of fabricating a PERC cell with reduced recombination rate in accordance with an embodiment of the present application;
fig. 4 is a flow chart of a method of fabricating a PERC battery with reduced recombination rate in accordance with an embodiment of the application.
Description of main reference numerals:
PERC cell 10, front electrode 11, front film layer 12, silicon oxide layer 13, diffusion layer 14, front polishing layer 151, suede layer 152, silicon substrate 16, back polishing layer 153, back film layer 17, back electrode 18.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the related art, a bottleneck occurs in improvement of photoelectric conversion efficiency of the PERC battery. According to the manufacturing method of the PERC battery and the PERC battery for reducing the recombination rate, the reflectivity of sunlight is reduced through the suede layer, the surface recombination rate of the electrode contact area is reduced through the polishing layer, and the photoelectric conversion efficiency can be improved.
Referring to fig. 1 and 2, a method for manufacturing a PERC battery 10 with reduced recombination rate according to an embodiment of the application includes:
step S11: texturing the silicon substrate 16 to form a polished layer and a textured layer 152 spaced apart from the polished layer on the textured silicon substrate 16;
step S12: diffusion treating the textured silicon substrate 16 to form a diffusion layer 14;
step S13: etching the diffused silicon substrate 16;
step S14: annealing the etched silicon substrate 16 to form a silicon oxide layer 13;
step S15: depositing a back surface film layer 17 and a front surface film layer 12 on the annealed silicon substrate 16;
step S16: an electrical circuit is fabricated on the silicon substrate 16, where the back film 17 and the front film 12 are deposited, the circuit including electrodes disposed on the polishing layer.
In the manufacturing method of the PERC battery 10 for reducing the recombination rate, the silicon substrate 16 after texturing forms the polishing layer and the textured layer 152 spaced by the polishing layer, and the electrode is arranged on the polishing layer, so that the reflectivity of sunlight can be reduced through the textured layer 152, the surface recombination rate of the electrode contact area can be reduced through the polishing layer, the open circuit voltage is improved, and the photoelectric conversion efficiency of the solar battery is improved.
Specifically, in the present embodiment, the silicon substrate 16 is a P-type silicon wafer.
Referring to fig. 3, optionally, step S11 includes:
step S111: treating the silicon substrate 16 with a texturing alkali solution to form a texture surface to be patterned on the surface of the silicon substrate 16;
step S112: and polishing the suede to be patterned according to a preset pattern to form a suede layer 152 and a polishing layer.
Thus, the polishing layer can be precisely formed by performing overall texturing and then performing partial polishing, thereby precisely forming the textured layer 152 spaced by the polishing layer.
In other embodiments, the silicon substrate 16 may be treated with a polishing alkaline solution to form a polishing surface to be patterned on the surface of the silicon substrate 16; the polishing surface to be patterned is treated with a texturing alkaline solution according to a predetermined pattern to form a polishing layer and a textured layer 152 spaced from the polishing layer. Specifically, after the silicon substrate 16 is treated with the polishing alkali solution to form a polishing surface to be patterned on the surface of the silicon substrate 16, a texture mask may be covered on the silicon substrate 16, the area corresponding to the polishing layer is covered by the texture mask, and the area corresponding to the texture layer 152 is exposed from the texture mask; treating the surface to be patterned exposed from the velvet mask with a velvet making alkali solution to form a velvet surface layer 152 and a polishing layer; and removing the texturing mask. Thus, the velvet surface layer 152 can be accurately formed by polishing comprehensively and then locally velvet, so that the polishing layers spacing the velvet surface layers 152 can be accurately formed.
In other embodiments, the silicon substrate 16 may be treated with a texturing alkaline solution according to a predetermined pattern to form a polishing layer and a textured layer 152 spaced from the polished layer. Specifically, the silicon substrate 16 may be covered with a texture mask, the region corresponding to the polishing layer is covered with the texture mask, and the region corresponding to the texture layer 152 is exposed from the texture mask; and treating the exposed area of the self-made velvet mask by using velvet making alkali liquor. In this way, local texturing is performed, and the area which is not textured is used as the polishing layer, so that the textured layer 152 which is formed by the polishing layer and the polished layer at intervals is directly formed, and the efficiency is high.
In other embodiments, silicon substrate 16 may be treated with a texturing and polishing solution, respectively, according to a predetermined pattern to form polishing layer and textured layer 152 spaced from the polished layer. Specifically, the silicon substrate 16 may be covered with a texture mask, the region corresponding to the polishing layer is covered with the texture mask, and the region corresponding to the texture layer 152 is exposed from the texture mask; treating the exposed area of the self-made velvet mask by using velvet making alkali liquor; removing the texturing mask, covering the silicon substrate 16 after the texturing with a polishing mask, covering the region corresponding to the textured layer 152 with the polishing mask, and exposing the region corresponding to the polishing layer from the polishing mask; treating the area exposed from the polishing mask with a polishing alkaline solution; the polishing mask is removed. Thus, the local texturing and the local polishing are performed respectively, thereby forming the polishing layer and the textured layer 152 spaced from the polished layer, and the texturing effect of the textured layer 152 and the polishing effect of the polishing layer can be ensured. It can be understood that in the case of performing local texturing and local polishing, respectively, local texturing may be performed first, and then local polishing may be performed; or the polishing and the texturing can be carried out locally. The specific order is not limited herein.
Optionally, in step S111, the texturing lye comprises a KOH solution with a mass ratio of 1.5% -3%. The mass ratio is, for example, 1.5%, 1.52%, 1.6%, 1.73%, 1.9%, 2%, 2.2%, 2.5%, 2.73%, 3%. Therefore, the mass ratio of the wool making alkali liquor is in a proper range, so that the wool making effect is ensured. In particular, the texturing lye may be contained in a texturing tank.
Optionally, in step S111, the texturing temperature ranges from 75 ℃ to 85 ℃. For example, 75 ℃, 75.2 ℃, 76 ℃, 76.5 ℃, 78 ℃, 80 ℃, 82 ℃, 84.8 ℃ and 85 ℃. Therefore, the temperature of the wool making is in a proper range, so that the wool making effect is ensured.
Optionally, in step S111, the texturing duration ranges from 300S to 500S. For example 300s, 310s, 350s, 370s, 400s, 420s, 450s, 480s, 500s. Thus, the length of the wool making time is in a proper range, and the wool making effect is ensured.
Optionally, in step S111, the weight loss of the silicon substrate 16 after the texturing alkali treatment is controlled to be 0.2g-0.6g. For example, 0.2g, 0.22g, 0.25g, 0.3g, 0.36g, 0.4g, 0.45g, 0.5g, 0.58g, 0.6g. Therefore, the weight reduction is in a proper range, the poor wool making effect caused by too little weight reduction is avoided, and the poor strength of the PERC battery 10 caused by too much weight reduction is also avoided.
Optionally, in step S111, the reflectivity of the silicon substrate 16 after the texturing alkali treatment is controlled to be 8% -12%. For example, 8%, 8.2%, 8.5%, 9%, 9.6%, 10%, 10.5%, 11%, 11.7%, 12%. Therefore, reflection of the silicon wafer to sunlight is reduced through texturing, and photoelectric conversion efficiency is improved.
Optionally, after step S111, the silicon substrate 16 after the texturing alkali treatment is cleaned with an acid solution. In this way, residual texturing lye can be washed away, avoiding that the residual texturing lye on the silicon substrate 16 adversely affects subsequent processing.
Specifically, the acid liquid can be mixed acid liquid of HF and HCL, the concentration is 2% -10%, and the soaking time is 150s-300s. The concentration is, for example, 2%, 2.2%, 3%, 4.5%, 5%, 5.2%, 6%, 7.5%, 8%, 8.2%, 9.6%, 10%. The soaking time is, for example, 150s, 152s, 160s, 172s, 185s, 192s, 200s, 212s, 220s, 232s, 240s, 262s, 273s, 285s, 292s, 300s. Therefore, the concentration and the soaking time of the acid liquid are in proper ranges, and the pickling effect is good.
Alternatively, after the silicon substrate 16 treated with the texturing alkali is washed with an acid solution, the silicon substrate 16 may be washed with clear water and dried. Thus, the residual acid solution on the silicon substrate 16 can be washed away, and the acid solution is prevented from being remained on the silicon substrate 16 to adversely affect the subsequent treatment. Specifically, the silicon substrate 16 may be dehydrated and then dried to improve drying efficiency.
Referring to fig. 4, optionally, step S112 includes:
step S1121: covering an alkali-resistant etching-resistant ink mask on the suede to be patterned to cover the region corresponding to the suede layer 152 and expose the region corresponding to the polishing layer;
step S1122: polishing the texture surface to be patterned exposed from the alkali-resistant etching-resistant ink mask by using polishing alkali liquor;
step S1123: the alkali-resistant etch-resistant ink mask on the polished silicon substrate 16 is removed.
Therefore, the alkali-resistant etching-resistant ink mask is used for realizing the patterning of the suede, and the accuracy and the efficiency are higher. It will be appreciated that the areas corresponding to the nap-side layer 152 are not polished by the polishing solution because they are covered by the alkali-resistant etch-resistant ink mask, and that the areas corresponding to the polishing layer are exposed from the alkali-resistant etch-resistant ink mask and are polished by the polishing solution and form a polishing layer. In this way, patterning of the pile is achieved.
In this embodiment, the texture surface to be patterned is formed on the front and back surfaces of the silicon substrate 16, the polishing layers include a front polishing layer 151 and a back polishing layer 153, the texture surface layer 152 is located on the front surface of the silicon substrate 16, and the texture surface layer 152 is separated by the front polishing layer 151; step S1121 includes:
the front surface of the silicon substrate 16 is covered with an alkali-resistant etching-resistant ink mask to cover the region corresponding to the textured layer 152 and expose the region corresponding to the front surface polishing layer 151 and the region corresponding to the back surface polishing layer 153.
Thus, the front side of the silicon substrate 16 forms a staggered suede layer 152 and front side polishing layer 151, and the back side of the silicon substrate 16 forms an entire back side polishing layer 153. It will be appreciated that since sunlight is incident from the front side of the silicon substrate 16, the back side of the silicon substrate 16 need not be formed with the flocked layer 152, and the flocked layer is not required to be patterned, the back side of the silicon substrate 16 can be directly polished without covering an alkali-resistant etching-resistant ink mask, and alignment is not required when the back electrode is printed, so that the production efficiency can be improved without affecting the performance of the PERC battery 10.
It can be understood that the double-sided suede is obtained by making the velvet, then polishing by using the alkali-resistant anti-etching ink mask, and arranging the electrode on the polishing layer, so that the suede of the non-electrode area is reserved, the surface reflectivity can be reduced to the maximum extent, and the photon injection quantity can be improved. The polishing layer is in a polishing state, and is flatter than the suede layer 152, so that the surface recombination rate is greatly reduced, and the improvement of open pressure is facilitated. After the entire back surface of the silicon substrate 16 is in a polished state, in addition to the reduction of the surface recombination rate and the improvement of the open pressure, it is advantageous to improve the absorption capacity of the PERC cell 10 for light in a long wavelength band and to improve the conversion efficiency of the PERC cell 10.
In other embodiments, the texture surface to be patterned may be formed on the front surface of the silicon substrate 16. In other words, the front side of the silicon substrate 16 is treated with the texturing solution to form a texture to be patterned on the front side of the silicon substrate 16. Thus, the back surface of the silicon substrate 16 is not required to be treated by waste of the texturing alkali, and the cost is reduced.
In other embodiments, the texture surface to be patterned may be formed on the front and back surfaces of the silicon substrate 16. The polishing layers include a front polishing layer 151 and a back polishing layer 153, with the pile layer 152 including a front pile layer and a back pile layer, the front pile layer being separated by the front polishing layer and the back pile layer being separated by the back polishing layer. In this manner, patterned pile surfaces are formed on both the front and back surfaces of the silicon substrate 16.
Optionally, step S1121 includes:
and covering an alkali-resistant anti-etching ink mask on the suede to be patterned by utilizing screen printing.
Thus, the alkali-resistant etching-resistant ink mask can be efficiently and accurately covered on the suede to be patterned.
The screen used when covering the alkali-resistant etching-resistant ink mask in this embodiment may be the same as that used when printing the front electrode 11. In this way, the front electrode 11 can be ensured to be arranged on the front polishing layer 151, and the dislocation between the front electrode 11 and the front polishing layer 151 caused by errors caused by different screen printing plates is avoided, so that the photoelectric conversion efficiency of the PERC cell 10 is improved.
Optionally, in step S1122, the polishing lye comprises a KOH solution and/or a NaOH solution, the polishing lye having a volume concentration in the range of 5% -10%. The volume concentration is, for example, 5%, 5.2%, 6%, 7.5%, 8.3%, 9.6%, 10%. Therefore, the volume concentration of the polishing alkali liquor is in a proper range, so that the polishing effect is ensured.
Optionally, in step S1122, the polishing temperature ranges from 75 ℃ to 85 ℃. For example, 75 ℃, 75.2 ℃, 76 ℃, 76.5 ℃, 78 ℃, 80 ℃, 82 ℃, 84.8 ℃ and 85 ℃. Thus, the polishing temperature is in a proper range, thereby ensuring the polishing effect.
Optionally, in step S1122, the polishing duration ranges from 100S to 600S. For example 100s, 110s, 150s, 210s, 300s, 350s, 400s, 560s, 600s. Thus, the polishing duration is in a proper range, and the polishing effect is ensured.
Optionally, in step S1122, the weight loss of the polished silicon substrate 16 is controlled to be 0.25g-0.5g. For example, 0.25g, 0.3g, 0.36g, 0.4g, 0.45g, 0.5g. Thus, the weight reduction is in a proper range, the poor polishing effect caused by too little weight reduction is avoided, and the poor strength of the PERC battery 10 caused by too much weight reduction is also avoided.
Optionally, in step S1122, the reflectivity of the polished polishing layer after polishing is controlled to be 35% -50%. For example 35%, 36%, 38%, 40%, 42%, 44%, 45%, 48%, 50%. Therefore, the reflectivity of the polishing layer is in a proper range, the poor polishing effect and high recombination rate caused by the too low reflectivity are avoided, and the excessive cost caused by the too high reflectivity is also avoided.
Alternatively, in step S1123, the polished silicon substrate 16 may be cleaned with HCL to remove the alkali-resistant etch-resistant ink mask. Thus, the alkali-resistant etch-resistant ink mask can be chemically removed. Specifically, after removal of the alkali-resistant, etch-resistant ink mask using HCL cleaning, the silicon substrate 16 may be baked.
Alternatively, in step S1123, the alkali-resistant etch-resistant ink mask may be scraped off with a doctor blade. Thus, the alkali-resistant etch-resistant ink mask can be removed mechanically.
Optionally, after step S1123, the silicon substrate 16 may be cleaned with an acid solution. Specifically, the acid liquid can be mixed acid liquid of HF and HCL, the concentration is 2% -10%, and the soaking time is 150s-300s. The concentration is, for example, 2%, 2.2%, 3%, 4.5%, 5%, 5.2%, 6%, 7.5%, 8%, 8.2%, 9.6%, 10%. The soaking time is, for example, 150s, 152s, 160s, 172s, 185s, 192s, 200s, 212s, 220s, 232s, 240s, 262s, 273s, 285s, 292s, 300s. Therefore, by the method of mixed acid liquid cleaning, the oxide layer on the surface of the silicon wafer and metal ions such as K or Na remained during alkali polishing can be removed, and the final conversion efficiency is ensured not to be adversely affected.
Optionally, in step S12, the textured silicon substrate 16 may be subjected to a diffusion process using a low pressure diffusion technique to form the diffusion layer 14. Therefore, the diffusion sheet resistance has better uniformity and lower energy consumption, so that the cost for forming the PN junction is lower, and the effect is better. Specifically, the sheet resistance of the post-diffusion silicon substrate 16 ranges from 100 Ω/-200 Ω/. For example, 100, 110, 120, 150, 170, 180, 190, 200. In this embodiment, the diffusion layer 14 is an N-type layer.
Optionally, between step S12 and step S13, the silicon substrate 16 may be subjected to a front side laser treatment (SE) to achieve localized heavy diffusion.
Alternatively, in step S13, HF and HNO may be used 3 And etching the back and side surfaces of the diffused silicon substrate 16. The ratio of HF to HNO3 ranges from 1:1.5-1:3, for example 1:1.5,1:1.6,1:2,1:2.5,1:2.7,1:3. in this manner, phosphosilicate glass (PSG) and N-type silicon may be removed from the back and sides of silicon substrate 16. The front side of the diffused silicon substrate 16 may be etched using an HF solution. The concentration of the HF solution ranges from 3% to 10%. In this manner, phosphosilicate glass (PSG) may be removed from the front side of silicon substrate 16.
Optionally, in step S13, the weight reduction range of the etched silicon substrate 16 is controlled to be 0.02g-0.05g. For example, 0.02g, 0.021g, 0.025g, 0.03g, 0.035g, 0.04g, 0.045g, 0.05g. Therefore, on the premise of ensuring that the redundant phosphosilicate glass at the edge and the back surface is removed, the polished suede structure at the back surface can be reserved to the maximum extent, the back surface polishing layer 153 is prevented from being excessively corroded, and the reflectivity of the back surface is ensured to meet the specified requirement.
Optionally, in step S13, the back surface reflectivity of the etched silicon substrate 16 is controlled to be 35% -50%. For example 35%, 36%, 38%, 40%, 42%, 45%, 48%, 50%. It is understood that if the reflectivity is less than 35%, the back polishing layer 153 does not reach the polished state, which directly affects the surface recombination rate, resulting in reduced efficiency. If the reflectivity is higher than 50%, the reflectivity of the back is too high, on one hand, the back efficiency is damaged, the double-sided rate of the PERC battery 10 is obviously reduced, and on the other hand, the surface is too flat, so that the binding force of silver silicon and aluminum silicon is reduced, the front and back tension of the PERC battery 10 is directly affected, and the normal welding of the assembly is finally affected.
Alternatively, in step S14, the etched silicon substrate 16 may be subjected to an annealing treatment by thermal oxidation to form the silicon oxide layer 13. Specifically, the annealing temperature ranges from 500 ℃, 510 ℃, 580 ℃, 600 ℃, 650 ℃, 660 ℃, 700 ℃, 750 ℃, 800 ℃. Thus, the recombination of carriers at the surface can be effectively prevented, the conversion efficiency of the PERC battery 10 is improved, the PID resistance of the PERC battery 10 is improved, and the service life is prolonged.
Alternatively, in step S15, an aluminum oxide film 171 (Al 2 O 3 ) And a back surface silicon nitride film 172 (SiN x ). In other words, the back surface film layer 17 includes an aluminum oxide film 171 and a back surface silicon nitride film 172. In this way, back recombination of the PERC battery 10 can be reduced. Specifically, the thickness of the back surface film layer 17 ranges from 70nm to 90nm. For example 70nm, 72nm, 75nm, 80nm, 82nm, 85nm, 88nm, 90nm. Therefore, the passivation effect is better.
Alternatively, in step S15, a front side silicon nitride film (SiN) may be deposited on the front side of the annealed silicon substrate 16 x ). In other words, the front surface film layer 12 includes a front surface silicon nitride film. In this way, the reflectance of the PERC battery 10 to sunlight can be reduced, which is advantageous in improving the photoelectric conversion efficiency of the PERC battery 10. The front side silicon nitride film has a thickness in the range of 65nm to 100nm. For example 65nm, 66nm, 70nm, 75nm, 80nm, 82nm, 90nm, 98nm, 100nm. Positive directionThe refractive index of the planar silicon nitride film is in the range of 1.8 to 2.5. For example 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, 2.5.
Alternatively, in step S16, back surface grooving may be performed using a laser, the back surface electrode 18 may be formed by screen printing using silver paste on the grooved silicon substrate 16, the back electric field may be formed by screen printing using aluminum paste, and the front surface electrode 11 may be formed by screen printing using silver paste. The printed silicon substrate 16 is then sintered. The sintering temperature ranges from 600 ℃ to 900 ℃. For example, 600 ℃, 610 ℃, 660 ℃, 710 ℃, 850 ℃, 900 ℃. In this way, the recombination rate of the surface can be reduced by the back electric field, the back surface can be passivated, and the current can be output through the front electrode 11 and the back electrode 18.
The PERC battery 10 of the present application is manufactured by the method of any one of the above.
According to the PERC battery 10 provided by the embodiment of the application, the textured silicon substrate 16 is provided with the polishing layer and the textured layer 152 spaced by the polishing layer, and the electrode is arranged on the polishing layer, so that the reflectivity of sunlight can be reduced through the textured layer 152, the surface recombination rate of the electrode contact area can be reduced through the polishing layer, the open-circuit voltage is improved, and the photoelectric conversion efficiency of the solar battery is improved.
The PERC battery 10 of the embodiment of the present application includes sequentially stacked: a front surface film layer 12, a silicon oxide layer 13, a diffusion layer 14, a silicon substrate 16, and a back surface film layer 17; PERC cell 10 further includes a circuit, a polishing layer, and a textured layer 152 spaced apart from the polishing layer, the textured layer 152 and the polishing layer both disposed on the silicon substrate 16, the circuit including an electrode disposed on the polishing layer.
According to the PERC battery 10 provided by the embodiment of the application, the textured silicon substrate 16 is provided with the polishing layer and the textured layer 152 spaced by the polishing layer, and the electrode is arranged on the polishing layer, so that the reflectivity of sunlight can be reduced through the textured layer 152, the surface recombination rate of the electrode contact area can be reduced through the polishing layer, the open-circuit voltage is improved, and the photoelectric conversion efficiency of the solar battery is improved.
For the explanation and description of the PERC battery 10, refer to the foregoing, and the description thereof is omitted herein for the sake of redundancy.
By combining the above, the manufacturing method of the PERC battery 10 and the PERC battery 10 for reducing the recombination rate can effectively reduce the recombination rate of the front and back surfaces of the PERC battery 10 and the metal contact area, improve the open circuit Voltage (VOC) and the short circuit current (ISC), improve the absorption of the PERC battery 10 to long-wave-band light, and are beneficial to improving the photoelectric conversion efficiency of the PERC battery 10. In addition, new equipment is not required to be added, the existing equipment can be utilized to reduce the recombination rate so as to improve the photoelectric conversion efficiency, the problems of site occupation and fund investment are avoided, and the method is suitable for mass production and manufacturing of production lines.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application.

Claims (4)

1. A method of fabricating a PERC battery having a reduced recombination rate, comprising:
performing texturing treatment on a silicon substrate to form a polishing layer and a textured layer which is separated by the polishing layer on the textured silicon substrate; the protruding height of the protrusions of the polishing layer is smaller than that of the protrusions of the velvet surface layer;
performing diffusion treatment on the silicon substrate after texturing to form a diffusion layer;
etching the diffused silicon substrate;
annealing the etched silicon substrate to form a silicon oxide layer;
depositing a back surface film layer and a front surface film layer on the annealed silicon substrate;
manufacturing a circuit on a silicon substrate deposited with a back surface film layer and a front surface film layer, wherein the circuit comprises an electrode, and the electrode is arranged on the polishing layer so as to reduce the surface recombination rate of an electrode contact area;
specifically, the method for texturing a silicon substrate to form a polishing layer and a textured layer separated by the polishing layer on the textured silicon substrate comprises the following steps:
treating a silicon substrate by using a texturing alkali liquor to form texture surfaces to be patterned on the front surface and the back surface of the silicon substrate, wherein the polishing layer is of an undulating structure and comprises a front polishing layer and a back polishing layer, the texture surface layer is positioned on the front surface of the silicon substrate, and the texture surface layers are separated by the front polishing layer;
covering alkali-resistant etching-resistant ink masks on the to-be-patterned suede on the front surface of the silicon substrate to cover the areas corresponding to the suede layers and expose the areas corresponding to the front polishing layers and the areas corresponding to the back polishing layers;
polishing the to-be-patterned suede exposed from the alkali-resistant etching-resistant ink mask by using polishing alkali liquor to form the polishing layer; specifically, the polishing alkali solution comprises KOH solution and/or NaOH solution, the volume concentration of the polishing alkali solution is 5-10%, the polishing temperature is 75-78 ℃, and the polishing duration is 100-600 s;
and removing the alkali-resistant etching-resistant ink mask on the polished silicon substrate.
2. The method of fabricating a reduced recombination rate PERC cell according to claim 1, wherein the texture to be patterned on the front side of the silicon substrate is covered with an alkali-resistant, etch-resistant ink mask, comprising:
and covering an alkali-resistant anti-etching ink mask on the suede to be patterned by utilizing screen printing.
3. A PERC battery produced by the method of claim 1 or 2.
4. A PERC battery comprising, in order: the silicon oxide film comprises a front surface film layer, a silicon oxide layer, a diffusion layer, a silicon substrate and a back surface film layer; the PERC battery also comprises a circuit, a polishing layer and a suede layer which is separated by the polishing layer, wherein the suede layer and the polishing layer are both arranged on the silicon substrate, the circuit comprises an electrode, and the electrode is arranged on the polishing layer so as to reduce the surface recombination rate of an electrode contact area; the protruding height of the protrusions of the polishing layer is smaller than that of the protrusions of the velvet surface layer;
specifically, the polishing layer is a structure formed by polishing a to-be-patterned suede exposed from an alkali-resistant etching-resistant ink mask, the to-be-patterned suede is a structure formed by making the suede, the polishing layer is of a relief structure and comprises a front polishing layer and a back polishing layer, the velvet surface layer is positioned on the front surface of the silicon substrate, and the velvet surface layer is separated by the front polishing layer.
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