CN113328012A - Method for manufacturing PERC battery capable of reducing recombination rate and PERC battery - Google Patents
Method for manufacturing PERC battery capable of reducing recombination rate and PERC battery Download PDFInfo
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- CN113328012A CN113328012A CN202110702939.2A CN202110702939A CN113328012A CN 113328012 A CN113328012 A CN 113328012A CN 202110702939 A CN202110702939 A CN 202110702939A CN 113328012 A CN113328012 A CN 113328012A
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- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
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Abstract
The application is suitable for the technical field of solar cells, and provides a method for manufacturing a PERC cell capable of reducing recombination rate and the PERC cell. The manufacturing method of the PERC battery for reducing the recombination rate comprises the following steps: texturing the silicon substrate to form a polishing layer and a textured layer separated by the polished layer on the textured silicon substrate; performing diffusion treatment on the textured silicon substrate to form a diffusion layer; etching the diffused silicon substrate; annealing the etched silicon substrate to form a silicon oxide layer; depositing a back film layer and a front film layer on the annealed silicon substrate; and manufacturing a circuit on the silicon substrate deposited with the back film layer and the front film layer, wherein the circuit comprises an electrode which is arranged on the polishing layer. Therefore, the reflectivity to sunlight can be reduced through the suede layer, the surface recombination rate of the electrode contact area can be reduced through the polishing layer, and the photoelectric conversion efficiency of the solar cell can be improved.
Description
Technical Field
The application belongs to the technical field of solar cells, and particularly relates to a method for manufacturing a PERC cell capable of reducing recombination rate and the PERC cell.
Background
In the related art, the reason why the photoelectric conversion efficiency of the PERC cell is greatly improved mainly lies in the enhancement of the passivation performance of the back surface, which effectively reduces the recombination rate of the back surface. However, the bottleneck of improving the photoelectric conversion efficiency of the PERC cell is becoming more and more significant, and the improvement of the efficiency is imminent. Therefore, how to reduce the recombination rate to improve the photoelectric conversion efficiency of the PERC cell becomes a technical problem to be solved urgently.
Disclosure of Invention
The application provides a method for manufacturing a PERC battery capable of reducing recombination rate and the PERC battery, and aims to solve the problem of how to reduce recombination rate to improve photoelectric conversion efficiency of the PERC battery.
In a first aspect, the present application provides a method for manufacturing a PERC battery with a reduced recombination rate, including:
texturing a silicon substrate to form a polishing layer and a textured layer separated by the polishing layer on the textured silicon substrate;
performing diffusion treatment on the textured silicon substrate to form a diffusion layer;
etching the diffused silicon substrate;
annealing the etched silicon substrate to form a silicon oxide layer;
depositing a back film layer and a front film layer on the annealed silicon substrate;
and manufacturing a circuit on the silicon substrate deposited with the back film layer and the front film layer, wherein the circuit comprises an electrode which is arranged on the polishing layer.
Optionally, performing a texturing process on a silicon substrate to form a polishing layer and a textured layer spaced by the polishing layer on the textured silicon substrate, including:
treating the silicon substrate by using wool making alkali liquor to form a suede surface to be patterned on the surface of the silicon substrate;
and polishing the suede to be patterned according to a preset pattern to form the suede layer and the polishing layer.
Optionally, performing polishing treatment on the suede to be patterned according to a preset pattern to form the suede layer and the polishing layer, including:
covering an alkali-resistant and etching-resistant ink mask on the suede to be patterned so as to cover the region corresponding to the suede layer and expose the region corresponding to the polishing layer;
polishing the to-be-patterned suede exposed from the alkali-resistant etching-resistant ink mask by using polishing alkali liquor;
and removing the polished alkali-resistant etching-resistant ink mask on the silicon substrate.
Optionally, the textured surface to be patterned is formed on the front surface and the back surface of the silicon substrate, the polishing layer includes a front surface polishing layer and a back surface polishing layer, the textured surface layer is located on the front surface of the silicon substrate, and the textured surface layer is spaced by the front surface polishing layer; covering an alkali-resistant and etching-resistant ink mask on the suede surface to be patterned so as to cover the region corresponding to the suede layer and expose the region corresponding to the polishing layer, wherein the steps of:
and covering an alkali-resistant and etching-resistant ink mask on the front surface of the silicon substrate to cover the area corresponding to the textured layer and expose the area corresponding to the front surface polishing layer and the area corresponding to the back surface polishing layer.
Optionally, covering an alkali-resistant and etching-resistant ink mask on the textured surface to be patterned to cover a region corresponding to the textured layer and expose a region corresponding to the polishing layer, including:
and covering an alkali-resistant and etching-resistant ink mask on the suede to be patterned by utilizing screen printing.
Optionally, in the step of polishing the to-be-patterned textured surface exposed from the alkali-resistant etching-resistant ink mask by using a polishing alkali solution, the polishing alkali solution includes a KOH solution and/or a NaOH solution, and a volume concentration of the polishing alkali solution is in a range of 5% to 10%.
Optionally, in the step of polishing the to-be-patterned suede exposed from the alkali-resistant etching-resistant ink mask by using polishing alkali liquor, the polishing temperature ranges from 75 ℃ to 85 ℃.
Optionally, in the step of polishing the to-be-patterned suede exposed from the alkali-resistant etching-resistant ink mask by using polishing alkali liquor, the polishing time is in a range of 100s-600 s.
In a second aspect, the PERC cell provided herein is made by any of the methods described above.
In a third aspect, the present application provides a PERC cell, comprising, stacked in order: the silicon substrate comprises a front film layer, a silicon oxide layer, a diffusion layer, a silicon substrate and a back film layer; the PERC cell further comprises a circuit, a polishing layer and a suede layer spaced by the polishing layer, wherein the suede layer and the polishing layer are both arranged on the silicon substrate, the circuit comprises an electrode, and the electrode is arranged on the polishing layer.
In the method for manufacturing the PERC battery with the reduced recombination rate and the PERC battery, the textured silicon substrate forms the polishing layer and the textured layer spaced by the polishing layer, the electrode is arranged on the polishing layer, the reflectivity of sunlight can be reduced through the textured layer, the surface recombination rate of the electrode contact area can be reduced through the polishing layer, the open-circuit voltage is improved, and the photoelectric conversion efficiency of the solar battery is improved.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a PERC cell with a reduced recombination rate according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a PERC cell according to an embodiment of the present application;
FIG. 3 is a schematic flow chart illustrating a method of fabricating a PERC cell with reduced recombination rate according to an embodiment of the present disclosure;
fig. 4 is a schematic flow chart illustrating a method for manufacturing a PERC cell with a reduced recombination rate according to an embodiment of the present application.
Description of the main element symbols:
PERC cell 10, front electrode 11, front membrane layer 12, silicon oxide layer 13, diffusion layer 14, front polishing layer 151, textured layer 152, silicon substrate 16, back polishing layer 153, back membrane layer 17, back electrode 18.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In the related art, the improvement of the photoelectric conversion efficiency of the PERC cell has a bottleneck. According to the manufacturing method of the PERC cell capable of reducing the recombination rate and the PERC cell, the reflectivity of sunlight is reduced through the suede layer, the surface recombination rate of the electrode contact area is reduced through the polishing layer, and the photoelectric conversion efficiency can be improved.
Referring to fig. 1 and 2, a method for manufacturing a PERC cell 10 with a reduced recombination rate according to an embodiment of the present application includes:
step S11: texturing the silicon substrate 16 to form a textured layer 152 between the polishing layer and the polished layer on the textured silicon substrate 16;
step S12: performing diffusion treatment on the textured silicon substrate 16 to form a diffusion layer 14;
step S13: etching the diffused silicon substrate 16;
step S14: annealing the etched silicon substrate 16 to form a silicon oxide layer 13;
step S15: depositing a back film layer 17 and a front film layer 12 on the annealed silicon substrate 16;
step S16: a circuit is fabricated on the silicon substrate 16 with the back side film layer 17 and the front side film layer 12 deposited thereon, the circuit including electrodes disposed on the polishing layer.
In the method for manufacturing the PERC cell 10 with reduced recombination rate according to the embodiment of the present application, the textured silicon substrate 16 forms the polishing layer and the textured layer 152 spaced by the polishing layer, the electrode is disposed on the polishing layer, and not only can the reflectivity of sunlight be reduced through the textured layer 152, but also the surface recombination rate of the electrode contact area can be reduced through the polishing layer, thereby increasing the open-circuit voltage, and facilitating the improvement of the photoelectric conversion efficiency of the solar cell.
Specifically, in the present embodiment, the silicon substrate 16 is a P-type silicon wafer.
Referring to fig. 3, optionally, step S11 includes:
step S111: treating the silicon substrate 16 by using a texturing alkali solution to form a textured surface to be patterned on the surface of the silicon substrate 16;
step S112: and polishing the textured surface to be patterned according to a preset pattern to form a textured layer 152 and a polishing layer.
Thus, by performing the overall texturing and then performing the local polishing, the polishing layer can be accurately formed, and the textured layer 152 spaced by the polishing layer can be accurately formed.
In other embodiments, the silicon substrate 16 may be treated with a polishing lye to form a polished surface to be patterned on the surface of the silicon substrate 16; and treating the polishing surface to be patterned by using a texturing alkali solution according to a preset pattern to form a textured layer 152 between the polishing layer and the layer to be polished. Specifically, after the silicon substrate 16 is treated by polishing lye to form a polishing surface to be patterned on the surface of the silicon substrate 16, a texturing mask can be covered on the silicon substrate 16, an area corresponding to the polishing layer is covered by the texturing mask, and an area corresponding to the texturing layer 152 is exposed from the texturing mask; treating the polishing surface to be patterned exposed from the self-made texturing mask by using texturing alkali liquor to form a textured layer 152 and a polishing layer; and removing the texturing mask. Thus, by performing the overall polishing and then the local texturing, the textured layer 152 can be accurately formed, and the polishing layer for spacing the textured layer 152 can be accurately formed.
In other embodiments, the silicon substrate 16 may be treated with a texturing bath according to a predetermined pattern to form a textured layer 152 spaced from the polishing layer. Specifically, a texturing mask may be covered on the silicon substrate 16, the region corresponding to the polishing layer is covered by the texturing mask, and the region corresponding to the textured layer 152 is exposed from the texturing mask; and treating the exposed area of the self-made texturing mask by using a texturing alkali liquor. In this way, local texturing is performed, and the non-textured area is used as the polishing layer, so that the textured layer 152 between the polishing layer and the polished layer is directly formed, and the efficiency is high.
In other embodiments, the silicon substrate 16 may be treated with a texturing bath and a polishing bath, respectively, according to a predetermined pattern to form a textured layer 152 spaced apart from the polishing layer and the layer to be polished. Specifically, a texturing mask may be covered on the silicon substrate 16, the region corresponding to the polishing layer is covered by the texturing mask, and the region corresponding to the textured layer 152 is exposed from the texturing mask; treating the exposed area of the self-made texturing mask by using a texturing alkali liquor; removing the texturing mask and covering the polishing mask on the textured silicon substrate 16, wherein the region corresponding to the textured layer 152 is covered by the polishing mask, and the region corresponding to the polishing layer is exposed from the polishing mask; treating the region exposed from the polishing mask with polishing lye; and removing the polishing mask. Thus, local texturing and local polishing are respectively carried out, so that the suede layer 152 between the polishing layer and the polished layer is formed, and the texturing effect of the suede layer 152 and the polishing effect of the polishing layer can be ensured. It can be understood that, under the condition of respectively carrying out the local texturing and the local polishing, the local texturing can be carried out firstly, and then the local polishing can be carried out; or the local polishing can be carried out firstly, and then the local texturing can be carried out. The specific order is not limited herein.
Optionally, in step S111, the wool making alkali solution comprises a KOH solution with a mass ratio of 1.5% to 3%. The mass ratio is, for example, 1.5%, 1.52%, 1.6%, 1.73%, 1.9%, 2%, 2.2%, 2.5%, 2.73%, 3%. Therefore, the mass ratio of the texturing alkali liquor is in a proper range, and the texturing effect is ensured. Specifically, the texturing alkali solution can be contained in the texturing groove.
Alternatively, in step S111, the texturing temperature is in the range of 75 ℃ to 85 ℃. For example, 75 ℃, 75.2 ℃, 76 ℃, 76.5 ℃, 78 ℃, 80 ℃, 82 ℃, 84.8 ℃ and 85 ℃. Therefore, the temperature for making the wool is in a proper range, and the effect of making the wool is ensured.
Alternatively, in step S111, the texturing time period ranges from 300S to 500S. For example 300s, 310s, 350s, 370s, 400s, 420s, 450s, 480s, 500 s. Therefore, the texturing duration is in a proper range, and the texturing effect is guaranteed.
Alternatively, in step S111, the weight of the silicon substrate 16 after the texturing alkali treatment is controlled to be 0.2g to 0.6 g. For example, 0.2g, 0.22g, 0.25g, 0.3g, 0.36g, 0.4g, 0.45g, 0.5g, 0.58g, 0.6 g. Thus, the weight reduction is in a proper range, poor texturing effect caused by too little weight reduction is avoided, and poor strength of the PERC battery 10 caused by too much weight reduction is also avoided.
Alternatively, in step S111, the reflectivity of the silicon substrate 16 after the texturing alkali treatment is controlled to be 8% -12%. For example, 8%, 8.2%, 8.5%, 9%, 9.6%, 10%, 10.5%, 11%, 11.7%, 12%. Therefore, reflection of the silicon wafer to sunlight is reduced through texturing, and photoelectric conversion efficiency is improved.
Alternatively, after step S111, the texturing alkali-treated silicon substrate 16 is washed with an acid solution. Therefore, the residual texturing alkali liquor can be washed away, and the situation that the texturing alkali liquor remains on the silicon substrate 16 to have adverse effect on subsequent treatment is avoided.
Specifically, the acid solution can be a mixed acid solution of HF and HCL, the concentration is 2% -10%, and the soaking time is 150-300 s. The concentration is, for example, 2%, 2.2%, 3%, 4.5%, 5%, 5.2%, 6%, 7.5%, 8%, 8.2%, 9.6%, 10%. The soaking time is, for example, 150s, 152s, 160s, 172s, 185s, 192s, 200s, 212s, 220s, 232s, 240s, 262s, 273s, 285s, 292s, 300 s. Therefore, the concentration of the acid liquor and the soaking time are in proper ranges, and the pickling effect is good.
Alternatively, after the silicon substrate 16 after the texturing alkali treatment is washed with the acid solution, the silicon substrate 16 may be washed with clean water and dried. Thus, the residual acid solution on the silicon substrate 16 can be washed away, and the adverse effect of the residual acid solution on the silicon substrate 16 on the subsequent treatment can be avoided. Specifically, the silicon substrate 16 may be dried after dehydration to improve drying efficiency.
Referring to fig. 4, optionally, step S112 includes:
step S1121: covering an alkali-resistant and etching-resistant ink mask on the suede surface to be patterned so as to cover the area corresponding to the suede surface layer 152 and expose the area corresponding to the polishing layer;
step S1122: polishing the to-be-patterned suede exposed from the alkali-resistant and etching-resistant ink mask by using polishing alkali liquor;
step S1123: the polished alkali resistant etch resistant ink mask on the silicon substrate 16 is removed.
Therefore, the imaging of the suede is realized by utilizing the alkali-resistant etching-resistant ink mask, the accuracy is higher, and the efficiency is higher. It can be understood that the regions corresponding to the matte layer 152 are covered by the alkali-resistant etching-resistant ink mask and thus will not be polished by the polishing alkali, and the regions corresponding to the polishing layer are exposed from the alkali-resistant etching-resistant ink mask and thus will be polished by the polishing alkali and form the polishing layer. Thus, the patterning of the suede is realized.
In this embodiment, the textured surface to be patterned is formed on the front surface and the back surface of the silicon substrate 16, the polishing layers include a front polishing layer 151 and a back polishing layer 153, the textured layer 152 is located on the front surface of the silicon substrate 16, and the textured layer 152 is separated by the front polishing layer 151; step S1121 includes:
a mask of alkali-resistant, etch-resistant ink is applied over the front side of silicon substrate 16 to cover the area corresponding to textured layer 152 and expose the area corresponding to front side polishing layer 151 and the area corresponding to back side polishing layer 153.
Thus, the textured layer 152 and the front side polishing layer 151 are formed alternately on the front side of the silicon substrate 16, and the back side polishing layer 153 is formed on the whole back side of the silicon substrate 16. It can be understood that, since sunlight is incident from the front side of the silicon substrate 16, the backside of the silicon substrate 16 does not need to form a textured surface layer 152, and further does not need to pattern a textured surface, and can directly polish the backside of the silicon substrate 16 without covering an alkali-resistant etching-resistant ink mask, and does not need to align when printing a backside electrode, so that the production efficiency can be improved without affecting the performance of the PERC cell 10.
It can be understood that the double-sided suede is obtained by texturing firstly, then the alkali-resistant etching-resistant ink mask is used for polishing, and the electrode is arranged on the polishing layer, so that the suede of the non-electrode area is reserved, the surface reflectivity can be reduced to the maximum extent, and the photon injection quantity is improved. And the polishing layer is in a polishing state, and is more flat compared with the suede layer 152, so that the surface recombination rate is greatly reduced, and the increase of the open pressure is facilitated. After the entire back surface of the silicon substrate 16 is in a polished state, in addition to the reduction of the surface recombination rate and the increase of the open-circuit voltage, the absorption capability of the PERC cell 10 for light in a long-wavelength band is also improved, which is advantageous for improving the conversion efficiency of the PERC cell 10.
In other embodiments, the textured surface to be patterned may be formed on the front surface of the silicon substrate 16. In other words, the front surface of the silicon substrate 16 is treated with the texturing alkali solution to form a textured surface to be patterned on the front surface of the silicon substrate 16. Therefore, the back surface of the silicon substrate 16 is not required to be treated by the wool making alkali liquor, and the cost is reduced.
In other embodiments, the textured surface to be patterned may be formed on the front and back surfaces of the silicon substrate 16. The polishing layers include a front side polishing layer 151 and a back side polishing layer 153, and the textured layer 152 includes a front side textured layer spaced apart by the front side polishing layer and a back side textured layer spaced apart by the back side polishing layer. In this manner, patterned textured surfaces are formed on both the front and back sides of the silicon substrate 16.
Optionally, step S1121 includes:
and covering an alkali-resistant and etching-resistant ink mask on the suede to be patterned by utilizing screen printing.
Therefore, the alkali-resistant and etching-resistant ink mask can be efficiently and accurately covered on the suede to be patterned.
In the present embodiment, the screen used for covering the alkali-resistant etching-resistant ink mask may be the same as the screen used for printing the front electrode 11. Therefore, the front electrode 11 can be ensured to be arranged on the front polishing layer 151, the front electrode 11 and the front polishing layer 151 are prevented from being dislocated due to errors caused by different screen printing plates, and the improvement of the photoelectric conversion efficiency of the PERC cell 10 is facilitated.
Optionally, in step S1122, the polishing alkali solution includes a KOH solution and/or a NaOH solution, and the volume concentration of the polishing alkali solution is in the range of 5% -10%. The volume concentration is, for example, 5%, 5.2%, 6%, 7.5%, 8.3%, 9.6%, 10%. Therefore, the volume concentration of the polishing alkali liquor is in a proper range, and the polishing effect is ensured.
Alternatively, in step S1122, the polishing temperature is in the range of 75 deg.C to 85 deg.C. For example, 75 ℃, 75.2 ℃, 76 ℃, 76.5 ℃, 78 ℃, 80 ℃, 82 ℃, 84.8 ℃ and 85 ℃. Thus, the polishing temperature is in a proper range, and the polishing effect is ensured.
Alternatively, in step S1122, the polishing time period ranges from 100S to 600S. For example 100s, 110s, 150s, 210s, 300s, 350s, 400s, 560s, 600 s. Therefore, the polishing time is in a proper range, and the polishing effect is ensured.
Alternatively, in step S1122, the weight reduction of the polished silicon substrate 16 is controlled to 0.25g to 0.5 g. For example, 0.25g, 0.3g, 0.36g, 0.4g, 0.45g, 0.5 g. Thus, the weight reduction is in a proper range, poor polishing effect caused by too little weight reduction is avoided, and poor strength of the PERC battery 10 caused by too much weight reduction is also avoided.
Alternatively, in step S1122, the reflectivity of the polished polishing layer is controlled to 35% to 50%. For example 35%, 36%, 38%, 40%, 42%, 44%, 45%, 48%, 50%. Therefore, the reflectivity of the polishing layer is in a proper range, poor polishing effect and high recombination rate caused by too low reflectivity are avoided, and too high cost caused by too high reflectivity is also avoided.
Alternatively, in step S1123, the polished silicon substrate 16 may be cleaned with HCL to remove the alkali-resistant and etching-resistant ink mask. Thus, the alkali-resistant, etch-resistant ink mask can be chemically removed. Specifically, after removing the alkali-resistant etch-resistant ink mask using HCL cleaning, the silicon substrate 16 may be baked.
Optionally, in step S1123, the alkali-resistant and etching-resistant ink mask may be scraped off by a doctor blade. In this manner, the alkali-resistant, etch-resistant ink mask may be mechanically removed.
Optionally, after step S1123, the silicon substrate 16 may be cleaned with an acid solution. Specifically, the acid solution can be a mixed acid solution of HF and HCL, the concentration is 2% -10%, and the soaking time is 150-300 s. The concentration is, for example, 2%, 2.2%, 3%, 4.5%, 5%, 5.2%, 6%, 7.5%, 8%, 8.2%, 9.6%, 10%. The soaking time is, for example, 150s, 152s, 160s, 172s, 185s, 192s, 200s, 212s, 220s, 232s, 240s, 262s, 273s, 285s, 292s, 300 s. Therefore, by the method of cleaning with the mixed acid solution, the oxide layer on the surface of the silicon wafer and metal ions such as K or Na remained during alkali polishing can be removed, and the final conversion efficiency is not adversely affected.
Alternatively, in step S12, the textured silicon substrate 16 may be subjected to a diffusion process using a low pressure diffusion technique to form the diffusion layer 14. Therefore, the uniformity of the diffusion sheet resistance is better, the energy consumption is lower, the cost for forming the PN junction is lower, and the effect is better. Specifically, the sheet resistance of the silicon substrate 16 after diffusion ranges from 100 Ω/. about.200 Ω/. about.. For example, 100 Ω/, 110 Ω/, 120 Ω/, 150 Ω/, 170 Ω/, 180 Ω/, 190 Ω/, 200 Ω/. In the present embodiment, the diffusion layer 14 is an N-type layer.
Alternatively, between step S12 and step S13, the silicon substrate 16 may be subjected to front side laser processing (SE) to achieve local re-diffusion.
Alternatively, in step S13, HF and HNO may be employed3The back surface and the side surface of the diffused silicon substrate 16 are etched. The ratio of HF to HNO3 ranged from 1: 1.5-1: 3, for example 1: 1.5,1: 1.6,1: 2,1: 2.5,1:2.7,1: 3. in this manner, phosphosilicate glass (PSG) and N-type silicon on the back surface and side surfaces of the silicon substrate 16 may be removed. The front surface of the diffused silicon substrate 16 may be etched using an HF solution. The concentration range of the HF solution is 3% -10%. In this manner, the phosphosilicate glass (PSG) on the front surface of the silicon substrate 16 may be removed.
Alternatively, in step S13, the weight reduction range of the etched silicon substrate 16 is controlled to be 0.02g to 0.05 g. For example, 0.02g, 0.021g, 0.025g, 0.03g, 0.035g, 0.04g, 0.045g, 0.05 g. Therefore, on the premise of ensuring that redundant phosphorosilicate glass on the edge and the back is removed, the polishing suede structure of the back can be kept to the maximum extent, the back polishing layer 153 is prevented from being excessively corroded, and the back reflectivity is ensured to meet the specified requirements.
Optionally, in step S13, the back side reflectivity of the etched silicon substrate 16 is controlled to be 35% to 50%. For example 35%, 36%, 38%, 40%, 42%, 45%, 48%, 50%. It is understood that if the reflectivity is less than 35%, the backside polishing layer 153 does not reach the polished state, which directly affects the surface recombination rate, resulting in a decrease in efficiency. If the reflectivity is higher than 50%, the reflectivity of the back side is too large, on one hand, the back side efficiency is damaged, the double-side rate of the PERC battery 10 is obviously reduced, on the other hand, the surface is too flat, the bonding force of silver silicon and aluminum silicon is reduced, the tension of the front side and the back side of the PERC battery 10 is directly influenced, and the normal welding of the assembly is finally influenced.
Alternatively, in step S14, the etched silicon substrate 16 may be annealed by thermal oxidation to form the silicon oxide layer 13. Specifically, the annealing temperature ranges from 500 deg.C, 510 deg.C, 580 deg.C, 600 deg.C, 650 deg.C, 660 deg.C, 700 deg.C, 750 deg.C, 800 deg.C. Thus, the recombination of the carriers at the surface can be effectively prevented, the conversion efficiency of the PERC cell 10 is improved, the PID resistance of the PERC cell 10 is improved, and the service life is prolonged.
Alternatively, in step S15, an aluminum oxide film 171 (Al) may be deposited on the back side of the annealed silicon substrate 162O3) And a back surface silicon nitride film 172 (SiN)x). In other words, the back surface film layer 17 includes the aluminum oxide film 171 and the back surface silicon nitride film 172. Thus, PERC power can be reducedThe back of the cell 10 is compounded. Specifically, the thickness of the back film layer 17 ranges from 70nm to 90 nm. For example, 70nm, 72nm, 75nm, 80nm, 82nm, 85nm, 88nm, and 90 nm. Thus, the passivation effect is better.
Alternatively, in step S15, a front side silicon nitride film (SiN) may be deposited on the front side of the annealed silicon substrate 16x). In other words, the front surface film layer 12 includes a front surface silicon nitride film. This reduces the reflectance of the PERC cell 10 to sunlight, and is advantageous for improving the photoelectric conversion efficiency of the PERC cell 10. The thickness of the front silicon nitride film ranges from 65nm to 100 nm. For example, 65nm, 66nm, 70nm, 75nm, 80nm, 82nm, 90nm, 98nm, 100 nm. The refractive index of the front silicon nitride film is in the range of 1.8 to 2.5. For example, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, 2.5.
Alternatively, in step S16, back-surface grooving may be performed using a laser, the back-surface electrode 18 may be formed by screen printing on the grooved silicon substrate 16 using silver paste, the back electric field may be formed by screen printing using aluminum paste, and the front-surface electrode 11 may be formed by screen printing using silver paste. The printed silicon substrate 16 is then sintered. The sintering temperature ranges from 600 ℃ to 900 ℃. For example, 600 ℃, 610 ℃, 660 ℃, 710 ℃, 850 ℃, 900 ℃. In this way, the recombination rate of the surface can be reduced by the back electric field, the back surface can be passivated, and current can be output through the front electrode 11 and the back electrode 18.
The PERC cell 10 of the embodiment of the present application is manufactured by any one of the above-described methods.
In the percolated cell 10, the silicon substrate 16 forms the polishing layer and the suede layer 152 spaced by the polishing layer, the electrode is arranged on the polishing layer, the reflectivity of sunlight can be reduced through the suede layer 152, the surface recombination rate of the electrode contact area can be reduced through the polishing layer, the open-circuit voltage is improved, and the photoelectric conversion efficiency of the solar cell is improved.
The PERC cell 10 of the embodiment of the present application includes, stacked in sequence: a front film layer 12, a silicon oxide layer 13, a diffusion layer 14, a silicon substrate 16 and a back film layer 17; PERC cell 10 further includes a circuit, a polishing layer, and a textured layer 152 spaced apart by the polishing layer, both textured layer 152 and polishing layer being disposed on silicon substrate 16, the circuit including an electrode, the electrode being disposed on the polishing layer.
In the percolated cell 10, the silicon substrate 16 forms the polishing layer and the suede layer 152 spaced by the polishing layer, the electrode is arranged on the polishing layer, the reflectivity of sunlight can be reduced through the suede layer 152, the surface recombination rate of the electrode contact area can be reduced through the polishing layer, the open-circuit voltage is improved, and the photoelectric conversion efficiency of the solar cell is improved.
For the explanation and explanation of PERC cell 10, reference is made to the foregoing description, which is not repeated herein to avoid redundancy.
In summary, the method for manufacturing the PERC cell 10 with the reduced recombination rate and the PERC cell 10 according to the embodiment of the present application can effectively reduce the recombination rate of the front and back surfaces of the PERC cell 10 and the metal contact region, increase open-circuit Voltage (VOC) and short-circuit current (ISC), improve absorption of the PERC cell 10 to long-wavelength light, and facilitate improvement of photoelectric conversion efficiency of the PERC cell 10. In addition, new equipment is not required to be added, the composite rate can be reduced by utilizing the existing equipment so as to improve the photoelectric conversion efficiency, the problems of site occupation and capital investment are avoided, and the method is suitable for batch production and manufacturing of a production line.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
Claims (10)
1. A method of fabricating a PERC cell with reduced recombination rate, comprising:
texturing a silicon substrate to form a polishing layer and a textured layer separated by the polishing layer on the textured silicon substrate;
performing diffusion treatment on the textured silicon substrate to form a diffusion layer;
etching the diffused silicon substrate;
annealing the etched silicon substrate to form a silicon oxide layer;
depositing a back film layer and a front film layer on the annealed silicon substrate;
and manufacturing a circuit on the silicon substrate deposited with the back film layer and the front film layer, wherein the circuit comprises an electrode which is arranged on the polishing layer.
2. The method of claim 1, wherein texturing a silicon substrate to form a polishing layer and a textured layer spaced apart from the polishing layer on the textured silicon substrate comprises:
treating the silicon substrate by using wool making alkali liquor to form a suede surface to be patterned on the surface of the silicon substrate;
and polishing the suede to be patterned according to a preset pattern to form the suede layer and the polishing layer.
3. The method of claim 2, wherein the step of polishing the textured surface to be patterned according to a predetermined pattern to form the textured layer and the polishing layer comprises:
covering an alkali-resistant and etching-resistant ink mask on the suede to be patterned so as to cover the region corresponding to the suede layer and expose the region corresponding to the polishing layer;
polishing the to-be-patterned suede exposed from the alkali-resistant etching-resistant ink mask by using polishing alkali liquor;
and removing the polished alkali-resistant etching-resistant ink mask on the silicon substrate.
4. The method of claim 3, wherein the textured surface to be patterned is formed on the front and back surfaces of the silicon substrate, the polishing layer comprises a front polishing layer and a back polishing layer, the textured surface layer is on the front surface of the silicon substrate, and the textured surface layer is spaced apart by the front polishing layer; covering an alkali-resistant and etching-resistant ink mask on the suede surface to be patterned so as to cover the region corresponding to the suede layer and expose the region corresponding to the polishing layer, wherein the steps of:
and covering an alkali-resistant and etching-resistant ink mask on the front surface of the silicon substrate to cover the area corresponding to the textured layer and expose the area corresponding to the front surface polishing layer and the area corresponding to the back surface polishing layer.
5. The method of claim 3, wherein covering a mask of alkali-resistant and etching-resistant ink on the textured surface to be patterned to cover the textured layer and expose the polishing layer comprises:
and covering an alkali-resistant and etching-resistant ink mask on the suede to be patterned by utilizing screen printing.
6. The method as claimed in claim 3, wherein in the step of polishing the textured surface to be patterned exposed from the alkali-resistant and etching-resistant ink mask with a polishing solution, the polishing solution comprises KOH solution and/or NaOH solution, and the volume concentration of the polishing solution is in the range of 5-10%.
7. The method as claimed in claim 3, wherein the polishing temperature is in the range of 75-85 ℃ in the step of polishing the exposed surface of the PERC with polishing alkali solution.
8. The method as claimed in claim 3, wherein the step of polishing the exposed portion of the textured surface to be patterned by the alkali-resistant and etching-resistant ink mask with a polishing solution has a polishing duration in a range of 100s to 600 s.
9. A PERC cell, produced by the method of any one of claims 1 to 8.
10. A PERC cell, comprising, stacked in sequence: the silicon substrate comprises a front film layer, a silicon oxide layer, a diffusion layer, a silicon substrate and a back film layer; the PERC cell further comprises a circuit, a polishing layer and a suede layer spaced by the polishing layer, wherein the suede layer and the polishing layer are both arranged on the silicon substrate, the circuit comprises an electrode, and the electrode is arranged on the polishing layer.
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