CN113327898B - Manufacturing method of packaging structure and packaging structure - Google Patents
Manufacturing method of packaging structure and packaging structure Download PDFInfo
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- CN113327898B CN113327898B CN202010129734.5A CN202010129734A CN113327898B CN 113327898 B CN113327898 B CN 113327898B CN 202010129734 A CN202010129734 A CN 202010129734A CN 113327898 B CN113327898 B CN 113327898B
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Abstract
The application provides a manufacturing method of a packaging structure and the packaging structure, wherein the manufacturing method comprises the steps of obtaining a substrate, wherein a groove is formed in a preset position of the substrate; and mounting an electronic component at a preset position in the groove, and packaging the electronic component to form a packaging structure. Therefore, the overall height of the packaging structure can be reduced, the heat dissipation path of the electronic component is shortened, and the heat dissipation efficiency is effectively improved.
Description
Technical Field
The invention relates to the technical field of semiconductor system-in-package, in particular to a manufacturing method of a packaging structure and the packaging structure.
Background
In the information society of today, the dependence of human beings on electronic products is increasing day by day, and the electronic products are developing vigorously in the direction of high integration, miniaturization and miniaturization.
At present, in order to achieve high integration, miniaturization, and miniaturization of products, electronic components are generally mounted on a substrate provided with an inner layer circuit pattern, so as to communicate among the electronic components through the substrate, and then the electronic components are packaged to form a package structure with a small volume.
However, the package structure in the prior art has a high overall height, a long heat dissipation path of the electronic component, and a low heat dissipation efficiency.
Disclosure of Invention
The application provides a manufacturing method of a packaging structure and the packaging structure.
In order to solve the technical problem, the application adopts a technical scheme that: a manufacturing method of a package structure is provided, which includes:
obtaining a substrate, wherein a groove is formed in a preset position of the substrate;
and mounting an electronic component at a preset position in the groove, and packaging the electronic component to form a packaging structure.
In order to solve the above technical problem, another technical solution adopted by the present application is: a package structure is provided, which is manufactured by the manufacturing method of the package structure.
According to the manufacturing method of the packaging structure and the packaging structure, the substrate is obtained, and the groove is formed in the preset position of the substrate; mounting an electronic component at the bottom of the groove, and packaging the electronic component to form a packaging structure; compared with the prior art in which the electronic component is directly attached to the surface of the substrate, the manufacturing method effectively reduces the overall height of the packaging structure; simultaneously, because the electronic components of this application sets up in the recess of base plate, the distance of electronic components apart from base plate opposite side surface compares among the prior art that the distance of electronic components and base plate opposite side surface is shorter to shorten electronic components's heat dissipation route greatly, effectively improved radiating efficiency.
Drawings
Fig. 1 is a schematic structural diagram of a package structure according to an embodiment of the present application;
fig. 2 is a schematic flowchart illustrating a manufacturing method of a package structure according to an embodiment of the present disclosure;
fig. 3 is a schematic view of a product structure corresponding to steps S10 to S11 in fig. 2;
FIG. 4 is a schematic diagram of the detailed process of step S10 in FIG. 2;
fig. 5 is a schematic view of a product structure corresponding to steps S200 to S204 in fig. 4;
FIG. 6 is a schematic diagram of the detailed process of step S11 in FIG. 2;
FIG. 7 is a schematic diagram of the product structure from step S300 to step S303 in FIG. 6;
FIG. 8 is a flowchart illustrating the step S200 in FIG. 4;
fig. 9 is a schematic diagram of a product structure corresponding to steps S400 to S402 in fig. 8;
fig. 10 is a detailed flowchart of step S201 in fig. 4;
fig. 11 is a schematic view of a product structure corresponding to steps S500 to S503 in fig. 10;
fig. 12 is a detailed flowchart of step S203 in fig. 4;
fig. 13a is a schematic view of a product structure corresponding to step S600 in fig. 12;
fig. 13b is a schematic view of a product structure corresponding to step S601 in fig. 12;
fig. 13c is a schematic view of a product structure corresponding to step S602 in fig. 12;
fig. 13d is a schematic view of a product structure corresponding to step S603 in fig. 12;
fig. 13e is a schematic view of a product structure corresponding to step S604 in fig. 12;
FIG. 14 is a flowchart illustrating the detailed process of step S204 in FIG. 4;
fig. 15 is a schematic diagram of a product structure corresponding to steps S700 to S702 in fig. 14.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second" and "third" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any indication of the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise. In the embodiment of the present application, all directional indicators (such as up, down, left, right, front, rear \8230;) are used only to explain the relative positional relationship between the components, the motion situation, etc. at a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein may be combined with other embodiments.
The present application will be described in detail with reference to the drawings and examples.
Fig. 1 is a schematic structural diagram of a package structure according to an embodiment of the present application.
In the present embodiment, a package structure 1 is provided, and the package structure 1 specifically includes a substrate 10, an electronic component 11, and an encapsulation layer 12.
Wherein, the electronic component 11 is attached on the substrate 10 to communicate with the circuit layer on the substrate 10; the encapsulation layer 12 covers a surface of the electronic component 11 away from the substrate 10, and cooperates with the substrate 10 to encapsulate the electronic component 11, so as to protect the electronic component 11.
Specifically, a groove 102 is formed in a surface of one side of the substrate 10, and the electronic component 11 is specifically attached to the groove 102 of the substrate 10, so as to reduce the overall height of the package structure 1, and reduce the heat dissipation path of the electronic component 11, thereby improving the heat dissipation efficiency.
Specifically, in one embodiment, a pad is disposed on the substrate 10, the pad is communicated with a circuit layer on the substrate 10, and a bonding wire is disposed on the electronic component 11; in a specific implementation, the bonding wires of the electronic component 11 are connected to the pads through solder paste to communicate with the circuit layer on the substrate 10.
Specifically, the package structure 1 is specifically manufactured by the following manufacturing method of the package structure, please refer to fig. 2 to 3, and fig. 2 is a schematic flow chart of the manufacturing method of the package structure according to an embodiment of the present application; fig. 3 is a schematic view of a product structure corresponding to steps S10 to S11 in fig. 2.
In this embodiment, a method for manufacturing a package structure is provided, where the method includes:
step S10: a substrate is obtained.
Specifically, please refer to fig. 4 and fig. 5, wherein fig. 4 is a schematic flowchart of step S10 in fig. 2; fig. 5 is a schematic view of a product structure corresponding to steps S200 to S204 in fig. 4; the step S10 specifically includes:
step S200: and obtaining a primary processing substrate.
Specifically, the as-machined substrate 100 includes a base material plate and a first metal layer 201 provided on at least one surface of the base material plate; specifically, the substrate plate includes a first surface and a second surface disposed away from the first surface, and in a specific implementation process, the first surface and the first surface of the substrate plate are both provided with the first metal layer 201. The first surface and the second surface of the substrate 10 are in the same direction, and the first surface and the second surface are in the same direction, respectively.
Step S201: and carrying out surface treatment on the primary processed substrate, and exposing a part of the substrate plate.
Specifically, the as-machined substrate 100 includes a first surface and a second surface disposed apart from the first surface; in a specific implementation, both the first and second surfaces of the as-machined substrate 100 are treated and the first surface of a portion of the substrate sheet is exposed.
Step S202: and carrying out lamination treatment on the primary processed substrate to form a multilayer board.
Specifically, lamination is performed from both sides of the first surface and the second surface of the as-processed substrate 100 to form a multilayer board 101; it is understood that the as-machined substrate 100 is in the middle of the multi-layer board 101.
Specifically, referring to fig. 5, in one embodiment, the multi-layer board 101 may be formed by sequentially stacking and pressing a bottom substrate, a preform substrate 100, and a top substrate; specifically, the bottom base plate includes bottom base material board and sets up the bottom metal level on two surfaces at bottom base material board, and the top base plate includes top base material board and the top metal level of setting on the surface of one side of top base material board, wherein, a bottom metal level of bottom base plate and the second surface contact of primary processing base plate 100, the top base plate does not set up the first surface contact of one side surface and primary processing base plate 100 of top metal level to form multiply wood 101, this is all taken as an example to following multiply wood 101's structure.
It is understood that while in the above embodiments the structure of the multi-layer board 101 is a conventional substrate board and build-up laminated four-layer board structure, in other embodiments the multi-layer board 101 structure may also be a coreless process and other multi-layer board structures.
Step S203: and carrying out surface treatment on the multilayer board, and exposing part of the base material board of the multilayer board.
Specifically, the multilayer board 101 includes a first surface and a second surface that is away from the first surface, and in a specific implementation process, both the first surface and the second surface of the multilayer board 101 are processed, and the first surface of a part of the substrate board in the multilayer board 101 is exposed.
Step S204: and processing the base material plates exposed on the multilayer board so as to process off the partially exposed base material plates and form grooves of the base board.
Specifically, two sides of the groove 102 are stepped.
It is understood that a part of the substrate sheet of the multi-layer board 101 is exposed on the surface, and the exposed surface of the substrate sheet is processed in step S204, and the processed part of the substrate sheet is disposed to form the groove 102 of the substrate 10.
Specifically, the structure of the product after the processing of steps S200 to S204 can be specifically seen in fig. 5.
Step S11: and mounting an electronic component at a preset position in the groove, and packaging the electronic component to form a packaging structure.
Specifically, the electronic component 11 may be mounted at a predetermined position of the groove 102 by using a surface mount technology.
Specifically, the electronic component 11 is attached to the bottom wall of the groove 102; it can be understood that the bottom wall of the groove 102 is located at a level lower than that of the first surface of the substrate 10, so that the overall height of the package structure 1 formed by mounting the electronic component 11 in the groove 102 is significantly lower than that of the package structure 1 formed by mounting the electronic component 11 on the first surface of the substrate 10; meanwhile, it can be understood that the vertical distance from the bottom wall of the groove 102 to the second surface of the substrate 10 is obviously smaller than the vertical distance from the first surface to the second surface of the substrate 10, so that the heat dissipation path of the electronic component 11 attached to the bottom wall of the groove 102 is effectively shortened, and the heat dissipation efficiency of the electronic component 11 is greatly improved.
Specifically, the structure of the product after being processed in step S10 and step S11 can be specifically seen in fig. 3.
Specifically, in an embodiment, please refer to fig. 6 and fig. 7, wherein fig. 6 is a schematic flowchart of step S11 in fig. 2; FIG. 7 is a schematic diagram of the product structure from step S300 to step S303 in FIG. 6; step S11 specifically includes:
step S300: and coating adhesive on the preset position of the groove.
The preset position of the groove 102 may be specifically the bottom wall of the groove 102, and the adhesive may specifically cover the entire bottom wall of the groove 102; of course, in other embodiments, the adhesive dots may also be coated on the bottom wall of the groove 102, i.e., at partial positions of the bottom wall, which is not limited by the embodiment.
Specifically, the adhesive may specifically be an epoxy resin.
Step S301: and attaching the electronic component to the preset position of the groove, and attaching the electronic component to the adhesive.
Specifically, one surface of the electronic component 11 is brought into contact with an adhesive so that the electronic component 11 is attached to the substrate 10 via the adhesive.
Step S302: and communicating the electronic component with the circuit layer on the substrate.
Specifically, a bonding wire is arranged on the electronic component 11, a bonding pad is arranged at a position where the groove 102 is connected with the electronic component 11, and the bonding pad is communicated with the circuit layer on the substrate 10; in a specific implementation, the bonding wires on the electronic component 11 may be connected to the bonding pads through solder paste to communicate with the circuit layer on the substrate 10.
The electronic component 11 may include one or any combination of a resistor, an inductor, a capacitor, a chip, and a bare chip of a power supply.
Step S303: and packaging the electronic components to protect the electronic components and form a packaging structure.
Specifically, the electronic component 11 is plastically packaged by using an injection molding device, and the plastic packaging material may be a mixture of epoxy resin and silica, so as to prevent the electronic component 11 from directly contacting with the atmosphere, and further protect the electronic component 11.
It can be understood that the electronic component 11 is packaged to form the package layer 12 of the package structure 1, and the package structure 1 specifically includes the substrate 10, the electronic component 11 disposed on the substrate 10, and the package layer 12, where the package layer 12 covers a side surface of the electronic component 11 away from the substrate 10 and cooperates with the substrate 10 to package the electronic component 11.
Specifically, the structure of the product after being processed in steps S300 and S303 can be specifically seen in fig. 7.
In the manufacturing method of the package structure provided by this embodiment, by obtaining the substrate 10, a groove 102 is formed in a preset position of the substrate 10; mounting an electronic component 11 at the bottom of the groove 102, and packaging the electronic component 11 to form a packaging structure 1; because the groove 102 is formed in the preset position of the substrate 10, and the electronic component 11 is specifically arranged in the groove 102 of the substrate 10, compared with a method for directly attaching the electronic component 11 to the surface of the substrate in the prior art, the manufacturing method of the present application effectively reduces the overall height of the package structure 1; meanwhile, because the electronic component 11 of the present application is disposed in the groove 102 of the substrate 10, the distance from the electronic component 11 to the other surface of the substrate 10 is shorter than the distance from the electronic component 11 to the other surface of the substrate 10 in the prior art, thereby greatly shortening the heat dissipation path of the electronic component 11 and effectively improving the heat dissipation efficiency
Referring to fig. 8 to fig. 15, fig. 8 is a schematic flowchart illustrating the step S200 in fig. 4; fig. 9 is a schematic view of a product structure corresponding to steps S400 to S402 in fig. 8; fig. 10 is a detailed flowchart of step S201 in fig. 4; fig. 11 is a schematic diagram of a product structure corresponding to steps S500 to S503 in fig. 10; fig. 12 is a detailed flowchart of step S203 in fig. 4; fig. 13a is a schematic view of a product structure corresponding to step S600 in fig. 12; fig. 13b is a schematic view of a product structure corresponding to step S601 in fig. 12; fig. 13c is a schematic view of a product structure corresponding to step S602 in fig. 12; fig. 13d is a schematic view of a product structure corresponding to step S603 in fig. 12; fig. 13e is a schematic view of a product structure corresponding to step S604 in fig. 12; FIG. 14 is a detailed flowchart of step S204 in FIG. 4; fig. 15 is a schematic view of a product structure corresponding to steps S700 to S702 in fig. 14.
In this embodiment, a manufacturing method of a package structure is provided, which is different from the first embodiment in that, referring to fig. 8, step S200 specifically includes:
step S400: a carrier plate is provided.
Specifically, the carrier board includes a substrate board and a first metal layer 201 disposed on at least one surface of the substrate board.
Specifically, the substrate plate includes a first surface and a second surface disposed away from the first surface, and in a specific implementation process, the first surface and the second surface of the substrate plate are both provided with the first metal layer 201.
Specifically, the carrier may be a printed circuit board.
Step S401: and drilling holes at a plurality of preset positions of the carrier plate to form a plurality of first via holes.
Specifically, drilling holes at a plurality of preset positions of the carrier plate in a laser drilling mode; the first via hole 202 is a through hole structure penetrating through the upper and lower surfaces of the carrier.
Step S402: and electroplating the side wall of the first conducting hole and forming a first conducting layer so as to conduct the circuit layers on the upper surface and the lower surface of the carrier plate through the first conducting layer.
Specifically, the step consists of a desmear-electroless copper plating process, which is used for in-hole cleaning and copper layer deposition to form the first conductive layer 203. It can be understood that the first conductive layer 203 is in communication with the metal layers on the upper and lower surfaces of the carrier board, so as to conduct the circuit layers on the upper and lower surfaces of the carrier board through the first conductive layer 203.
Specifically, the structure of the product after the processing of step S400 and step S402 can be specifically seen in fig. 9.
Referring to fig. 10, step S201 specifically includes:
step S500: a first photomask etching process is performed on the surface of the pre-processed substrate to form a first photoresist mask at a first predetermined position of the pre-processed substrate.
Specifically, a first photoresist layer is disposed on the first surface and the second surface of the raw substrate 100, and the first photoresist layer is exposed and developed to form a first photoresist mask 300.
Specifically, a first mask etching process is performed on both the first surface and the second surface of the processed substrate 100 to form a first photoresist mask 300 at a first predetermined position on the first surface and the second surface of the processed substrate 100.
Specifically, the first photoresist mask 300 corresponds to a first predetermined position of the as-processed substrate 100.
Specifically, it can be understood that the formation of the first photoresist mask 300 at the first predetermined position of the as-processed substrate 100 can protect the first predetermined position to prevent the position from being plated in the subsequent plating process.
Step S501: electroplating is carried out on the surface of the primary processing substrate to form a first groove.
Specifically, electroplating is performed on the surface of the as-processed substrate 100 to form a second metal layer 301, and then the first photoresist mask 300 is removed to form a first groove 302. It is understood that, since the first predetermined location is provided with the first photoresist mask 300, the first predetermined location is not plated with a metal layer during the plating process, so that the first predetermined location is formed as the first recess 302 on the as-machined substrate 100 after the first photoresist mask 300 is removed.
Specifically, plating is performed on both the first surface and the second surface of the as-processed substrate 100, and the plating solution penetrates through the first via hole 202 in the as-processed substrate 100.
Specifically, a first groove 302 is formed on the first surface of the as-machined substrate 100.
In the implementation process, the thickness of the metal layer formed by electroplating in step S501 may be set according to practical situations, and this embodiment does not limit this.
Step S502: and performing a second mask etching process on the surface of the pre-processed substrate to form a second photoresist mask at a second predetermined position of the pre-processed substrate.
Specifically, a second photoresist layer is disposed on the first surface and the second surface of the preliminary processed substrate 100, and then the second photoresist layer is exposed and developed to form a second photoresist mask 303.
Specifically, the second preset position is partially overlapped with the first preset position, so that part of the first preset position is protected by the second photoresist mask 303, and the problem that the laser milling groove burns through the substrate plate due to no metal layer protection in the subsequent laser milling process of the first preset position protected by the second photoresist mask 303 is solved.
Specifically, a second mask etching process is performed on both the first surface and the second surface of the processed substrate 100 to form a second photoresist mask 303 on a second predetermined position of the first surface and the second surface of the processed substrate 100.
Specifically, the second photoresist mask 303 corresponds to a second predetermined position of the as-processed substrate 100.
It can be understood that the second photoresist mask 303 formed at the second predetermined position of the as-machined substrate 100 can protect the second predetermined position, so as to avoid the problem that the metal layer at the second predetermined position is also etched when the metal layer at the bottom wall of the first groove 302 is etched, which results in the problem that the laser milling groove burns through the substrate plate in the subsequent laser milling groove process due to no protection of the metal layer.
Step S503: the bottom wall of the first recess is subjected to an etching process to reveal a portion of the substrate plate.
Specifically, a differential etching process is performed to etch away the metal layer on the carrier corresponding to the bottom of the first groove 302 and contacting the substrate, so as to expose the substrate at the position.
In the specific implementation, the second photoresist mask 303 is removed after the process of step S503, and then a lamination process is performed to form the multilayer board 101.
Specifically, the structure of the product after the processing of steps S500 and S503 can be specifically seen in fig. 11.
Referring to fig. 12, step S203 specifically includes:
step S600: and drilling holes at a plurality of first preset positions of the multilayer board to form a plurality of second via holes.
Specifically, the structure of the product after processing in step S600 can be specifically seen in fig. 13a.
Specifically, the laser drilling method may be used to drill holes at a plurality of first predetermined positions of the multilayer board 101 to form the second via holes 400.
Specifically, the second via hole 400 penetrates at least two metal layers of the multilayer board 101.
In one embodiment, referring to fig. 13a, a portion of the second via hole 400 penetrates through the top metal layer of the multi-layer board 101 and the plating layer on the first surface of the as-machined substrate 100, and connects the circuit layer on the top metal layer and the circuit layer on the plating layer on the first surface of the as-machined substrate 100; specifically, the second via hole 400 may be disposed at two sides of the multilayer board 101 near the edge; part of the second via hole 400 penetrates through the underlying metal layer of the multi-layer board 101 and the plating layer on the second surface of the as-machined substrate 100, and communicates the wiring layer on the underlying metal layer of the multi-layer board 101 with the wiring layer on the plating layer on the second surface of the as-machined substrate 100; wherein, run through the second via hole 400 of the bottom metal layer of multiply wood 101 and the plating layer on the second surface of the primary processing base plate 100, its part sets up the both sides position near the edge at multiply wood 101, the part sets up the position that corresponds in the first recess 302 bottom of multiply wood 101, so that the second via hole 400 of this position is when the circuit layer on the bottom metal layer of intercommunication and the circuit layer on the plating layer on the second surface of the primary processing base plate 100, also play certain heat dissipation effect, thereby make the electronic components and parts 11 of dress above this second via hole 400 dispel the heat through this hole, compare in prior art through running through the top metal layer of multiply wood 101 and the method that the via hole dispels the heat of bottom metal layer, electronic components and parts 11's heat dissipation route has been shortened greatly, the heat dissipation efficiency has effectively been improved.
Step S601: and electroplating the side wall of the second via hole and forming a second conductive layer so as to conduct all the circuit layers of the multilayer board through the first conductive layer and the second conductive layer.
Specifically, the step is composed of a desmear-electroless copper plating process, which is used for cleaning in-hole and depositing a copper layer to form the second conductive layer 401.
Specifically, the structure of the product after the processing in step S601 can be specifically seen in fig. 13b.
Step S602: and performing a third photomask etching process on the surface of the multilayer board to form a third photoresist mask at a second preset position of the multilayer board.
Specifically, please refer to the related description about the mask etching process in step S500, and the same or similar technical effects can be achieved, which is not repeated herein.
Specifically, the structure of the product after the processing of step S602 can be specifically seen in fig. 13c.
Step S603: and electroplating the surface of the multilayer board to form a second groove.
Specifically, electroplating is performed on the surface of the multilayer board 101 to form a third metal layer 404, and then the third photoresist mask 402 is removed to form a second groove 403. It will be appreciated that because the predetermined location of multi-layer board 101 is provided with third photoresist mask 402, the predetermined location is not plated with a metal layer during the plating process, such that the second predetermined location is formed as second recess 403 in multi-layer board 101 after third photoresist mask 402 is removed.
Specifically, electroplating is performed on both the first surface and the second surface of the multilayer board 101, and the electroplating solution penetrates through the second via hole 400 on the multilayer board 101 so as to connect the circuit layers on the multilayer board 101 in a conductive manner by combining with the first via hole 202; of course, in the implementation, the third metal layer 404 may also be formed by copper deposition.
Specifically, the second groove 403 is formed on the first surface of the multilayer board 101.
In the implementation process, the thickness of the metal layer formed by electroplating in step S603 may be set according to the actual situation, which is not limited in this embodiment.
Specifically, the structure of the product after the processing in step S603 can be specifically seen in fig. 13d.
Step S604: and etching the bottom wall of the second groove to expose part of the base material plate of the multilayer plate.
Specifically, a differential etching process flow is performed to etch away the metal layer between the bottom of the second groove 403 and the substrate board, so as to expose the substrate board at the position of the multilayer board 101 and prevent a short circuit phenomenon.
Specifically, the structure of the product after processing in step S604 can be specifically seen in fig. 13e.
Referring to fig. 14, step S204 specifically includes:
step S700: and performing resistance welding at a plurality of preset positions of the exposed substrate plate to protect the preset positions.
Specifically, the specific solder mask process can refer to the solder mask processing process in the prior art, and the same or similar technical effects can be achieved, and the details of this embodiment are not repeated herein.
Step S701: and carrying out laser groove milling on the substrate board exposed at other positions where the resistance welding is not carried out so as to process the substrate board exposed at other positions where the resistance welding is not carried out and form a groove of the substrate.
In particular, the substrate plate may be processed by mechanical depth control and laser milling to form the grooves 102 of the substrate 10. Of course, in other embodiments, the processing may be performed by other chemical etching methods, which is not limited in this embodiment.
Step S702: and etching the bottom wall of the groove to remove part of the first metal layer.
Specifically, after the groove is milled in step S701, a differential etching process is performed to remove the metal layer between the bottom of the groove 102 and the substrate board, so as to avoid short circuit between the first metal layer 201 of the groove 102 and the inner pattern network.
Step S703: and coating the surface of the substrate to form a protective layer to protect the substrate.
Specifically, the outer surface of the metal layer exposed to the atmosphere on the substrate 10 is coated to prevent the metal layer from directly contacting the atmosphere, so as to protect the metal layer on the substrate 10.
Wherein, the protective layer can be a gold layer or a silver layer; the metal layer referred to above may be specifically a copper layer.
Specifically, the structure of the product after the processing of steps S700 to S703 can be specifically seen in fig. 15.
The manufacturing method of the packaging structure and the packaging structure 1 provided by the application not only reduce the overall height of the packaging structure 1, but also can be applied to the thinning requirement of the electronic component 11; the heat dissipation channel of the electronic component 11 is shortened, and the heat dissipation device can be applied to chips and other electronic components 11 with higher heat dissipation requirements; meanwhile, the manufacturing method does not need to invest in new equipment and increase the modification cost; in addition, the pasting area of the electronic component 11 is made of full copper sheets, so that the smoothness of the surface of the pasting area is effectively improved, and the heat dissipation efficiency is effectively improved by the copper sheets.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (9)
1. A method for manufacturing a package structure includes:
obtaining a pre-processed substrate, wherein the pre-processed substrate comprises a substrate plate and a first metal layer disposed on at least one surface of the substrate plate;
carrying out surface treatment on the primary processing substrate, and exposing a part of the substrate plate;
carrying out lamination treatment on the primary processing substrate to form a multilayer board;
carrying out surface treatment on the multilayer board, and exposing a part of the base material board of the multilayer board;
processing the substrate board exposed on the multilayer board so as to process off the substrate board partially exposed and form a substrate and a groove of the substrate; wherein, two sides of the groove are in a step structure;
and mounting an electronic component at a preset position in the groove, and packaging the electronic component to form a packaging structure.
2. The method for manufacturing the package structure according to claim 1, wherein the obtaining the preliminary processed substrate specifically includes:
providing a carrier plate; the carrier plate comprises a base material plate and a first metal layer arranged on at least one surface of the base material plate;
drilling holes in a plurality of preset positions of the carrier plate to form a plurality of first via holes;
and electroplating the side wall of the first conducting hole and forming a first conducting layer so as to conduct the circuit layers on the upper surface and the lower surface of the carrier plate through the first conducting layer.
3. The method for manufacturing the package structure according to claim 1, wherein the performing the surface treatment on the preliminary processed substrate and exposing a portion of the substrate board specifically comprises:
performing a first photomask etching process on the surface of the primary processing substrate to form a first photoresist mask at a first preset position of the primary processing substrate;
electroplating the surface of the primary processing substrate to form a first groove;
performing a second photomask etching process on the surface of the primary processing substrate to form a second photoresist mask at a second preset position of the primary processing substrate;
and etching the bottom wall of the first groove to expose part of the substrate plate.
4. The method for manufacturing the package structure according to claim 3, wherein the electroplating on the surface of the preliminary processed substrate to form the first groove specifically comprises:
electroplating the surface of the primary processing substrate to form a second metal layer;
and removing the first photoresist mask to form a first groove.
5. The method for manufacturing a package structure according to claim 2, wherein the surface treatment of the multilayer board and the exposing of a portion of the substrate board of the multilayer board comprise:
drilling holes in a plurality of first preset positions of the multilayer board to form a plurality of second via holes;
electroplating the side wall of the second conducting hole and forming a second conducting layer so as to conduct all circuit layers of the multilayer board through the first conducting layer and the second conducting layer;
performing a third photomask etching process on the surface of the multilayer board to form a third photoresist mask at a second preset position of the multilayer board;
electroplating the surface of the multilayer board to form a second groove;
and etching the bottom wall of the second groove to expose part of the substrate plate of the multilayer plate.
6. The method for manufacturing the package structure according to claim 5, wherein the step of electroplating the surface of the multilayer board to form the second groove comprises:
electroplating the surface of the multilayer board to form a third metal layer;
and removing the third photoresist mask to form a second groove.
7. The method for manufacturing a package structure according to claim 1, wherein the processing the exposed substrate board on the multilayer board to process away the partially exposed substrate board and form a substrate and a groove of the substrate includes:
performing solder mask on a plurality of exposed preset positions of the substrate board to protect the preset positions;
performing laser groove milling on the substrate board exposed at other positions where the solder resist is not performed so as to process the substrate board exposed at other positions where the solder resist is not performed and form a groove of the substrate board;
etching the bottom wall of the groove to remove part of the first metal layer;
coating the surface of the substrate to form a protective layer to protect the substrate.
8. The method of claim 3 or 5, wherein the mask etching process comprises:
setting a light resistance layer;
and exposing and developing the photoresist layer to form a photoresist mask.
9. A package structure, characterized in that it is manufactured by the method of any one of claims 1 to 8.
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| TW200644204A (en) * | 2005-06-07 | 2006-12-16 | Phoenix Prec Technology Corp | Substrate structure of semiconductor package |
| JP5100081B2 (en) * | 2006-10-20 | 2012-12-19 | 新光電気工業株式会社 | Electronic component-mounted multilayer wiring board and manufacturing method thereof |
| JP5013973B2 (en) * | 2007-05-31 | 2012-08-29 | 株式会社メイコー | Printed wiring board and method for manufacturing the same, electronic component housing board using the printed wiring board, and method for manufacturing the same |
| US10468399B2 (en) * | 2015-03-31 | 2019-11-05 | Cree, Inc. | Multi-cavity package having single metal flange |
| CN109659239B (en) * | 2018-11-22 | 2021-05-18 | 珠海越亚半导体股份有限公司 | Integrated circuit packaging method and structure with post-embedded core process |
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Effective date of registration: 20231017 Address after: Building 101, No. 2 Shennan Circuit, East Zone, Gaoqiao Brand Industrial Park, Gaoqiao Community, Pingdi Street, Longgang District, Shenzhen City, Guangdong Province, 518000 Patentee after: Shenzhen Guangxin Packaging Substrate Co.,Ltd. Address before: No. 1639, Yanlong Avenue, Pingdi street, Longgang District, Shenzhen, Guangdong 518117 Patentee before: SHENNAN CIRCUITS Co.,Ltd. |