CN113314617A - 一种软快恢复二极管及其制备方法 - Google Patents

一种软快恢复二极管及其制备方法 Download PDF

Info

Publication number
CN113314617A
CN113314617A CN202110476668.3A CN202110476668A CN113314617A CN 113314617 A CN113314617 A CN 113314617A CN 202110476668 A CN202110476668 A CN 202110476668A CN 113314617 A CN113314617 A CN 113314617A
Authority
CN
China
Prior art keywords
district
region
layer
diffusion
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110476668.3A
Other languages
English (en)
Inventor
贺晓金
王光磊
袁强
陆超
姚秋原
孟繁新
王博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
China Zhenhua Group Yongguang Electronics Coltd
Original Assignee
China Zhenhua Group Yongguang Electronics Coltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by China Zhenhua Group Yongguang Electronics Coltd filed Critical China Zhenhua Group Yongguang Electronics Coltd
Priority to CN202110476668.3A priority Critical patent/CN113314617A/zh
Publication of CN113314617A publication Critical patent/CN113314617A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/868PIN diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明提供的一种软快恢复二极管;包括N区和P区,P区扩散在N区上端面中部的凹槽内,所述N区包括依次在N+区上生长的N缓冲区和外延区,所述P区包括P base区和P+区,P base区嵌入外延区的上端面中部,所述P+区扩散在P base区的两端,所述外延区的上端面外端制作有钝化层,外延区的中心制作有阳极金属层,N+区的底部制作有金属层。本发明通过超低掺杂浓度的N型漂移区和低掺杂浓度的P base区可以有效地可以有效的降低反向恢复电荷和反向恢复时间;N型漂移区下表面的N型缓冲层可以缓冲空间电荷区扩展,减缓了载流子反向抽取速度,使恢复特性得到软化;并且高掺杂的深结P+区可以有效抑制电场集中,降低器件反向漏电。

Description

一种软快恢复二极管及其制备方法
技术领域
本发明涉及一种软快恢复二极管及其制备方法。
背景技术
现有技术中的快恢复二极管其主要结构包括:轻掺杂N型漂移区;位于所述轻掺杂N型漂移区表面的重掺杂P型区;位于所述重掺杂P型区表面的阳极金属层;位于所述轻掺杂N型漂移区下表面的重掺杂N型衬底层;位于所述重掺杂N型衬底层表面的阴极金属层。
当器件在正向导通时,轻掺杂N型漂移区和重掺杂P型区内存储有大量的少数载流子空穴和电子;当器件关断时,其耗尽区在轻掺杂N型漂移区与重掺杂P型区向外扩展;由于轻掺杂漂移区一侧的浓度较低,器件关断时,耗尽区主要向轻掺杂一侧扩展;在耗尽区扩展的过程中,耗尽区所经过的区域少数载流子被迅速扫出,造成反向恢复电流迅速减少到0,FRD软度较差,导致回路中产生了较大的过冲电压,进而引起系统电路元件损坏。
发明内容
为解决上述技术问题,本发明提供了一种软快恢复二极管及其制备方法。
本发明通过以下技术方案得以实现。
本发明提供的一种软快恢复二极管;包括N区和P区,P区扩散在N区上端面中部的凹槽内,所述N区包括依次在N+区上生长的N缓冲区和外延区,所述P区包括P base区和P+区,P base区嵌入外延区的上端面中部,所述P+区扩散在P base区的两端,所述外延区的上端面外端制作有钝化层,外延区的中心制作有阳极金属层,N+区的底部制作有金属层。
本申请是一种双基区结构,下面为N+区,上面分别为双基区的N区和N-区,有源区采用低掺杂浓度P base浅结结构,结终端采用的是高掺杂浓度的P+深结结构,当正向导通时,低掺杂浓度的P base区可以有效地降低反向恢复电荷、反向恢复时间和抑制反向恢复峰值电流的作用,当器件处于反向偏置时,二极管的N区缓冲层可以缓冲空间电荷区的扩展,缩短基区宽度和降低通态电压;并且N-N与NN+界面的电场减缓了载流子反向抽取速度,使得在N区缓冲层存储有更多的电荷用于复合,使恢复特性得到软化;并且高掺杂浓度的深结P+区可以有效抑制电场集中,降低器件的反向漏电流。
所述金属层包括依次覆盖在N+区底部的钛层、镍层、银层。
所述阳极金属层中部与P base区接触,阳极金属层的边缘搭接在钝化层的上端面上。
所述P+区对称镶嵌在P base区的两端且部分融合在P base区内。
一种软快恢复二极管的制备方法,其步骤为:
1)制作衬底,在衬底上端面依次生长N缓冲层和N-外延层;
2)在N-外延层上通过热氧化生长氧化层;
3)在氧化层中部两端进行光刻、刻蚀出两个对称的P+区扩散窗口;
4)在窗口内进行P+区硼预扩、P+区硼主扩散,并生长热氧化层;
5)对晶圆进行光刻、刻蚀出P base区离子注入窗口;
6)进行P base区硼注入、推阱;
7)在晶圆表面进行进行磷硅玻璃和氮化硅薄膜淀积形成钝化层;
8)将衬底底部减薄;
9)在衬底底部进行铂扩散;
10)在晶圆表面进行氮化硅、磷硅玻璃和氧化硅光刻形成蒸发窗口;
11)对晶圆进行金属Al蒸发,并进行金属刻蚀;
12)对晶圆进行正面金属Al合金;
13)进行衬底减薄;
14)在衬底底部进行金属化,依次为钛、镍、银。
所述N缓冲区和N-外延区的厚度均为6~7μm,电阻分别为2~3Ω·cm和30~35Ω·cm。
所述氧化层采用干氧+湿氧+干氧工艺氧化层生长温度为1000~1100℃,生长时间为80~120min。
P+区硼预扩扩散源采用固态扩散源,预扩散温度和时间分别为1080~1010℃,50~65min;P+区硼主扩散采用氧化+推阱的方式,硼主扩散温度和时间分别为1120~1160℃,160~175min。
所述P base区硼注入的注入剂量和能量分别为5e15cm-2、100keV,然后通过氧化+推阱的方式进行硼主扩散,硼主扩散温度和时间分别为1030~1060℃、70~90min。
所述钝化层首先采用PECVD方式淀积薄膜厚度为0.45~0.55um的磷硅玻璃PSG;然后采用LPCVD方式淀积薄膜厚度为0.25~0.35um的氮化硅Si3N4。
本发明的有益效果在于:通过超低掺杂浓度的N型漂移区和低掺杂浓度的P base区可以有效地可以有效的降低反向恢复电荷和反向恢复时间;N型漂移区下表面的N型缓冲层可以缓冲空间电荷区扩展,减缓了载流子反向抽取速度,使恢复特性得到软化;并且高掺杂的深结P+区可以有效抑制电场集中,降低器件反向漏电。
附图说明
图1是本发明的结构示意图;
图中:1-N+区,2-N缓冲区,3-N-外延区,4-P base区,5-P+区,6-钝化层,7-阳极金属层,8-钛层,9-镍层,10-银层。
具体实施方式
下面进一步描述本发明的技术方案,但要求保护的范围并不局限于所述。
一种软快恢复二极管;包括N区和P区,P区扩散在N区上端面中部的凹槽内,所述N区包括依次在N+区1上生长的N缓冲区2和外延区3,所述P区包括P base区4和P+区5,P base区4嵌入外延区3的上端面中部,所述P+区5扩散在P base区4的两端,所述外延区3的上端面外端制作有钝化层6,外延区3的中心制作有阳极金属层7,N+区1的底部制作有金属层。
本申请的二极管通过超低掺杂浓度的N型漂移区和低掺杂浓度的P base区可以有效地可以有效的降低反向恢复电荷和反向恢复时间;N型漂移区下表面的N型缓冲层可以缓冲空间电荷区扩展,减缓了载流子反向抽取速度,使恢复特性得到软化;并且高掺杂的深结P+区可以有效抑制电场集中,降低器件反向漏电。
实施例1:
如图1所示的二极管芯片结构,其中包括N+区1,N缓冲区2,N-外延区3,P base区4,P+区5,钝化层6。其特征是:P+区5左右对称的镶嵌在P base区4两侧,其与P base区4有一部分重合。
P+区结深为4-5um,P+区表面方块电阻为5-7Ω/□,且两侧P+区5宽度为50um。
Pbase区结深为1.5-2um,P base区表面方块电阻为30-40Ω/□。
钝化层6为磷硅玻璃PSG和氮化硅Si3N4复合钝化层,厚度0.8-0.9um。磷硅玻璃PSG厚度为0.5-0.6um,氮化硅Si3N4厚度为0.3-0.4um。
上述二极管通过以下步骤制作:
1.制作衬底,选取<111>晶向N型抛光片材料,按现有技术生长双层外延,外延参数分别为2Ω·cm、6um和30Ωcm、6um。
2.进行一次氧化,氧化层的生长温度为1050℃,生长时间为95min,氧化层采用干氧+湿氧+干氧工艺。
3.采用现有技术刻蚀氧化层,形成P+区扩散窗口。
4.进行硼预扩散,扩散源采用固态扩散源,预扩散温度和时间分别为1100℃,60min;然后进行硼主扩散(氧化+推阱),硼主扩散温度和时间分别为1150℃,170min。
5.采用现有技术刻蚀氧化层,形成P base区离子注入窗口。
6.进行硼离子注入,注入剂量和能量分别为5e15cm-2、100keV,然后进行硼主扩散(氧化+推阱),硼主扩散温度和时间分别为1050℃、80min。
7.采用PECVD方式淀积磷硅玻璃PSG,淀积薄膜厚度为0.5um;然后采用LPCVD方式淀积氮化硅Si3N4,淀积薄膜厚度为0.3um。
8.进行背面减薄,硅片厚度减薄至250±10um,然后进行背面铂扩散工艺,铂源为液态源,铂扩散温度和时间分别为950min、1h。
9.采用现有技术刻蚀Si3N4、PSG、SiO2,形成金属接触孔。
10.正面蒸发Al金属,厚度为3-4um,按照现有技术刻蚀Al金属,形成正面电极,然后进行金属合金,合金温度和时间分别为400℃、30min。
11.进行背面减薄,硅片厚度减薄至200±10um,然后进行背面金属化,背面金属分别为钛/镍/银,其厚度分别为0.1±0.01um/0.6±0.1um/0.8±0.1um。
表1实施例1工艺产生的二极管参数
Figure BDA0003047300540000061
Figure BDA0003047300540000071

Claims (10)

1.一种软快恢复二极管,其特征在于:包括N区和P区,P区扩散在N区上端面中部的凹槽内,所述N区包括依次在N+区(1)上生长的N缓冲区(2)和外延区(3),所述P区包括P base区(4)和P+区(5),P base区(4)嵌入外延区(3)的上端面中部,所述P+区(5)扩散在P base区(4)的两端,所述外延区(3)的上端面外端制作有钝化层(6),外延区(3)的中心制作有阳极金属层(7),N+区(1)的底部制作有金属层。
2.如权利要求1所述的软快恢复二极管,其特征在于:所述金属层包括依次覆盖在N+区(1)底部的钛层(8)、镍层(9)、银层(10)。
3.如权利要求1所述的软快恢复二极管,其特征在于:所述阳极金属层(7)中部与Pbase区(4)接触,阳极金属层(7)的边缘搭接在钝化层(6)的上端面上。
4.如权利要求1所述的软快恢复二极管,其特征在于:所述P+区(5)对称镶嵌在P base区(4)的两端且部分融合在P base区(4)内。
5.一种软快恢复二极管的制备方法,其步骤为:
1)制作衬底,在衬底上端面依次生长N缓冲层和N-外延层;
2)在N-外延层上通过热氧化生长氧化层;
3)在氧化层中部两端进行光刻、刻蚀出两个对称的P+区扩散窗口;
4)在窗口内进行P+区硼预扩、P+区硼主扩散,并生长热氧化层;
5)对晶圆进行光刻、刻蚀出P base区离子注入窗口;
6)进行P base区硼注入、推阱;
7)在N-外延层、P+区、P base区表面上进行磷硅玻璃和氮化硅薄膜淀积形成钝化层;
8)将衬底底部减薄;
9)在衬底底部进行铂扩散;
10)进行氮化硅、磷硅玻璃和氧化硅光刻形成蒸发窗口;
11)在蒸发窗口进行金属Al蒸发,并进行金属刻蚀形成正面金属电极;
12)对晶圆进行正面金属Al合金;
13)进行衬底减薄;
14)在衬底底部进行金属化,依次为钛、镍、银。
6.如权利要求5所述的软快恢复二极管的制备方法,其特征在于:所述N缓冲区和N-外延区的厚度均为6~7μm,电阻分别为2~3Ω·cm和30~35Ω·cm。
7.如权利要求5所述的软快恢复二极管的制备方法,其特征在于:所述氧化层采用干氧+湿氧+干氧工艺氧化层生长温度为1000~1100℃,生长时间为80~120min。
8.如权利要求5所述的软快恢复二极管的制备方法,其特征在于:P+区硼预扩扩散源采用固态扩散源,预扩散温度和时间分别为1080~1010℃,50~65min;P+区硼主扩散采用氧化+推阱的方式,硼主扩散温度和时间分别为1120~1160℃,160~175min。
9.如权利要求5所述的软快恢复二极管的制备方法,其特征在于:所述P base区硼注入的注入剂量和能量分别为5e15cm-2、100keV,然后通过氧化+推阱的方式进行硼主扩散,硼主扩散温度和时间分别为1030~1060℃、70~90min。
10.如权利要求5所述的软快恢复二极管的制备方法,其特征在于:所述钝化层首先采用PECVD方式淀积薄膜厚度为0.45~0.55um的磷硅玻璃PSG;然后采用LPCVD方式淀积薄膜厚度为0.25~0.35um的氮化硅Si3N4。
CN202110476668.3A 2021-04-29 2021-04-29 一种软快恢复二极管及其制备方法 Pending CN113314617A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110476668.3A CN113314617A (zh) 2021-04-29 2021-04-29 一种软快恢复二极管及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110476668.3A CN113314617A (zh) 2021-04-29 2021-04-29 一种软快恢复二极管及其制备方法

Publications (1)

Publication Number Publication Date
CN113314617A true CN113314617A (zh) 2021-08-27

Family

ID=77371216

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110476668.3A Pending CN113314617A (zh) 2021-04-29 2021-04-29 一种软快恢复二极管及其制备方法

Country Status (1)

Country Link
CN (1) CN113314617A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115763572A (zh) * 2022-12-16 2023-03-07 扬州国宇电子有限公司 一种软快恢复二极管及其制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115763572A (zh) * 2022-12-16 2023-03-07 扬州国宇电子有限公司 一种软快恢复二极管及其制备方法
CN115763572B (zh) * 2022-12-16 2023-09-05 扬州国宇电子有限公司 一种软快恢复二极管及其制备方法

Similar Documents

Publication Publication Date Title
US7282753B2 (en) Vertical conducting power semiconducting devices made by deep reactive ion etching
US20140102524A1 (en) Novel electron collectors for silicon photovoltaic cells
JP2016036056A (ja) ポリシリコンドープ領域を有するバックコンタクト型太陽電池のトレンチプロセス及び構造
US20200098945A1 (en) Process for producing a photovoltaic solar cell having a heterojunction and a diffused-in emitter region
CN108682695A (zh) 一种大电流低正向压降碳化硅肖特基二极管芯片及其制备方法
US20090084440A1 (en) Semiconductor photovoltaic devices and methods of manufacturing the same
CN111430453A (zh) 一种反向恢复特性好的rc-igbt芯片及其制造方法
CN111244171A (zh) 一种沟槽rc-igbt器件结构及其制作方法
CN110896098B (zh) 一种基于碳化硅基的反向开关晶体管及其制备方法
CN113314617A (zh) 一种软快恢复二极管及其制备方法
CN114093928A (zh) 一种快恢复二极管的铂掺杂方法
CN212365972U (zh) 融合pn肖特基二极管
KR102668024B1 (ko) 향상된 수명, 패시베이션 및/또는 효율을 갖는 태양 전지
CN214956893U (zh) 一种软快恢复二极管
CN111081758A (zh) 降低导通电阻的SiC MPS结构及制备方法
AU2021393000B2 (en) Back-contact solar cell, and production thereof
CN111799338B (zh) 一种沟槽型SiC JBS二极管器件及其制备方法
CN109559989A (zh) 碳化硅结势垒肖特基二极管及其制作方法
CN210349845U (zh) 一种碳化硅结势垒肖特基二极管
CN207868205U (zh) 一种碳化硅二极管器件
CN113224175A (zh) 一种二极管芯片结构及制备方法
CN112531007A (zh) 具有梯度深度p型区域的结势垒肖特基二极管及制备方法
CN111799337A (zh) 一种SiC JBS二极管器件及其制备方法
CN217522006U (zh) 一种二极管元胞
CN214588868U (zh) 一种二极管芯片结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination