CN113300965A - Cellular router for network-on-chip interconnection - Google Patents
Cellular router for network-on-chip interconnection Download PDFInfo
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- CN113300965A CN113300965A CN202110534810.5A CN202110534810A CN113300965A CN 113300965 A CN113300965 A CN 113300965A CN 202110534810 A CN202110534810 A CN 202110534810A CN 113300965 A CN113300965 A CN 113300965A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/60—Router architectures
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/02—Constructional details
- H04Q1/028—Subscriber network interface devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/02—Constructional details
- H04Q1/04—Frames or mounting racks for selector switches; Accessories therefor, e.g. frame cover
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Abstract
The invention discloses a honeycomb router for network-on-chip interconnection, which comprises a silicon dioxide substrate and N multiplied by N optical switch units arranged on the silicon dioxide substrate in a matrix manner. Each optical switch unit comprises a switch waveguide and 2 bus waveguides. The switch waveguide is formed by superposing a silicon layer, a lower hafnium oxide layer, an indium tin oxide layer, an upper hafnium oxide layer and a metal electrode layer from top to bottom; the 2 bus waveguides are silicon layers. The switch waveguide and the 2 bus waveguides are arranged in parallel on the upper surface of the silicon dioxide substrate; the silicon layer and the metal electrode layer of the switch waveguide are connected with the positive electrode at the same time, and the indium tin oxide layer of the switch waveguide is connected with the negative electrode. The identically numbered optical ports of every 2 adjacent optical switch units are connected, wherein the optical ports suspended in the optical switch units in the first row, the last row, the first column and the last column form N × N routing ports of the router. The invention has the advantages of small size, low power consumption and good stability.
Description
Technical Field
The invention relates to the technical field of network on chip, in particular to a cellular router for network on chip interconnection.
Background
The router, as a key element on the optical network on the optical chip based on the optical interconnection, has a great influence on the performance of the whole system. At present, routers based on optical interconnection network-on-chip are routers based on micro-ring resonators. However, routers based on microring resonators typically require ring radii of 10 μm or more, which limits the packaging process density of the router, making the size of the router large. In addition, when the micro-ring resonator operates the router by heating, the resonant wavelength of the micro-ring changes continuously, which not only requires higher power consumption for switching the optical switch, but also causes some optical signals needing to be directly communicated to resonate with the micro-ring, and the transmission of the optical signals is interrupted, thereby affecting the transmission of the whole optical interconnection network.
Disclosure of Invention
The invention aims to solve the problems of large size, large power consumption and poor stability of the conventional network-on-chip router, and provides a cellular router for network-on-chip interconnection.
In order to solve the problems, the invention is realized by the following technical scheme:
a cellular router for network-on-chip interconnection includes a silicon dioxide substrate and NxN optical switch cells; wherein N is a positive integer greater than or equal to 2; each optical switch unit comprises a switch waveguide and 2 bus waveguides; the switch waveguide is formed by superposing a silicon layer, a lower hafnium oxide layer, an indium tin oxide layer, an upper hafnium oxide layer and a metal electrode layer from top to bottom; the 2 bus waveguides are all silicon layers; the switch waveguide and the 2 bus waveguides are both strip-shaped straight waveguides; the switch waveguide and the 2 bus waveguides are arranged in parallel on the upper surface of the silicon dioxide substrate, the 2 bus waveguides are respectively positioned on two sides of the switch waveguide, and gaps exist between the 2 bus waveguides and the switch waveguide; the silicon layer and the metal electrode layer of the switch waveguide are connected with the positive electrode at the same time, and the indium tin oxide layer of the switch waveguide is connected with the negative electrode; two ends of the 2 bus waveguides form 4 optical ports of the optical switch unit; the N multiplied by N optical switch units are arranged on the silicon dioxide substrate in a matrix manner, and each 2 adjacent optical switch units are arranged in a mirror image manner; the identically numbered optical ports of every 2 adjacent optical switch units are connected, wherein the optical ports suspended in the optical switch units in the first row, the last row, the first column and the last column form N × N routing ports of the router.
In the above scheme, the optical ports with the same number of each 2 adjacent optical switch units are connected through the silicon-based waveguide.
In the above scheme, the metal electrode layer of the switch waveguide is a gold layer.
In the above scheme, the length and width of the switch waveguide and 2 bus waveguides are equal.
In the above scheme, the 2 bus waveguides are equally spaced from the switch waveguide.
Compared with the prior art, the invention has the following characteristics:
1. the structure of the router for the network on the optical chip is designed completely autonomously, surface plasmons and an active material ITO are introduced into an optical switch, and the optical switch is used as an interface for communication between the routers.
2. The optical switch based on the surface plasmon polariton and the active material enables the size of the optical switch to reach a micro-nano level, so that the sizes of the optical switch and the router are greatly reduced.
3. The optical switch only needs to change the bias voltage to realize switching, so that the energy consumption of the optical switch and the router can be effectively reduced, and the switching stability is ensured.
4. The 2 x 2 optical switch structure is adopted, the problem that a common optical switch device used in an optical network on a chip cannot perform a wavelength division multiplexing technology is solved, the communication throughput of the network is improved, the limitation of a communication distance is avoided, and the transmission bandwidth is large.
Drawings
Fig. 1 is a schematic perspective view of a cellular router for network on chip interconnection.
Figure 2 is a top view of a cellular router for network on chip interconnection.
Fig. 3 is a schematic perspective view of the optical switch unit.
Fig. 4 is a side view of the optical switch unit.
Fig. 5 is a schematic top view of the optical switch unit.
Fig. 6 is a schematic diagram of the application of a bias voltage to the switching waveguide.
Fig. 7 is an equivalent circuit diagram of the switching waveguide under the bias voltage application.
Fig. 8 is a simplified circuit diagram of fig. 7.
Reference numbers in the figures: 1. a silicon dioxide substrate; 2. an optical switch unit; 2-1, a switch waveguide; 2-2, bus waveguide; 3. a silicon-based waveguide.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to specific examples.
A cellular router for network-on-chip interconnection, as shown in fig. 1 and 2, comprises a silicon dioxide substrate 1 and N x N optical switch units 2. Where N is a positive integer greater than or equal to 2, and in this embodiment, N is 4.
Each optical switch unit 2 comprises a switch waveguide 2-1 and 2 bus waveguides 2-2. The 2 bus waveguides 2-2 are all silicon layers as shown in fig. 3-5. The switch waveguide 2-1 is formed by superposing a silicon layer, a lower hafnium oxide layer, an indium tin oxide layer, an upper hafnium oxide layer and a metal electrode layer from top to bottom.The lower hafnium oxide layer and the upper hafnium oxide layer of the switch waveguide 2-1 both adopt hafnium oxide (HfO)2) And (4) preparing. HfO2Is a ceramic material with wide band gap and high dielectric constant, which can replace silicon dioxide (SiO) of a gate insulating layer of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) of a core device of a silicon-based integrated circuit2) To solve the conventional SiO in MOSFET2The size limit problem of the development of the/Si structure, which is effective in reducing the size of the optical switch. The ITO layer of the switching waveguide 2-1 is made of an active material Indium Tin Oxide (ITO). ITO is a Transparent Conductive Oxide (TCOs) having a dielectric constant electronic characteristic, which can increase activity between the lower hafnium oxide layer and the upper hafnium oxide layer. The metal electrode layer of the switch waveguide 2-1 is made of a metal conductive material, such as gold, aluminum, or copper, and in this embodiment, the metal electrode layer of the switch waveguide 2-1 is made of gold (Au). The silicon layer of the switch waveguide 2-1 and the silicon layers of the 2 bus waveguides 2-2 are both made of silicon (Si).
The switch waveguide 2-1 and the 2 bus waveguides 2-2 are both strip-shaped straight waveguides, the length and width of the switch waveguide 2-1 and the 2 bus waveguides 2-2 can be adjusted according to requirements, and in this embodiment, the length and width of the switch waveguide 2-1 and the 2 bus waveguides 2-2 are both equal. The switch waveguide 2-1 and the 2 bus waveguides 2-2 are arranged in parallel on the upper surface of the silicon dioxide substrate 1, the 2 bus waveguides 2-2 are respectively positioned at two sides of the switch waveguide 2-1, and a certain gap exists between the switch waveguide 2-1 and the 2 bus waveguides 2-2. The gap between the switch waveguide 2-1 and the 2 bus waveguides 2-2 can be determined according to the coupling performance, and in the present embodiment, the 2 bus waveguides 2-2 are equally spaced from the switch waveguide 2-1. The two ends of the 2 bus waveguides 2-2 of the optical switch cell 2 form 4 optical ports (Port1-Port4) of the optical switch cell 2. The switch waveguide 2-1 of the optical switch unit 2 is used as a coupling bridge of 2 bus waveguides 2-2, and a tunable ITO layer is added in the metal oxide semiconductor structure by utilizing mixed surface plasmon polaritons to form a capacitor which is a tunable position of the optical switch. Referring to fig. 6, the silicon layer and the metal electrode layer of the switching waveguide 2-1 are simultaneously connected to the positive electrode, and the ito layer of the switching waveguide 2-1 is connected to the negative electrode, so as to apply the bias voltage. When a bias voltage is applied to the switch waveguide 2-1, the silicon layer and the Metal electrode layer form an accumulation of positive free electrons, and the indium tin Oxide layer forms an accumulation of negative free electrons, so that the switch waveguide 2-1 is essentially a silicon-based Metal-Oxide-Semiconductor (MOS). Since the silicon-based metal-oxide-semiconductor has a field effect similar to that of a silicon-based metal-oxide-semiconductor during the application of a voltage, a capacitor is formed in the middle, and thus the equivalent circuit of the switching waveguide 2-1 is shown in fig. 7, and the simplified circuit thereof is shown in fig. 8.
In this example, the silicon layers of the switch waveguides and the 2 bus waveguides were etched on a silicon dioxide substrate in the form of a thin film, and the lower hafnium dioxide (HfO) of the switch waveguides2) Layer, Indium Tin Oxide (ITO) layer, upper hafnium oxide layer (HfO)2) And the metal electrode layer is formed by sequential deposition through a sputtering process, and the whole optical switch is a micro-nano optical switch device. The thickness W of the silicon dioxide substrate was 100 nm. The switch waveguide and the 2 bus waveguides have length L8000 nm and width Wg 400 nm. The thickness of each of the 2 bus waveguides was 15 nm. The thickness Hg of the silicon layer of the switch waveguide is 15nm, and the thickness H of the lower hafnium oxide layer and the upper hafnium oxide layerHfO220nm, thickness H of the metal electrode layerAu500 nm. The distance between the switch waveguide and the bus waveguide a and the distance Wgap between the switch waveguide and the bus waveguide b were 150 nm.
The double-bias operation of two states of BAR-through (BAR) and CROSS-Coupling (CROSS) is realized for the optical switch unit 2 by controlling the bias voltage: when light is input to the bus waveguide 2-2a from Port1 of the optical switch: if the bias voltage applied to the switch waveguide 2-1 is 0, the light remains in the bus waveguide 2-2a and is output from the Port2 of the optical switch, which is now in a strip-through state; if the bias voltage applied to the switch waveguide 2-1 is Vdd, light is coupled from the bus waveguide 2-2a into the bus waveguide 2-2c via the switch waveguide 2-1b and out the Port3 of the optical switch, which is now cross-coupled. When light is input to the bus waveguides 2-2c from Port4 of the optical switch: if the bias voltage applied to the switch waveguide 2-1 is 0, the light remains in the bus waveguide 2-2c and is output from the Port3 of the optical switch, which is now in a strip-through state; if the bias voltage applied to the switch waveguide 2-1 is Vdd, light is coupled from the bus waveguide 2-2c into the bus waveguide 2-2a via the switch waveguide 2-1b and out the Port2 of the optical switch, which is now cross-coupled.
The N × N optical switch units 2 constitute an N × N router. The N × N optical switch units 2 are arranged in a matrix on the silicon dioxide substrate 1, and each 2 adjacent optical switch units 2 are arranged in a mirror image. The identically numbered optical ports of each 2 adjacent optical switch units 2 are connected, i.e.: for a current optical switch unit 2, there are 1 optical switch unit 2 adjacent to the current optical switch unit 2 in the 4 directions, i.e., the up, down, left, right, respectively, wherein the Port1 of the current optical switch unit 2 is the Port1 of the optical switch unit 2 adjacent to the current optical switch unit 2 in the first direction, the Port2 of the current optical switch unit 2 is the Port2 of the optical switch unit 2 adjacent to the current optical switch unit 2 in the second direction, the Port3 of the current optical switch unit 2 is the Port3 of the optical switch unit 2 adjacent to the current optical switch unit 2 in the third direction, and the Port4 of the current optical switch unit 2 is the Port4 of the optical switch unit 2 adjacent to the current optical switch unit 2 in the fourth direction. The 2 connected optical ports can be directly connected or connected through a waveguide. In this embodiment, 2 connected optical ports are connected by a silicon-based waveguide 3. Since there is no optical switch unit 2 adjacent thereto in the upper direction of the optical switch unit 2 located in the first row, there is no optical switch unit 2 adjacent thereto in the lower direction of the optical switch unit 2 located in the last row, there is no optical switch unit 2 adjacent thereto in the left direction of the optical switch unit 2 located in the first column, and there is no optical switch unit 2 adjacent thereto in the right direction of the optical switch unit 2 located in the last column; there are thus 2 suspended optical ports in each of the optical switch units 2 located in the first row, the last row, the first column and the last column, which suspended optical ports constitute N × N routing ports of the router.
In the present embodiment, a 4 × 4 router of a honeycomb shape is configured by 16 optical switch units 2. The 16 optical switch units 2 are arranged in a 4 × 4 matrix inside the router, and exchange information with 4 input paths and 4 output paths outside and outside the router. The optical switch units 2 are numbered from 1 to 16, and there is one optical switch unit 2 at each intersection inside the router to control the direction of the optical signal. The size and parameter performance of each optical switch are kept consistent, but the switch states of the optical switches are not necessarily the same, the switches are switched between the CROSS state and the BAR state, so that the high throughput of the router is realized, different channel links can be multiplexed in a mode of not interfering communication, the use efficiency of the switches and the transmission rate of the router are improved, and WDM can be realized. The optimal rate and the optimal throughput of the basic unit router are improved for the cascading efficiency of the later cellular routers.
It should be noted that, although the above-mentioned embodiments of the present invention are illustrative, the present invention is not limited thereto, and thus the present invention is not limited to the above-mentioned embodiments. Other embodiments, which can be made by those skilled in the art in light of the teachings of the present invention, are considered to be within the scope of the present invention without departing from its principles.
Claims (5)
1. A cellular router for network-on-chip interconnection is characterized by comprising a silicon dioxide substrate (1) and N multiplied by N optical switch units (2); wherein N is a positive integer greater than or equal to 2;
each optical switch unit (2) comprises a switch waveguide (2-1) and 2 bus waveguides (2-2); the switch waveguide (2-1) is formed by superposing a silicon layer, a lower hafnium oxide layer, an indium tin oxide layer, an upper hafnium oxide layer and a metal electrode layer from top to bottom; the 2 bus waveguides (2-2) are all silicon layers; the switch waveguide (2-1) and the 2 bus waveguides (2-2) are both strip-shaped straight waveguides; the switch waveguide (2-1) and the 2 bus waveguides (2-2) are arranged in parallel on the upper surface of the silicon dioxide substrate (1), the 2 bus waveguides (2-2) are respectively positioned on two sides of the switch waveguide (2-1), and gaps exist between the 2 bus waveguides (2-2) and the switch waveguide (2-1); the silicon layer and the metal electrode layer of the switch waveguide (2-1) are connected with the positive electrode at the same time, and the indium tin oxide layer of the switch waveguide (2-1) is connected with the negative electrode; two ends of the 2 bus waveguides (2-2) form 4 optical ports of the optical switch unit (2);
the N multiplied by N optical switch units (2) are arranged on the silicon dioxide substrate (1) in a matrix manner, and each 2 adjacent optical switch units (2) are arranged in a mirror image manner; the identically numbered optical ports of every 2 adjacent optical switch units (2) are connected, wherein the optical ports suspended in the optical switch units (2) located in the first row, the last row, the first column and the last column form nxn routing ports of the router.
2. A cellular router for network-on-chip interconnection according to claim 1, characterized in that the identically numbered optical ports of every 2 adjacent optical switch cells (2) are connected by a silicon-based waveguide (3).
3. A cellular router for network-on-chip interconnection according to claim 1, characterized in that the metal electrode layer of the switching waveguide (2-1) is a gold layer.
4. A cellular router for network-on-chip interconnection according to claim 1, characterized in that the switch waveguides (2-1) and the 2 bus waveguides (2-2) are equal in length and width.
5. A cellular router for network-on-chip interconnection according to claim 1, characterized in that the 2 bus waveguides (2-2) are equally spaced from the switch waveguide (2-1).
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| CN202110534810.5A CN113300965A (en) | 2021-05-17 | 2021-05-17 | Cellular router for network-on-chip interconnection |
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