CN209979957U - High-integration mode channel switching controller - Google Patents
High-integration mode channel switching controller Download PDFInfo
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- CN209979957U CN209979957U CN201920825243.7U CN201920825243U CN209979957U CN 209979957 U CN209979957 U CN 209979957U CN 201920825243 U CN201920825243 U CN 201920825243U CN 209979957 U CN209979957 U CN 209979957U
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Abstract
The utility model discloses a high-integration mode channel switching controller, which comprises a substrate layer, a lower cladding and an upper cladding; a left doped flat waveguide layer and a right doped flat waveguide layer are laid on the lower cladding layer, and a left electrode and an input waveguide are arranged on the left doped flat waveguide layer; a right electrode and a trunk waveguide are arranged on the right doped flat waveguide layer; the horizontal MOS capacitor based on the ENZ-ITO is adopted, the concentration of a double-carrier accumulation layer of the ITO layer is adjusted by adjusting the external voltage, the mode multiplexing state conversion is realized by fast phase change, the high-speed switch conversion is realized, the interaction between light and substances is improved, a good foundation is laid for the on-chip mode multiplexing technology, the flexible mode routing applied to a mode division multiplexing network is further realized, and a foundation is laid for realizing a high-performance optical signal processing chip or device in optical communication and photonic systems.
Description
Technical Field
The utility model relates to an optical communication device especially relates to a high integration level mode passageway switching controller.
Background
The Mode-division multiplexing (MDM) technology has an important application prospect in overcoming communication bottlenecks and improving the capacity of an optical transmission network. Silicon photonics has the advantages of compact structure, low cost, optical devices compatible with CMOS (Complementary Metal-Oxide Semiconductor) processes, and the like. To build an on-chip MDM system, various silicon-based building blocks are emerging, including mode multiplexers/demultiplexers, multi-mode power splitters, mode filters, multi-mode curved/crossed waveguides, and Mode Selective Switches (MSSs). Among these devices, the MSS is a fundamental and critical component to implement flexible mode routing and switching for reconfigurable MDM networks.
Recently, some MSS methods of building silicon reconfigurable MDM networks have been reported, including micro-ring resonators (MRRs), mach-zehnder interferometers (MZIs), multimode interference (MMI) couplers, and three-dimensional waveguide couplers (TWCs): specifically, the switch comprises a 1 × 2 multimode switch based on MRRs, an MSS and thermo-optic phase shifter based on MMI coupler and phase shifter, and a TWC-based configuration using Phase Change Materials (PCMs) and Transparent Conductive Oxides (TCOs).
Although these schemes have low crosstalk, low insertion loss, fast switching speed and small size, some of these schemes may degrade the operating bandwidth due to the presence of critical resonance conditions; some electro-optical devices have larger size or the phase shifter realizes essential phase change due to the influence of the traditional electro-optical devices on silicon; still other structures have limited design flexibility and may not be compatible with other on-chip components.
SUMMERY OF THE UTILITY MODEL
Utility model purpose: in order to solve the problems existing in the prior art, the utility model aims to provide a high integration level mode channel switching controller adjusts the carrier concentration of the ITO double accumulation layer through the external grid voltage, realizes ideal on-off state.
The technical scheme is as follows: a high-integration-level mode channel switching controller is characterized by comprising a substrate layer, wherein a lower cladding is arranged on the substrate layer, a doped flat waveguide layer, an input waveguide, a central capacitor and a trunk waveguide are arranged on the lower cladding, and electrodes are arranged on the doped flat waveguide layer;
the central capacitor comprises a central capacitor left side doped silicon layer, a central capacitor left side HfO2, a central capacitor left side ITO layer, a central capacitor right side HfO2 layer and a central capacitor right side doped silicon layer, and the material layers are sequentially connected along the horizontal direction of the lower cladding layer to form a double-carrier accumulation layer; the left doped silicon layer of the central capacitor and the right doped silicon layer of the central capacitor are connected with the doped flat waveguide layer; applying an external voltage to the electrodes and the left ITO layer of the central capacitor;
the lower cladding is covered with an upper cladding.
Further, the doped planar waveguide layers include a left first doped planar waveguide layer, a left second doped planar waveguide layer, a right first doped planar waveguide layer, and a right second doped planar waveguide layer;
the left first doping flat waveguide layer is provided with a left electrode, and the right first doping flat waveguide layer is provided with a right electrode; the left doped silicon layer of the central capacitor is connected with the input waveguide through a left second doped flat waveguide layer, the right doped silicon layer of the central capacitor is connected with the trunk waveguide through a right second doped flat waveguide layer, the input waveguide is connected with the left electrode through a left first doped flat waveguide layer, and the trunk waveguide is connected with the right electrode through a right first doped flat waveguide layer; and applying an external voltage to the left side electrode, the right side electrode and the left side ITO layer of the central capacitor. .
Preferably, the ITO layer on the left side of the central capacitor is made of indium selenide ITO, graphene and G2S2T5And G2S2S4T1。
Further, the mode in the trunk waveguide is any higher-order mode.
Advantageous effects
Compared with the prior art, the utility modelThe utility model has the following progress: 1. the utility model provides a silica-based MSS of horizontal MOS condenser based on ENZ-ITO has improved switching efficiency through introducing the double-carrier accumulation layer to further improve system communication capacity. 2. The utility model discloses an introduction ITO layer makes ITO form horizontal Si HfO2/ITO/HfO2MOS capacitor structure of/Si. The problem of large loss of a metal-based plasma structure of a traditional double-waveguide plasma device is solved, the resistance loss and the light propagation loss are reduced, and the interaction between light and substances is improved, so that the mode switching speed is greatly improved, and the switching power consumption is reduced. 3. The utility model discloses an exert voltage offset on horizontal MOS condenser, control ITO's double-carrier gathers layer concentration or graphite alkene, G2S2T5And G2S2S4T1The phase change crystalline state achieves rapid phase change, and further the switch selection of the mode division multiplexing is realized. 4. The utility model discloses have the ability of selecting and routing different signals in different passageways, switch switching speed is fast, the memory is little, the consumption is little, the size is little, has realized the conversion between the different modes. 5. The utility model discloses based on current ripe CMOS technology preparation, operating cost is low, can realize the mass production, and production efficiency is higher, has competitive advantage. 6. The utility model discloses can use with current multiple multiplexing technique (WDM, PDM etc.) compatibility, widen its range of application and bandwidth capacity, compatible high, the range of application is wide.
Drawings
FIG. 1 is a diagram of a high-integration mode channel switching controller;
FIG. 2 is a schematic cross-sectional view of a high-integration mode channel-switching controller waveguide;
FIG. 3 is a supermode TM-A field profile of a high-integration mode channel switching controller;
FIG. 4 is a supermode TM-B field layout of a high-integration mode channel switching controller;
FIG. 5 is a supermode TM-C field profile of a high-integration mode channel switching controller;
FIG. 6 is a graph of the propagation field in the z-direction for a highly integrated mode channel switching controller operating at an accumulation layer thickness of 10nm and a spacing between waveguides of 200nm, with the switch in the "on" state;
FIG. 7 is a graph of the propagation field in the z-direction for a highly integrated mode channel switching controller with an accumulation layer thickness of 10nm and a spacing between waveguides of 200nm, with the switch in the "off" state;
Detailed Description
As shown in fig. 1 and 2, the high-integration mode channel switching controller of the present invention includes a substrate layer 1, a lower cladding layer 2 disposed on the substrate layer, and an upper cladding layer covering the lower cladding layer 2.
Specifically, a left first doped planar waveguide layer 13, an input waveguide 3, a left second doped planar waveguide layer 15, a central capacitor, a right second doped planar waveguide layer 16, a trunk waveguide 9, and a right first doped planar waveguide layer 14 are sequentially laid on the lower cladding layer 2 from left to right, a left electrode 11 is disposed on the left first doped planar waveguide layer 13, and a right electrode 12 is disposed on the right first doped planar waveguide layer 14. The input waveguide 3 is connected to the left electrode 11 via a left first doped slab waveguide layer 13, and the trunk waveguide 9 is connected to the right electrode 12 via a right first doped slab waveguide layer 14.
Wherein, the central capacitor comprises a left doped silicon layer 4 of the central capacitor and a left HfO of the central capacitor 25. ITO layer 6 on left side of central capacitor and HfO on right side of central capacitor2Layer 7 and the central capacitor right doped silicon layer 8, wherein the central capacitor left doped silicon layer 4 is connected to the input waveguide 3 via a left second doped slab waveguide layer 15, and the central capacitor right doped silicon layer 8 is connected to the trunk waveguide 9 via a right second doped slab waveguide layer 16.
The ITO layer 6 on the left side of the central capacitor is made of indium selenide ITO, graphene and G2S2T5And G2S2S4T1. A doped silicon layer 4 on the left side of the central capacitor, and HfO on the left side of the central capacitor 25. ITO layer 6 on left side of central capacitor and HfO on right side of central capacitor2Layer 7 and center electrodeThe doped silicon layers 8 on the right side of the container are stacked together along the horizontal direction, and external voltage is applied to the two ends of the doped flat waveguide layer and the ITO layer 6 on the left side of the central capacitor. An upper cladding layer 10 is covered on the above waveguide layer.
The utility model discloses a high integration level mode passageway switching controller, including two silicon outer wave guides and a central horizontal MOS (metal-oxide-semiconductor) electric capacity that contains phase change material, through adopting horizontal silicon HfO2/ITO/HfO2MOS capacitor/silicon, dual carrier accumulation layer scheme provides fast phase change and efficient switching slew rate. The carrier concentration of the indium selenide double accumulation layers is adjusted through the additional grid voltage, and an ideal switching state is realized. The on and off states of the MOS mode of the three-waveguide coupler based on the central MOS capacitor are optimized by using a full vector finite element method.
The mode selection switch works according to the following principle: (1) in the off state, a phase matching condition between the three-dimensional waveguide and the three-dimensional waveguide coupler (TWC) can be satisfied without applying a gate voltage. Input quasi-TE0quasi-TE mode multiplexing to trunk waveguide1Mode(s). (2) In the "on" state, a negative gate voltage is applied to the ITO layer, and the matching condition will be destroyed because of the ENZ effect and the index change of the central MOS die is large. Input quasi-TE0The mode will switch back to the input waveguide and be output at the output port of the input waveguide.
The technical solution and the advantages of the present invention will be described in detail with reference to the following embodiments.
A high-integration mode channel switching controller shown in FIGS. 6 and 7 belongs to a specific case analysis example, and calculates an optimally designed propagation field with parameters of an accumulation layer thickness of 10nm, a spacing between waveguides of 200nm, crosstalk of-19.21 dB, a extinction ratio of 17.8dB, and an insertion loss of-1.4 dB.
3-5 are supermode field profiles of a high-integration-mode channel switching controller based on a tri-waveguide coupler; 400nm for input waveguide, 860nm for main line waveguide, 50nm for ITO width, HfO2Has a width of 10nm and a width of 307 of silicon5nm, the thickness of each waveguide and the capacitor is 220nm, the thickness of the thick plate is 30nm, the supermode field distribution when the interval between every two waveguides is 200nm is shown in figure 3, the TM-A supermode of a z domain is shown in figure 4, and the TM-B supermode of the z domain is shown in figure 5.
Claims (3)
1. A high-integration-level mode channel switching controller is characterized by comprising a substrate layer (1), wherein a lower cladding (2) is arranged on the substrate layer, a doped flat waveguide layer, an input waveguide (3), a central capacitor and a trunk waveguide (9) are arranged on the lower cladding (2), and electrodes are arranged on the doped flat waveguide layer;
the central capacitor comprises a central capacitor left side doped silicon layer (4) and a central capacitor left side HfO2(5) An ITO layer (6) at the left side of the central capacitor and HfO at the right side of the central capacitor2The layer (7) and the right side doped silicon layer (8) of the central capacitor are sequentially connected along the horizontal direction of the lower cladding (2) to form a double-carrier accumulation layer; the left doped silicon layer (4) of the central capacitor and the right doped silicon layer (8) of the central capacitor are both connected with the doped flat waveguide layer;
applying an external voltage to the electrodes and the left ITO layer (6) of the central capacitor;
the lower cladding (2) is covered with an upper cladding (10).
2. The high integration density mode channel switching controller of claim 1, wherein: the doped flat waveguide layers comprise a left first doped flat waveguide layer (13), a left second doped flat waveguide layer (15), a right first doped flat waveguide layer (14) and a right second doped flat waveguide layer (16);
a left electrode (11) is arranged on the left first doping flat waveguide layer (13), and a right electrode (12) is arranged on the right first doping flat waveguide layer (14); the left doped silicon layer (4) of the central capacitor is connected with the input waveguide (3) through a left second doped flat waveguide layer (15), the right doped silicon layer (8) of the central capacitor is connected with the trunk waveguide (9) through a right second doped flat waveguide layer (16), the input waveguide (3) is connected with the left electrode (11) through a left first doped flat waveguide layer (13), and the trunk waveguide (9) is connected with the right electrode (12) through a right first doped flat waveguide layer (14);
an external voltage is applied to the left electrode (11), the right electrode (12) and the left ITO layer (6) of the central capacitor.
3. The high integration density mode channel switching controller of claim 1, wherein: the mode in the trunk waveguide (9) is any high-order mode.
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| CN201920825243.7U CN209979957U (en) | 2019-06-03 | 2019-06-03 | High-integration mode channel switching controller |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113253383A (en) * | 2021-06-28 | 2021-08-13 | 西安奇芯光电科技有限公司 | Optical waveguide coupler structure insensitive to wavelength |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113253383A (en) * | 2021-06-28 | 2021-08-13 | 西安奇芯光电科技有限公司 | Optical waveguide coupler structure insensitive to wavelength |
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