CN113299734A - 一种氮化镓晶体管器件及其制备方法 - Google Patents
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Abstract
一种氮化镓晶体管器件及其制备方法,包括由下至上设置的衬底、GaN层、AlGaN层和源漏栅电极结构,源极、漏极设于AlGaN层两侧,栅极设于源极和漏极之间,其特征在于:该AlGaN层的上表面氧化形成若干相互平行且间隔分布的隔离道,隔离道长度方向一端与漏极相连,另一端与源极间隔设置,栅极设于AlGaN层上表面,其长度方向与隔离道相互垂直。本发明通过氧化AlGaN的方式实现纳米沟道,无需蚀刻避免刻蚀引入的均匀性、重复性和损伤的风险,能有效减小寄生电容的影响,提高器件的频率特性。
Description
技术领域
本发明涉及半导体器件领域,特别是指一种氮化镓晶体管器件及其制备方法。
背景技术
作为重要的第三代宽禁带半导体材料,氮化镓(GaN)禁带宽度大(3.4eV),击穿场强高(>3MV/cm),AlGaN/GaN异质结中的二维电子气(2DEG)浓度高(>1013cm-2),电子饱和速度高(2.8x107cm/s),且GaN材料的化学惰性和温度稳定性好,因此,AlGaN/GaN高电子迁移率晶体管(HEMT)能够获得很高的击穿电压、功率密度以及较高的工作频率,且开关损耗非常小。
传统的GaN器件多为平面结构,也有报道一些其他的结构如纳米沟道器件,纳米沟道器件有很多优势,如单条沟道中的电流相比传统器件小得多,所以散热要比传统器件好,可以很好的抑制传统异质结场效应晶体管中存在的自热效应,目前纳米沟道器件的实现方法大多是采用蚀刻的方式实现。
例如一种基于横向沟道调制的GaN基增强型场效应晶体管,自下而上包括衬底、AlN成核层、GaN缓冲层和AlGaN势垒层,AlGaN势垒层的两端设有源电极和漏电极,AlGaN势垒层和GaN缓冲层上均设有多条纳米线沟道,沟道之间通过隔离区隔开,AlGaN势垒层上设有凹槽栅电极等。该多条纳米线沟道是通过在AlGaN势垒层表面用电子束光刻机光刻源极与漏极之间的有源区,形成由条状隔离区图形和条状纳米线沟道图形按周期性排列的图案。这种方式会引入蚀刻损伤,对工艺的稳定性与重复性要求极高,同时,蚀刻损伤带来的沟道侧壁2DEG的耗尽,使得实际器件的沟道宽度无法得到有效的控制。
发明内容
本发明的主要目的在于克服现有技术中的GaN器件的纳米沟道通常采用蚀刻的方式实现,工艺要求极高且带来了蚀刻损伤的缺陷,提出一种氮化镓晶体管器件及其制备方法,通过氧化AlGaN的方式实现纳米沟道,无需蚀刻避免刻蚀引入的均匀性、重复性和损伤的风险,能有效减小寄生电容的影响,提高器件的频率特性。
本发明采用如下技术方案:
一种氮化镓晶体管器件,包括由下至上设置的衬底、GaN层、AlGaN层和源漏栅电极结构,源极、漏极设于AlGaN层两侧,栅极设于源极和漏极之间,其特征在于:该AlGaN层的上表面氧化形成若干相互平行且间隔分布的隔离道,隔离道长度方向一端与漏极相连,另一端与源极间隔设置,栅极设于AlGaN层上表面,其长度方向与隔离道相互垂直。
优选的,所述隔离道的宽度范围:1nm-1000nm。
优选的,所述隔离道的厚度大于1nm。
优选的,所述隔离道为Ga2O3。
优选的,还包括有钝化层,该钝化层沉积于所述AlGaN层表面,所述栅极贯穿钝化层与AlGaN层欧姆接触。
优选的,所述衬底为硅、碳化硅或蓝宝石。
优选的,所述GaN层包括有GaN缓冲层和GaN沟道层,GaN缓冲层生长于衬底表面,该GaN沟道生长于GaN缓冲层表面且与所述AlGaN层形成所述AlGaN/GaN异质结。
一种氮化镓晶体管器件的制备方法,其特征在于:包括如下步骤
1)在衬底上依次生长GaN层和AlGaN层,该GaN层和AlGaN层形成有AlGaN/GaN异质结;
2)在AlGaN层上定义有源区,在有源区两侧制作源极和漏极;
3)在AlGaN层表面定义出相互平行且间隔分布的隔离道区域,将隔离道区域热氧化成Ga2O3,未氧化部分被分隔为若干纳米沟道,该纳米沟道与隔离道为交替排列;
4)在AlGaN层表面定义出栅极区域,并制作栅极。
优选的,步骤3)中,沉积SiN或SiO2覆盖AlGaN层上表面,形成掩膜,刻蚀开口定义出隔离道区域,热氧化条件为:温度范围650℃-850℃,气体包括O2和N2,时间为20-30min。
优选的,步骤4)中,先采用光刻技术在纳米沟道和隔离道表面定义出栅极区域,再采用金属蒸发方法制备栅极金属,剥离完成后形成栅极。
由上述对本发明的描述可知,与现有技术相比,本发明具有如下有益效果:
1、本发明的器件,将AlGaN层局部热氧化形成若干平行间隔分布的隔离道,未氧化部分构成若干平行间隔分布的纳米沟道,该纳米沟道与隔离道为交替排列,避免刻蚀引入的均匀性、重复性和损伤的风险,能有效减小寄生电容的影响,提高器件的频率特性。
2、本发明的器件,源极和漏极之间热氧化形成的纳米沟道,单条沟道中的电流相比穿传统器件小得多,所以散热要比传统器件好,可以很好的抑制传统异质结场效应晶体管中存在的自热效应,同时源极附近的GaN和AlGaN并未被氧化,使得器件在工作状态下有更大的电流驱动能力。
3、本发明的方法,采用热氧化工艺在AlGaN层上制作隔离道和纳米沟道,无需进行刻蚀,工艺流程更为简单,减少刻蚀损伤,且改善器件内部的电场分布,形成一种调控器件内部电场的GaN器件技术,提高器件的击穿电压,抑制了电流崩塌。
4、本发明还设置有钝化层,用于保护EPI表面,减小漏电、降低界面太、增大栅压摆幅等。
附图说明
图1为本发明结构图(无钝化层);
图2为本发明俯视图(无钝化层);
图3为本发明剖视图(无钝化层);
图4为本发明剖视图(有钝化层);
图5为本发明方法流程图;
其中:
10、衬底,20、GaN层,30、AlGaN层,31、纳米沟道,32、隔离道,40、钝化层,50、源极,60、漏极,70、栅极。
以下结合附图和具体实施例对本发明作进一步详述。
具体实施方式
以下通过具体实施方式对本发明作进一步的描述。
参见图1,本发明提出一种氮化镓晶体管器件,包括由下至上设置的衬底10、GaN层20、AlGaN层30和源漏栅电极结构,该GaN层20和AlGaN层30之间形成有AlGaN/GaN异质结,该源极50和漏极60与AlGaN层30欧姆接触,该AlGaN层30的源极50和漏极60之间局部热氧化形成若干平行间隔分布的隔离道32,隔离道32长度方向一端与漏极60相连,另一端与源极50间隔设置,栅极70设于AlGaN层30上表面,其长度方向与隔离道32相互垂直。其中,未氧化部分被分隔成平行间隔分布的纳米沟道31,该纳米沟道31与隔离道32为交替排列。
本发明中,衬底10、GaN层20和AlGaN层30构成的外延结构为传统的AlGaN/GaN的结构。该衬底10可采用硅、碳化硅或蓝宝石,衬底的厚度可根据需要设定,例如可为500μm,但不限于此。GaN层20的厚度大于AlGaN层30的厚度。
其中,GaN层20可以是单层结构,也可以是多层结构。例如:GaN层20包括有GaN缓冲层和GaN沟道层,GaN缓冲层生长于衬底表面,其厚度范围1.5μm~2μm,该GaN沟道生长于GaN缓冲层表面,其厚度范围80nm~120nm。该AlGaN层30作为势垒层可与GaN缓冲层形成AlGaN/GaN异质结。
源极50和漏极60位于AlGaN层30两侧,栅极70位于源极50和漏极60之间,可靠近源极50。其中,AlGaN层30两侧可以是器件左右两侧边缘或靠近边缘处。该栅极70、源极50和漏极60为采用金属材质制作的电极结构。
参见图2、图3,本发明中,AlGaN层30的源极50和漏极60之间局部热氧化成Ga2O3形成的隔离道32,该隔离道32表面与AlGaN层30未氧化部分的纳米沟道表面平齐,且交替分布。隔离道32和纳米沟道31为条状,若干隔离道32的长度可相同或不同,优选为相同。隔离道32的数量可根据器件的尺寸设置,不作限定。
由于AlGaN层30表面局部薄薄一层被氧化后,氧化处的二维电子气就会消失,因此隔离道32的厚度大于1nm,小于AlGaN层30的厚度。隔离道32的宽度大于1nm,优选为1nm-1000nm,其长度小于源极50和漏极60之间的距离。纳米沟道31的宽度可以是1nm到微米量级均可以,优选为1nm~1μm。纳米沟道31的长度可与隔离道32的长度相同或不同,其数量、厚度与隔离道32的数量和厚度等相关。
本发明中,源极50和漏极60之间热氧化后形成的纳米沟道32,单条沟道中的电流相比穿传统器件小得多,所以散热要比传统器件好,可以很好的抑制传统异质结场效应晶体管中存在的自热效应。隔离道32与源极50之间的间隔处并未被氧化,则使得器件在工作状态下有更大的电流驱动能力。
参见图4,本发明还可设置钝化层40,该钝化层40沉积于AlGaN层30表面(包括纳米沟道31表面和隔离道32表面)。栅极70贯穿钝化层与AlGaN层30欧姆接触以保护EPI表面,减小漏电、降低界面太、增大栅压摆幅等。
本发明还提出一种氮化镓晶体管器件制备方法,参见图5,用于制作上述的氮化镓晶体管器件,包括如下步骤:
1)在衬底上依次生长GaN层20和AlGaN层30,该GaN层20和AlGaN层30之间形成有AlGaN/GaN异质结。
具体的,GaN层20包括有GaN缓冲层和GaN沟道层,在特定的工艺条件下,先在衬底的表面生长GaN缓冲层,在GaN缓冲层表面生长GaN沟道层,而后,在GaN沟道层表面生长AlGaN层30。GaN沟道层和AlGaN势垒层形成AlGaN/GaN异质结,AlGaN/GaN异质结界面处可形成二维电子气。
采用离子注入平面隔离技术实现晶体管器件间隔离,或者也可采用台面隔离工艺实现。
2)在AlGaN层30上定义于出有源区,并采用高温欧姆技术在有源区两侧制作源极50和漏极60以分别与AlGaN层30欧姆接触。
该步骤中,先采用光刻技术定义出源极区域和漏极区域,再采用金属蒸发的方法制备欧姆金属,随后进行高温退火工艺使得金属与AlGaN/GaN异质结的二维电子气形成良好的欧姆接触。该步骤中,对AlGaN层30两侧进行光刻时,其刻蚀后凹槽或孔的深度到达AlGaN/GaN异质结处,以便于形成欧姆接触即可,不作限定。其中,AlGaN层30两侧可以是器件左右两侧边缘或靠近边缘处,源极50和漏极60还可以采用其他常规的工艺方法制作。
3)在AlGaN层30表面定义出相互平行且间隔分布的隔离道区域,将隔离道区域热氧化成Ga2O3,形成若干平行间隔分布的隔离道32,未氧化部分被分隔成纳米沟道31,该纳米沟道31与隔离道32为交替排列。
其中,可在AlGaN层30表面覆盖遮蔽层形成掩膜,刻蚀开口定义出隔离道区域,使得AlGaN层30的隔离道区域外露。采用热氧化工艺对外露的隔离道区域进行热氧化,即通过高温高压的炉管内通入氧气,使暴露出的隔离道区域的AlGaN氧化,并非掺杂。遮蔽层可选材料为SiN、SiO2,热氧化条件为:温度650℃~850℃,气体包括O2和N2,时间为20~30min。该步骤中,通过控制氧化的气体浓度、氧化时间以及遮蔽层形貌来调节氧化的宽度和厚度。
采用该步骤制作的隔离道32的厚度大于1nm,小于AlGaN层30的厚度。隔离道32的宽度大于1nm,优选为1nm~1000nm,其长度小于源极50和漏极60之间的距离。纳米沟道31的宽度可以是1nm到微米量级均可以,优选为1nm~1μm。
4)在AlGaN层30表面(包括纳米沟道31和隔离道32表面)定义出栅极区域,并制作栅极70。
该步骤中,先采用光刻技术在AlGaN层30表面定义出栅极区域,再采用金属蒸发方法制备栅极金属,剥离完成后形成栅极70。
本发明还可包括在AlGaN层30外露表面(隔离道32和纳米沟道31外露表面)沉积钝化层40的步骤。本发明通过氧化AlGaN的方式实现纳米沟道,无需蚀刻避免刻蚀引入的均匀性、重复性和损伤的风险,能有效减小寄生电容的影响,提高器件的频率特性。
上述仅为本发明的具体实施方式,但本发明的设计构思并不局限于此,凡利用此构思对本发明进行非实质性的改动,均应属于侵犯本发明保护范围的行为。
Claims (10)
1.一种氮化镓晶体管器件,包括由下至上设置的衬底、GaN层、AlGaN层和源漏栅电极结构,源极、漏极设于AlGaN层两侧,栅极设于源极和漏极之间,其特征在于:该AlGaN层的上表面氧化形成若干相互平行且间隔分布的隔离道,隔离道长度方向一端与漏极相连,另一端与源极间隔设置,栅极设于AlGaN层上表面,其长度方向与隔离道相互垂直。
2.如权利要求1所述的一种氮化镓晶体管器件,其特征在于:所述隔离道的宽度范围:1nm-1000nm。
3.如权利要求1所述的一种氮化镓晶体管器件,其特征在于:所述隔离道的厚度大于1nm。
4.如权利要求1所述的一种氮化镓晶体管器件,其特征在于:所述隔离道为Ga2O3。
5.如权利要求1所述的一种氮化镓晶体管器件,其特征在于:还包括有钝化层,该钝化层沉积于所述AlGaN层表面,所述栅极贯穿钝化层与AlGaN层欧姆接触。
6.如权利要求1所述的一种氮化镓晶体管器件,其特征在于:所述衬底为硅、碳化硅或蓝宝石。
7.如权利要求1所述的一种氮化镓晶体管器件,其特征在于:所述GaN层包括有GaN缓冲层和GaN沟道层,GaN缓冲层生长于衬底表面,该GaN沟道生长于GaN缓冲层表面且与所述AlGaN层形成所述AlGaN/GaN异质结。
8.一种如权利要求1至7中任意一项所述氮化镓晶体管器件的制备方法,其特征在于:包括如下步骤
1)在衬底上依次生长GaN层和AlGaN层,该GaN层和AlGaN层形成有AlGaN/GaN异质结;
2)在AlGaN层上定义有源区,在有源区两侧制作源极和漏极;
3)在AlGaN层表面定义出相互平行且间隔分布的隔离道区域,将隔离道区域热氧化成Ga2O3,未氧化部分被分隔为若干纳米沟道,该纳米沟道与隔离道为交替排列;
4)在AlGaN层表面定义出栅极区域,并制作栅极。
9.如权利要求8所述的一种氮化镓晶体管器件制备方法,其特征在于:步骤3)中,沉积SiN或SiO2覆盖AlGaN层上表面,形成掩膜,刻蚀开口定义出隔离道区域,热氧化条件为:温度范围650℃-850℃,气体包括O2和N2,时间为20-30min。
10.如权利要求8所述的一种氮化镓晶体管器件制备方法,其特征在于:步骤4)中,先采用光刻技术在纳米沟道和隔离道表面定义出栅极区域,再采用金属蒸发方法制备栅极金属,剥离完成后形成栅极。
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