CN113292039B - MEMS silicon-based cavity circulator/isolator circuit film layer structure and preparation method - Google Patents
MEMS silicon-based cavity circulator/isolator circuit film layer structure and preparation method Download PDFInfo
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- CN113292039B CN113292039B CN202110599002.7A CN202110599002A CN113292039B CN 113292039 B CN113292039 B CN 113292039B CN 202110599002 A CN202110599002 A CN 202110599002A CN 113292039 B CN113292039 B CN 113292039B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 59
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 59
- 239000010703 silicon Substances 0.000 title claims abstract description 59
- 238000002360 preparation method Methods 0.000 title abstract description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052737 gold Inorganic materials 0.000 claims abstract description 39
- 239000010931 gold Substances 0.000 claims abstract description 39
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052802 copper Inorganic materials 0.000 claims abstract description 32
- 239000010949 copper Substances 0.000 claims abstract description 32
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 230000000903 blocking effect Effects 0.000 claims abstract description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 19
- 239000010936 titanium Substances 0.000 claims description 19
- 229910052719 titanium Inorganic materials 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 17
- 229910052804 chromium Inorganic materials 0.000 claims description 14
- 239000011651 chromium Substances 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 230000037452 priming Effects 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 239000012528 membrane Substances 0.000 claims 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 238000003780 insertion Methods 0.000 abstract description 11
- 230000037431 insertion Effects 0.000 abstract description 11
- 238000004544 sputter deposition Methods 0.000 description 26
- 238000011056 performance test Methods 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000859 α-Fe Inorganic materials 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0009—Structural features, others than packages, for protecting a device against environmental influences
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
Abstract
The invention discloses a circuit film structure of a MEMS silicon-based cavity circulator/isolator, which belongs to the field of microwave integrated devices, and comprises a gold film, a copper film, a tantalum nitride load film, a bottoming film, an isolation film and a high-resistance silicon layer from top to bottom, wherein a blocking film is preferably arranged between the gold film and the copper film; the invention also discloses a preparation method of the circuit film structure; compared with the prior art, the circuit film structure can reduce the insertion loss of the MEMS silicon-based cavity circulator/isolator device by 0.2-0.3dB, and meets the low-loss requirement of the MEMS silicon-based cavity circulator/isolator device application.
Description
Technical Field
The invention relates to the field of microwave integrated devices, in particular to a MEMS silicon-based cavity circulator/isolator circuit film structure and a preparation method thereof.
Background
The microwave ferrite circulator/isolator is an indispensable key device of various radar systems, is mainly used for solving series of problems of inter-stage isolation, impedance matching, antenna receiving and transmitting sharing and the like of the microwave system, and can greatly improve tactical performance of the radar system. The circulator loss is closely related to the radar system performance, and the lower the loss is, the farther the detection distance of the radar is. At present, the MEMS silicon-based cavity circulator has the advantages of good device performance, small size and mass production. Wherein, the structure of the metal film circuit manufactured on the high-resistance silicon wafer has close relation with the insertion loss of the circulator/isolator.
The microstrip circuit film structure adopted by the existing MEMS silicon-based cavity circulator is generally a chromium/gold structure, the microstrip circuit film structure adopted by the isolator is generally a chromium/tantalum nitride/gold structure, and the advantages of the chromium/gold, chromium/tantalum nitride/gold structure are that the technology is simple, the adhesion force with silicon is easy to control, but the same has larger problems, namely the insertion loss of the device is larger, and the cost is relatively higher. The main reason for the large loss is that the resistivity of gold is relatively high, the conductor loss is large, in addition, the film structure has the problem that the gold layer diffuses into silicon during high-temperature hot-pressing bonding, so that the resistivity of high-resistance silicon is reduced, the resistive loss of silicon is increased, and the insertion loss of a device is increased.
Therefore, for the above reasons, it is highly desirable to provide a circuit film structure more suitable for the MEMS silicon-based cavity circulator/isolator, and further reduce the insertion loss of the MEMS silicon-based cavity circulator/isolator.
Disclosure of Invention
One of the objectives of the present invention is to provide a MEMS silicon-based cavity circulator/isolator circuit film structure to solve the above-mentioned problems.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: a MEMS silicon-based cavity circulator/isolator circuit film structure sequentially comprises a gold film layer, a copper film layer, a tantalum nitride load film layer, a bottoming film layer, an isolation film layer and a high-resistance silicon layer from top to bottom.
As a preferable technical scheme: and a blocking film layer is arranged between the gold film layer and the copper film layer.
As a preferable technical scheme: the priming film layer is one of chromium, titanium or tungsten, and has a thickness of 10-100nm.
As a preferable technical scheme: the isolating film layer is silicon dioxide with the thickness of 180-400nm.
As a preferable technical scheme: the isolating film layer is made of titanium or tungsten and has the thickness of 10-100nm.
As a preferable technical scheme: the thickness of the gold film layer is 100-500nm; the thickness of the copper film is 1000-4000nm.
As a preferable technical scheme: the barrier film layer is one of chromium, titanium and nickel, and has a thickness of 10-100nm.
The second purpose of the invention is to provide a preparation method of the MEMS silicon-based cavity circulator/isolator circuit film structure, which adopts the technical scheme that the preparation method comprises the following steps:
(1) Uniformly oxidizing a silicon dioxide film or evaporating a metal isolation layer film on the front side and the back side of the high-resistance silicon; before manufacturing the device, performing isolation film covering treatment on the high-resistance silicon to prevent the high Wen Shijin layer from diffusing into the silicon;
(2) Setting a bottom film layer;
(3) Placing the silicon wafer into a box-type furnace for vacuum annealing treatment;
(4) A tantalum nitride load film layer is arranged on the bottom film layer;
(5) A copper film layer is arranged on the tantalum nitride load film layer;
(6) A barrier film layer is arranged on the copper film layer;
(7) A gold film layer is arranged on the barrier film layer;
(8) Patterning by photoetching;
(9) And electroplating to thicken the gold film.
As a preferable technical scheme: the annealing temperature in the step (3) is 200-400 ℃ and the annealing time is 0.5-1.5 hours.
As a preferable technical scheme: the backing film layer, the tantalum nitride load film layer, the copper film layer, the barrier film layer and the gold film layer are all arranged by adopting a magnetron sputtering method.
Compared with the prior art, the invention has the advantages that: firstly, uniformly oxidizing a silicon dioxide film or depositing a barrier layer film on the front and back sides of high-resistance silicon to prevent a gold layer or a copper layer from diffusing into silicon at high temperature, and then sequentially manufacturing a priming layer, a load, copper, a barrier layer and a gold layer structure; metallic copper with lower resistivity (copper 1.75X10) -8 Omega.m, gold 2.4X10 -8 Omega.m) uses copper/gold structure to replace all-gold structure, can reduce the conductor loss of the whole circuit and reduce the loss of devices, wherein the barrier film layer between copper and gold can block the mutual permeation of gold layer and copper layer at high temperature, and ensures the stability of copper/gold structure. Compared with the prior art, the circuit film structure can reduce the insertion loss of the MEMS silicon-based cavity circulator/isolator device by 0.2-0.3dB, and meets the low-loss requirement of the MEMS silicon-based cavity circulator/isolator device application.
Drawings
FIG. 1 is a schematic structural diagram of embodiment 1 of the present invention;
fig. 2 is the results of an 8-12GHz device electrical performance test of example 1 (ilmax=0.50 dB);
fig. 3 is the electrical performance test results (ilmax=0.7 dB) of the 8-12GHz chromium/tantalum nitride/copper/gold MEMS device of example 1;
fig. 4 is the results of an 8-12GHz device electrical performance test of example 2 (ilmax=0.52 dB);
fig. 5 is the electrical performance test results (ilmax=0.75 dB) of the 8-12GHz chromium/tantalum nitride/gold MEMS device of example 2.
In the figure: 1. a gold film layer; 2. a barrier film layer; 3. a copper film layer; 4. a tantalum nitride loading film layer; 5. backing film layer; 6. an isolation film layer; 7. and a high-resistance silicon layer.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
Example 1:
referring to fig. 1, a MEMS silicon-based cavity circulator/isolator circuit film structure sequentially comprises a gold film layer 1, a barrier film layer 2 (titanium film), a copper film layer 3, a tantalum nitride load film layer 4, a priming film layer 5 (chromium film), an isolation film layer 6 (silicon dioxide film) and a high-resistance silicon layer 7 from top to bottom;
the preparation method comprises the following steps:
(1) Marking and cleaning the two high-resistance silicon layers 7;
(2) Uniformly oxidizing a silicon dioxide film with the thickness of 300nm on the front side and the back side of the high-resistance silicon layer 7 to serve as an isolation film layer 6;
(3) Sputtering a layer of metal chromium film by magnetron sputtering as a backing film layer 5, sputtering at room temperature with sputtering power of 180W and chromium film thickness of 30nm;
(4) Placing the silicon wafer into a box furnace for vacuum annealing treatment, wherein the annealing temperature is 250 ℃, and the annealing time is 1 hour;
(5) Sputtering a tantalum nitride load film layer 4 on the chromium layer, wherein the sputtering temperature is 300 ℃, the sputtering power is 180W, and the thickness of the tantalum nitride film is 600nm;
(6) Sputtering a copper film layer 3 on the tantalum nitride load film layer 4, wherein the sputtering temperature is 400 ℃, the sputtering power is 900W, and the thickness of the copper film layer 3 is 3000nm;
(7) Sputtering a titanium film on the copper film layer 3 to serve as a barrier film layer 2, sputtering at room temperature, wherein the sputtering power is 180W, and the thickness of the titanium film is 10nm;
(8) Sputtering a gold film layer 1 on the titanium film, sputtering at room temperature, wherein the sputtering power is 200W, and the thickness of the gold film is 200nm; the method comprises the steps of carrying out a first treatment on the surface of the
(9) Patterning by photoetching;
(10) Electroplating to thicken the gold film, wherein the thickness of the gold film is 4000nm;
(11) And performing thermal compression bonding on the two wafers, performing deep silicon etching after bonding, and scribing to complete device assembly.
By adopting the film structure, the electrical performance of the assembled 8-12GHz MEMS silicon-based cavity isolator device is tested, and as a result, the single-section device insertion loss ILMAX=0.5 dB is lower by 0.2dB than that of the MEMS isolator with the same frequency band chromium/tantalum nitride/copper/gold structure, as shown in figures 2 and 3.
Example 2:
the MEMS silicon-based cavity circulator/isolator circuit film structure sequentially comprises a gold film layer 1, a barrier film layer 2 (titanium film), a copper film layer 3, a tantalum nitride load film layer 4, a priming film layer 5 (titanium film), an isolation film layer 6 (silicon dioxide film) and a high-resistance silicon layer 7 from top to bottom;
the preparation method comprises the following steps:
(1) Marking and cleaning the two high-resistance silicon layers 7;
(2) Uniformly oxidizing a 180nm thick silicon dioxide film on the front and back sides of the high-resistance silicon layer 7;
(3) Sputtering a layer of metal titanium film by magnetron sputtering as a backing film layer 5, sputtering at room temperature with sputtering power of 180W and thickness of the titanium film of 50nm;
(4) Sputtering a copper film on the titanium film at 400 ℃ with 900W sputtering power and 4000nm film thickness;
(5) Sputtering a layer of titanium film on the copper film, sputtering at room temperature, wherein the sputtering power is 180W, and the thickness of the titanium film is 15nm;
(6) Sputtering a gold film on the titanium film, sputtering at room temperature, wherein the sputtering power is 200W, and the thickness of the gold film is 250nm; the method comprises the steps of carrying out a first treatment on the surface of the
(7) Patterning by photoetching;
(8) Electroplating to thicken the gold film, wherein the thickness of the gold film is 2500nm;
(9) And performing thermal compression bonding on the two wafers, performing deep silicon etching after bonding, and scribing to complete device assembly.
By adopting the film structure, the electrical performance of the assembled 8-12GHz MEMS silicon-based isolator device is tested, and as a result, the single-section device insertion loss ILMAX=0.52 dB is lower than the loss of the MEMS isolator with the same frequency band chromium/gold structure by 0.23dB, as shown in figures 4 and 5.
Example 3
Compared with the embodiment 2, only a metal titanium layer which is formed by uniformly evaporating a layer of 50nm on the front side and the back side of the high-resistance silicon layer 7 in the step (2) is adopted, and the rest is the same as the embodiment 1, and the electric performance test is carried out on the assembled 8-12GHz MEMS silicon-based isolator device by adopting the prepared film structure, so that the single-section device insertion loss ILMAX=0.58 dB is lower than the loss of the MEMS isolator with the same frequency band chromium/gold structure by 0.17dB.
Comparative example 1:
this comparative example was compared with example 2, in which only the barrier film layer 2 was not provided between the gold film layer 1 and the copper film layer 3, and the rest was identical to example 2, and as a result, an electrical performance test was performed on the assembled 8-12GHz MEMS silicon-based isolator device, with the result that its single-segment device insertion loss ilmax=0.75 dB.
The above comparative examples demonstrate that: the barrier film layer 2 is arranged between the gold film layer 1 and the copper film layer 3, so that high-temperature Shi Tong gold infiltration can be prevented, and the loss of the isolator is reduced.
Comparative example 2
This comparative example was compared with example 2, except that the isolation film layer 6 was not provided, and the rest was the same as example 2, and as a result, an electrical performance test was performed on the assembled 5-13GHz MEMS silicon-based cavity circulator device, with the result that its single-segment device insertion loss ilmax=0.72 dB.
The above comparative examples demonstrate that: the high-resistance silicon is subjected to isolation film covering treatment before the device is manufactured, and the high Wen Shijin layer can be prevented from diffusing into the silicon, so that the loss of the isolator is reduced.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (9)
1. A MEMS silicon-based cavity circulator/isolator circuit film structure is characterized in that: the high-resistance silicon nitride film comprises a gold film layer, a copper film layer, a tantalum nitride load film layer, a bottom film layer, an isolation film layer and a high-resistance silicon layer from top to bottom in sequence; and a blocking film layer is further arranged between the gold film layer and the copper film layer, wherein the isolating film layer is used for blocking the high Wen Shijin film layer from diffusing to the high-resistance silicon layer, and the blocking film layer is used for blocking the gold film layer and the copper film layer from mutually penetrating at high temperature.
2. The MEMS silicon-based cavity circulator/isolator circuit membrane structure of claim 1, wherein: the priming film layer is one of chromium, titanium or tungsten, and has a thickness of 10-100nm.
3. The MEMS silicon-based cavity circulator/isolator circuit membrane structure of claim 1, wherein: the isolating film layer is silicon dioxide with the thickness of 180-400nm.
4. The MEMS silicon-based cavity circulator/isolator circuit membrane structure of claim 1, wherein: the isolating film layer is made of titanium or tungsten and has the thickness of 10-100nm.
5. The MEMS silicon-based cavity circulator/isolator circuit membrane structure of claim 1, wherein: the thickness of the gold film layer is 100-500nm; the thickness of the copper film is 1000-4000nm.
6. The MEMS silicon-based cavity circulator/isolator circuit membrane structure of claim 1, wherein: the barrier film layer is one of chromium, titanium and nickel, and has a thickness of 10-100nm.
7. The method for preparing the MEMS silicon-based cavity circulator/isolator circuit film structure of any one of claims 1 to 6, comprising the steps of:
(1) Uniformly oxidizing a silicon dioxide film or evaporating a metal isolation layer film on the front side and the back side of the high-resistance silicon;
(2) Setting a bottom film layer;
(3) Placing the silicon wafer into a box-type furnace for vacuum annealing treatment;
(4) A tantalum nitride load film layer is arranged on the bottom film layer;
(5) A copper film layer is arranged on the tantalum nitride load film layer;
(6) A barrier film layer is arranged on the copper film layer;
(7) A gold film layer is arranged on the barrier film layer;
(8) Patterning by photoetching;
(9) And electroplating to thicken the gold film.
8. The method according to claim 7, wherein: the annealing temperature in the step (3) is 200-400 ℃ and the annealing time is 0.5-1.5 hours.
9. The method according to claim 7, wherein: the backing film layer, the tantalum nitride load film layer, the copper film layer, the barrier film layer and the gold film layer are all arranged by adopting a magnetron sputtering method.
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