CN105448971B - A kind of semiconductor devices and preparation method thereof and electronic device - Google Patents

A kind of semiconductor devices and preparation method thereof and electronic device Download PDF

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Publication number
CN105448971B
CN105448971B CN201410441304.1A CN201410441304A CN105448971B CN 105448971 B CN105448971 B CN 105448971B CN 201410441304 A CN201410441304 A CN 201410441304A CN 105448971 B CN105448971 B CN 105448971B
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collecting zone
collector
characterized
formed
device wafers
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CN201410441304.1A
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CN105448971A (en
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陈福成
向阳辉
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中芯国际集成电路制造(上海)有限公司
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Abstract

The present invention provides a kind of semiconductor devices and preparation method thereof and electronic device, the production method include: offer device wafers, and the device wafers include substrate and the Facad structure for being formed in substrate face;Support wafer is provided, is temporarily bonded in the front of the support wafer and the device wafers by adhesive layer;The back side of the device wafers is carried out thinned;Collecting zone is formed at the back side of the device wafers;Collector is formed on the surface of the collecting zone, wherein the collector is the alloy that film-forming temperature is lower than 200 DEG C;Solution bonding is carried out, so that the device wafers and the support wafer separate.Production method according to the present invention, 200 DEG C of collector is lower than using film-forming temperature, while not needing Alloying Treatment, and good Ohmic contact between collector and collecting zone can be realized.Production cost can be reduced to avoid expensive Taiko wafer is used, guarantee the safe transmission of device wafers without there is the problem of fragmentation, and then raising yields.

Description

A kind of semiconductor devices and preparation method thereof and electronic device

Technical field

The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof and electronics Device.

Background technique

In semiconductor technology, insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, Abbreviation IGBT) the compound full-control type voltage that is made of double pole triode (BJT) and insulating gate type field effect tube (MOSFET) Drive-type power semiconductor has the high input impedance and power transistor (i.e. huge transistor, abbreviation GTR) of MOSFET concurrently Low conduction voltage drop of both advantage, therefore, IGBT is widely used as a kind of necessary switching device in frequency converter In the circuit structures such as inverter.

For the purpose of reducing energy loss and improving thermal diffusivity, generally require to carry out IGBT device it is thinned, however it is brilliant Thinner its of circle transmits between different processes and is just easier to chipping and deformation in process, has at present for thinned wafer Two kinds of processing methods: one is Taiko wafer (Wafer) methods of Disco;Taiko grinding technics mode is grinding for thin silicon wafer One of mill mode, its main feature is that only grinding silicon chip central part, and stay the region of 3mm-5mm not grind in silicon chip edge, from And support ring much one thicker than device silicon wafer thickness is formed in silicon chip edge, so that thin silicon wafer can be in subsequent biography Send, manufacture and carry in deformation occurs and rupture.However the expense of such method is relatively high, will increase production cost.

Another method is the method for interim bonding/Xie Jianhe (temporary bonding/de-bonding);But For such method when making double-side technology on thinned silicon wafer, technology difficulty is very big, especially the overleaf alloying system of metal Cheng Shi, temperature is excessively high, may cause adhesive (glue) failure of positive interim bonding (Temporary Bonding), leads Cause cannot operate wafer.

Therefore, in order to solve the above-mentioned technical problem, it is necessary to the production method for proposing a kind of new semiconductor devices.

Summary of the invention

A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.

In order to overcome the problems, such as that presently, there are the embodiment of the present invention one provides a kind of production method of semiconductor devices, packet It includes:

Device wafers are provided, the device wafers include substrate and the Facad structure for being formed in substrate face;

Support wafer is provided, the front of the support wafer and the device wafers is carried out by ephemeral key by adhesive layer It closes;

The back side of the device wafers is carried out thinned;

Collecting zone is formed at the back side of the device wafers;

Collector is formed on the surface of the collecting zone, wherein the collector is the alloy that film-forming temperature is lower than 200 DEG C;

Solution bonding is carried out, so that the device wafers and the support wafer separate.

Further, the material of the collector is selected from Cr/Au or Cr/Ag/Au.

Further, further include the steps that forming drift region in the substrate before forming the collecting zone.

It further, further include being formed to delay between the drift region and the collecting zone before forming the collecting zone The step of rushing area.

Further, the drift region and the collecting zone have different doping types, the collecting zone and the buffering Area has different doping types.

Further, the drift region is lightly doped for N-type, and the collecting zone is p-type heavy doping, and the buffer area is N-type weight Doping.

Further, further comprising the steps of before forming the collector:

Ti metal layer is formed on the surface of the collecting zone;

It is made annealing treatment;

Prerinse is carried out to the device wafers.

Further, the annealing is that laser annealing is handled.

Further, the Ti metal layer with a thickness of 200~2000 angstroms.

Further, the production method does not include the steps that carrying out Alloying Treatment to the collector.

Further, the thickness range of the device wafers is 50~200 μm after being thinned.

Second embodiment of the present invention provides a kind of semiconductor devices, comprising:

Substrate and the Facad structure for being formed in the substrate face;

It is formed with collecting zone at the back side of the substrate, collector is formed on the surface of the collecting zone, wherein institute State the alloy that current collection extremely film-forming temperature is lower than 200 DEG C.

Further, the material of the collector is selected from Cr/Au or Cr/Ag/Au.

Further, Alloying Treatment is not carried out to it after forming the collector.

Further, it is formed with buffer area above the collecting zone, is formed with drift region above the buffer area.

Further, the semiconductor devices is insulated gate bipolar transistor.

The embodiment of the present invention three provides a kind of electronic device, including above-mentioned semiconductor devices.

In conclusion production method according to the present invention, 200 DEG C of collector is lower than using film-forming temperature, is not required to simultaneously Alloying Treatment is wanted, good Ohmic contact between collector and collecting zone can be realized.It can be expensive to avoid using Taiko wafer reduces production cost.It is not in gluing at high temperature in addition, due to the step of not having to using high-temperature alloy The problem of layer failure, support wafer is still within bond styles with the device wafers after being thinned, it is ensured that the peace of device wafers Full transmission improves yields without there is the problem of fragmentation.

Detailed description of the invention

Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair Bright embodiment and its description, principle used to explain the present invention.

In attached drawing:

Fig. 1 shows the process flow chart of the successively implementation steps of method according to prior art;

The method that Fig. 2A -2H shows according to embodiments of the present invention one successively implements the diagrammatic cross-section of obtained device;

Fig. 3 shows the flow chart of the successively implementation steps of method in the embodiment of the present invention one;

Fig. 4 shows the diagrammatic cross-section of the IGBT device of the embodiment of the present invention two.

Specific embodiment

In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into Row description.

It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end Same reference numerals indicate identical element.

It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/ Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion Part, area, floor or part are represented by second element, component, area, floor or part.

Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its It is orientated) and spatial description language as used herein correspondingly explained.

The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation, The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute There is combination.

In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention There can also be other embodiments.

Existing IGBT backside process is described further with reference to Fig. 1.

Firstly, step 1, provides the device wafers for having completed front processing procedure, front processing procedure includes successively in substrate face The formation base area P+, N+ emitter region, grid oxic horizon, grid and emitter and etc.;

Step 2, support wafer is provided, by adhesive layer (glue), device wafers and support wafer are temporarily bonded;

Step 3, back Taiko grinding is carried out, device wafers are thinned;

Step 4, light shield is formed at the device wafers back side, and successively carries out N-type ion injection and P-type ion injection respectively, To form P+ collecting zone and N-type buffer area;

Step 5, deposited metal Ti layers on the surface of P+ collecting zone;

Step 6, laser annealing step is carried out, with the ion that activating appts backside of wafer is injected, while can also make part Ti Atom diffuses into collecting zone surface and forms titanium silicide;

Step 7, carry out prerinse step using the first standard solution SC1, with remove Ti layer of the metal on collecting zone surface with Titanium silicide;

Step 8, solution bonding, removal support wafer are carried out;

Step 9, in device wafers backside deposition metal layer as back electrode, the material of back electrode is Al/Ti/NiV/Ag, Wherein Al is ohmic contact resistance, and simple Al layer deposition can also be replaced by Direct precipitation Al and Si alloy, and Ti is NiV's Barrier layer, NiV be with data area metal, Ag be NiV protective layer, prevent NiV from aoxidizing;

Step 10, alloying technology is carried out, to reduce the contact resistance and resistance alloys of Al and Si substrate;

Step 11, igbt chip is installed;

Step 12, soldered ball is dripped.

Current IGBT back metal generally uses Al/Ti/NiV/Ag, and wherein Al is ohmic contact resistance, and Ti is The barrier layer of NiV, NiV be with data area metal, Ag be NiV protective layer, prevent NiV from aoxidizing, this four layers of metals, film forming temperature Degree is high, and 300 degree or more of temperature is needed to carry out alloying, to reduce the contact resistance and resistance alloys of Al and Si substrate.

In order to increase the operability that thick wafer is thinned, generally require to pass through adhesive layer ephemeral key in the front of device wafers Unification support wafer, and adhesive layer heat-resisting quantity is poor, need to control technological temperature in the making technology of back at 250 DEG C hereinafter, Adhesive layer could will not be made to fail.

But at present when making double-side technology on thinned silicon wafer, technology difficulty is very big, especially overleaf metal When alloying processing procedure, temperature is excessively high, may cause the adhesive (glue) of positive interim bonding (Temporary Bonding) Failure, leads to that wafer cannot be operated.If using Taiko wafer at this moment, wafer is carried out normally although can guarantee Operation, but its expense is relatively high.

Presence in view of the above problems, the invention proposes a kind of production methods of new semiconductor devices.

Embodiment one

In the following, the method for the embodiment of the present invention is described in detail referring to Fig. 2A-Fig. 2 H and Fig. 3.

The method that wherein Fig. 2A-Fig. 2 H shows the embodiment of the present invention successively implements the diagrammatic cross-section of obtained device; The process flow chart that the method that Fig. 3 shows the embodiment of the present invention is successively implemented.

Firstly, as shown in Figure 2 A, providing device wafers 20, the device wafers include substrate 200, and the substrate 200 can Think following at least one of the material being previously mentioned: silicon (SSOI), insulation is laminated on insulator in silicon, silicon-on-insulator (SOI) SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. are laminated on body.Further, the substrate can be with For N-type substrate or P type substrate.Substrate can also be lightly doped for N-type.

Isolation structure is formed in the substrate, and the isolation structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure.The channel layer of various traps (well) structure and substrate surface is also formed in the semiconductor substrate.Also Facad structure including being formed in the substrate face, such as base area, emitter region, grid oxic horizon, grid and emitter 201.

Then, as shown in Figure 2 B, support wafer 30 is provided, is temporarily bonded, by the support wafer 30 and device The positive engagement of wafer 20;The back side of the device wafers 20 is carried out thinned.

Specifically, the support wafer 30 can be Silicon Wafer, glass or ceramic material.For playing branch to device wafers Support effect, operates convenient for the back side to device wafers.

In one example, the support wafer and device wafers front are temporarily bonded by adhesive layer 202.Glue Adhesion coating 202 can be but be not limited to high-molecular organic material or can ultraviolet denaturation organic material.

The back side of the device wafers 20 is carried out thinned.In this step, the thining method can select this field Common method, such as can be using the methods of mechanical lapping, chemically mechanical polishing (CMP), chemical attack, plasma etching. Optionally, the thickness range of device wafers 20 is 50~200 μm after being thinned.

Then, as shown in Figure 2 C, collecting zone 204 is formed at the back side of device wafers 20.

It in one example, further include that ion implanting is carried out to 200 back of substrate before forming the collecting zone 204, The step of drift region is formed in substrate 200 specifically first forms patterned photoresist in substrate back, with patterned Photoresist is that exposure mask carries out ion implanting, forms drift region in substrate, finally removes patterned photoresist.Optionally, institute Stating drift region is the drift region N-.

It illustratively, include: to form patterned photoetching in substrate back the step of 200 back side of substrate forms collecting zone Glue-line carries out ion implanting using the patterned photoresist layer as exposure mask, to form collecting zone 204 at the back side of substrate, The surface of middle collecting zone 204 is flushed with the back surfaces of substrate, finally removes patterned photoresist layer.Collecting zone and drift region It is lightly doped with different doping types, such as drift region for N-type, collecting zone is p-type heavy doping.

Further, if the predetermined IGBT device that formed is punch device, need to also between collecting zone 204 and drift region shape At buffer area 203, it can be realized by way of carrying out ion implanting to substrate back, pass through the energy hole ion of control injection The depth of injection.Wherein, the buffer area 203 has different doping types from collecting zone 204, such as when collecting zone is p-type When heavy doping, buffer area can be N-type heavy doping.

Then, as shown in Figure 2 D, Ti metal layer 205 is formed on the surface of collecting zone 204, and is made annealing treatment.

The method for forming the Ti metal layer 205 can select any of deposition technique, such as various types of CVD (such as metallorganic CVD, pulse CVD), physical vapour deposition (PVD) (PVD), sputtering or plating etc..Optionally, the Ti metal layer With a thickness of 200~2000 angstroms.

The purpose made annealing treatment is to activate the ion of device wafers back side injection in abovementioned steps.In an example In, the annealing is that laser annealing is handled, with the ion injected in activating appts wafer.Annealing can also make simultaneously The surface that part Ti atom diffuses into collecting zone forms titanium-silicide alloy.

Then, as shown in Figure 2 E, prerinse is carried out to device wafers 20.Since laser annealing diffuses into part Ti atom Enter the surface of collecting zone and forms titanium silicide, and titanium silicide is more crisp, can have a negative impact to device, it is therefore desirable to it is gone It removes.In the present embodiment, the prerinse step is carried out using the first standard solution (SC1), to completely remove 204 surface of collecting zone Ti layers of metal and titanium silicide.

Then, as shown in Figure 2 F, collector 206 is formed on the surface of the collecting zone 204, wherein the collector 206 It is lower than 200 DEG C of alloy for film-forming temperature.

Optionally, the material of the collector is selected from the conjunction of Cr/Au or Cr/Ag/Au or other film-forming temperatures lower than 200 DEG C Gold.The method for forming the collector 206 can select any of deposition technique, such as various types of CVD (such as metals Organic C VD, pulse CVD etc.), physical vapour deposition (PVD) (PVD), sputtering or plating etc..By the film forming of collector in this present embodiment Temperature is lower than 200 DEG C, while not needing Alloying Treatment, and good Ohmic contact between collector and collecting zone can be realized. By the collector for selecting film-forming temperature low, production cost can be reduced to avoid expensive Taiko wafer is used.In addition, It is not in the problem of adhesive layer fails at high temperature, support due to the step of not having to using high-temperature alloy in this step Wafer is still within bond styles with the device wafers after being thinned, it is ensured that the safe transmission of device wafers is without the broken of appearance The problem of splitting.

Then, as shown in Figure 2 G, solution bonding is carried out, so that the device wafers and support wafer separate.

Specifically, the method that any solution bonding well known to those skilled in the art can be used, discrete device wafer and support Wafer, for example, high-temperature heating makes adhesive layer denaturation lose viscosity, then mechanically decoupled device wafer and support wafer.

Finally, as illustrated in figure 2h, installing device wafer, and soldered ball 207 is formed on collector 206.The formation of soldered ball 207 Any method well known to those skilled in the art can be used in method, is not specifically limited herein.

In conclusion production method according to the present invention, 200 DEG C of collector is lower than using film-forming temperature, is not required to simultaneously Alloying Treatment is wanted, good Ohmic contact between collector and collecting zone can be realized.It can be expensive to avoid using Taiko wafer reduces production cost.It is not in gluing at high temperature in addition, due to the step of not having to using high-temperature alloy The problem of layer failure, support wafer is still within bond styles with the device wafers after being thinned, it is ensured that the peace of device wafers Full transmission improves yields without there is the problem of fragmentation.

Embodiment two

It is described further with reference to IGBT device of the Fig. 4 to the embodiment of the present invention.

The embodiment of the present invention provides a kind of insulated gate bipolar transistor made of method in embodiment one, comprising:

Substrate 400 and it is formed in the positive Facad structure of the substrate 400.The substrate 400 can be mentioned by following At least one of material arrived: silicon (SSOI) is laminated on insulator, germanium is laminated on insulator for silicon, silicon-on-insulator (SOI) Silicon (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc..Further, the substrate 400 can also be N-type substrate Or P type substrate, substrate can also be lightly doped for N-type.

Isolation structure is formed in the substrate, and the isolation structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure.The channel layer of various traps (well) structure and substrate surface is also formed in the semiconductor substrate.Also Including being formed in the positive Facad structure of the substrate 400, such as base area, emitter region, grid oxic horizon, grid and emitter 401。

Collecting zone 402 is formed at the back side of the substrate 400.Further, it is formed in the top of the collecting zone 402 There is buffer area 403, is formed with drift region above the buffer area.Collecting zone and drift region have different doping types, Such as drift region is lightly doped for N-type, collecting zone is p-type heavy doping.The buffer area 402 has different mix from collecting zone 403 Miscellany type, such as when collecting zone is p-type heavy doping, buffer area can be N-type heavy doping.

It is formed with collector 404 on the surface of the collecting zone 402, wherein the collector 403 is that film-forming temperature is low In 200 DEG C of alloy.

Optionally, the material of the collector 404 is selected from Cr/Au or Cr/Ag/Au.

Illustratively, Alloying Treatment is not carried out to it after forming the collector 404.

In conclusion semiconductor device according to the invention, collector can be with collecting zone without Alloying Treatment Good contact is formed, therefore semiconductor devices of the invention has excellent Performance And Reliability.

Embodiment three

The present invention also provides a kind of electronic devices comprising above-mentioned semiconductor device.

Since the semiconductor devices for including has excellent Performance And Reliability, which equally has above-mentioned excellent Point.

The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD, Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, are also possible to have The intermediate products of above-mentioned semiconductor device, such as: the cell phone mainboard etc. with the integrated circuit.

The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by The appended claims and its equivalent scope are defined.

Claims (17)

1. a kind of production method of semiconductor devices, comprising:
Device wafers are provided, the device wafers include substrate and the Facad structure for being formed in substrate face;
Support wafer is provided, is temporarily bonded in the front of the support wafer and the device wafers by adhesive layer;
The back side of the device wafers is carried out thinned;
Collecting zone is formed at the back side of the device wafers;
Collector is formed on the surface of the collecting zone, wherein the collector is the alloy that film-forming temperature is lower than 200 DEG C, is not required to Alloying Treatment is carried out, can be achieved with good Ohmic contact between the collector and the collecting zone;
Solution bonding is carried out, so that the device wafers and the support wafer separate.
2. manufacturing method according to claim 1, which is characterized in that the material of the collector is selected from Cr/Au or Cr/ Ag/Au。
3. manufacturing method according to claim 1, which is characterized in that before forming the collecting zone further include described The step of drift region is formed in substrate.
4. production method according to claim 3, which is characterized in that further include in institute before forming the collecting zone State the step of buffer area is formed between drift region and the collecting zone.
5. production method according to claim 4, which is characterized in that the drift region and the collecting zone are with different Doping type, the collecting zone and the buffer area have different doping types.
6. production method according to claim 4, which is characterized in that the drift region is lightly doped for N-type, the collecting zone For p-type heavy doping, the buffer area is N-type heavy doping.
7. manufacturing method according to claim 1, which is characterized in that before forming the collector further include following step It is rapid:
Ti metal layer is formed on the surface of the collecting zone;
It is made annealing treatment;
Prerinse is carried out to the device wafers.
8. production method according to claim 7, which is characterized in that the annealing is that laser annealing is handled.
9. production method according to claim 7, which is characterized in that the Ti metal layer with a thickness of 200~2000 angstroms.
10. manufacturing method according to claim 1, which is characterized in that the production method does not include to the collector The step of carrying out Alloying Treatment.
11. manufacturing method according to claim 1, which is characterized in that the thickness range of the device wafers is after being thinned 50~200 μm.
12. a kind of semiconductor devices characterized by comprising
Substrate and the Facad structure for being formed in the substrate face;
It is formed with collecting zone at the back side of the substrate, is formed with collector on the surface of the collecting zone, wherein the collection Electrode is the alloy that film-forming temperature is lower than 200 DEG C, does not need to carry out Alloying Treatment, can be achieved with the collector and the collection Good Ohmic contact between electric area.
13. semiconductor devices according to claim 12, which is characterized in that the material of the collector be selected from Cr/Au or Cr/Ag/Au。
14. semiconductor devices according to claim 12, which is characterized in that after forming the collector not to its into Row Alloying Treatment.
15. semiconductor devices according to claim 12, which is characterized in that be formed with buffering above the collecting zone Area is formed with drift region above the buffer area.
16. semiconductor devices according to claim 12, which is characterized in that the semiconductor devices is insulated gate bipolar Transistor.
17. a kind of electronic device, which is characterized in that including such as described in any item semiconductor devices of claim 12-16.
CN201410441304.1A 2014-09-01 2014-09-01 A kind of semiconductor devices and preparation method thereof and electronic device CN105448971B (en)

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CN107452620B (en) * 2016-05-31 2019-12-24 上海微电子装备(集团)股份有限公司 IGBT silicon wafer back annealing method

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US6252158B1 (en) * 1998-06-16 2001-06-26 Canon Kabushiki Kaisha Photovoltaic element and solar cell module
CN101465301A (en) * 2007-12-21 2009-06-24 万国半导体股份有限公司 Wafer level chip scale packaging
CN102290595A (en) * 2011-06-24 2011-12-21 中国科学院上海微系统与信息技术研究所 An all-solid thin film lithium battery cycle-life and high manufacturing method

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JP4982948B2 (en) * 2004-08-19 2012-07-25 富士電機株式会社 Manufacturing method of semiconductor device

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US6252158B1 (en) * 1998-06-16 2001-06-26 Canon Kabushiki Kaisha Photovoltaic element and solar cell module
CN101465301A (en) * 2007-12-21 2009-06-24 万国半导体股份有限公司 Wafer level chip scale packaging
CN102290595A (en) * 2011-06-24 2011-12-21 中国科学院上海微系统与信息技术研究所 An all-solid thin film lithium battery cycle-life and high manufacturing method

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