CN113281634B - Chip testing equipment and chip testing process stacking or clamping checking method thereof - Google Patents
Chip testing equipment and chip testing process stacking or clamping checking method thereof Download PDFInfo
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- CN113281634B CN113281634B CN202110578262.6A CN202110578262A CN113281634B CN 113281634 B CN113281634 B CN 113281634B CN 202110578262 A CN202110578262 A CN 202110578262A CN 113281634 B CN113281634 B CN 113281634B
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- 238000012360 testing method Methods 0.000 title claims abstract description 598
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000005070 sampling Methods 0.000 claims description 62
- 239000000463 material Substances 0.000 claims description 32
- 238000007689 inspection Methods 0.000 claims description 28
- 230000002950 deficient Effects 0.000 claims description 15
- 239000013256 coordination polymer Substances 0.000 claims description 3
- 238000013100 final test Methods 0.000 description 134
- 238000001514 detection method Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000012361 intermediate testing Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2894—Aspects of quality control [QC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/01—Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/54—Testing for continuity
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- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses chip test equipment, in the FT test mode, if a chip identification reading module reads an identification in an FT mark register of a chip to be tested, which is placed in a test groove and used for finishing the open-short circuit test of the FT test, when the open-short circuit test module finishes the open-short circuit test of the FT test, the identification passes through an identification code, and a controller outputs stacking or clamping phenomenon occurrence information; when all test items of the FT test of the chip to be tested placed in the test groove are completed, if all the test items of the FT test of the chip to be tested pass, the controller controls the identification writing module to write a test passing identification code into the FT mark register of the chip, and if the FT test of the chip to be tested has a failure test item, the controller outputs test failing information. The invention also discloses a chip testing process stacking or clamping checking method of the chip testing equipment. The invention is convenient for timely finding out the chip stacking or clamping and convenient for follow-up tracking and checking whether the chip is the chip passing the FT test.
Description
Technical Field
The present invention relates to chip testing technology, and in particular, to a chip testing apparatus and a method for inspecting a chip test (FINAL TEST, or FT) process stack or card.
Background
Because of market demands, part of the chips are too thin or small in size, the chips are prone to stacking or jamming during the mechanized factory testing (FINAL TEST).
The stacking phenomenon, i.e. two chips are stacked up and down in a test seat (socket), can lead to that the chips positioned below in the test seat are actually tested twice, and the chips positioned above in the test seat are not actually tested, but are driven into the braid as test good products to flow into the market. The material-clamping phenomenon, i.e. a chip is clamped in the test seat, can lead to the chip to be tested continuously.
The current general material stacking phenomenon detection method is to monitor stacking through a hardware detection device (sensor), and when a product exists in a test seat of a tester, a gap between a pressing rod and the hardware detection device is reserved between the pressing rod and the product, and at the moment, the tester machine alarms for stacking.
The chinese patent application cn201911124364.X discloses a cn201911124364.X anti-stacking IC test device, as shown in fig. 1 to 4, the anti-stacking IC test device includes a rack, and a lifting and pressing device 20, a test seat 30, a main controller and an anti-stacking detecting device 42 mounted on the rack, where the test seat 30 has a test slot 31 for accommodating chips, the test seat 30 is located below the lifting and pressing device 20, the anti-stacking detecting device 42 detects the chip storage condition in the test slot 31 and detects the position of the lifting and pressing device 20, the main controller is electrically connected with the lifting and pressing device 20 and the anti-stacking detecting device 42, respectively, the main controller controls the lifting and pressing device 20 to load or load out chips on the test slot 31, the anti-stacking detecting device 42 detects that chips are stored in the test slot 31 and the lifting and pressing device 20 is in a state when leaving the chip taking position, and the main controller controls the anti-stacking IC test device according to the state, so that the chip test is completed and the chip is not stacked, if the chip is not stacked, the chip can not be continuously taken out, and the risk is avoided when the chip is not left in the chip taking operation. The anti-stacking IC test equipment judges whether chip stacking occurs in the test slot 31 or not according to the on-off state of the anti-stacking detection device 42 of hardware, and has high cost and complex structure.
Disclosure of Invention
The invention aims to solve the technical problem of providing chip testing equipment and a chip testing process stacking or clamping checking method thereof, which are convenient for a testing engineer to find out chip stacking or clamping in time and convenient for follow-up tracking and checking whether a chip passes the FT test.
In order to solve the technical problems, the chip test equipment provided by the invention comprises a test seat, an open-short circuit test module, an identification writing module, a chip identification reading module and a controller;
the test seat is provided with a test groove for accommodating a chip and is used for placing the chip to be detected;
The identification writing module is used for writing an identification into the FT mark register of the chip;
The open-short circuit test module is used for carrying out an open-short circuit test of FT test on the chip to be tested placed in the test groove;
The chip identification reading module is used for reading the identification in the FT mark register of the chip to be detected when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test slot and all test items of the FT test are completed;
The controller is used for outputting the occurrence information of the stacking or clamping phenomenon if the identification in the FT mark register of the chip to be detected, which is read by the chip identification reading module when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test slot, is a test passing identification code in the FT test mode;
The controller is used for controlling the identification writing module to write a test passing identification code into the FT mark register of the chip if all the test items of the FT test of the chip to be tested are passed when all the test items of the FT test of the chip to be tested placed in the test slot are finished in the FT test mode; if the FT test of the chip to be detected has a failure test item, outputting test failure information.
Preferably, before the FT test is started, the identification in the FT flag register of the chip to be tested is an initial identification code, and the test passing identification code is different from the initial identification code;
And the controller outputs information that no material stacking or material clamping occurs if the identification in the FT mark register of the chip to be detected is an initial identification code, which is read by the chip identification reading module when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test slot, in the FT test mode.
Preferably, in the EQC test mode, the controller reads, by the chip identifier reading module, an identifier in an FT flag register of a sampling test chip placed in the test slot when the sampling test chip completes an open-short test of the EQC test, and if the identifier is a test passing identifier, outputs FT test normal information; and if the test passing identification code is not the test passing identification code, outputting FT test missing test information.
Preferably, in the EQC test mode, when all test items of the FT test of the sampling test chip placed in the test slot are completed, if all test items of the EQC test of the sampling test chip pass, the controller controls the manipulator to take the sampling test chip from the test slot and place the sampling test chip in the good product box; and if the EQC test of the sampling inspection chip has a failure test item, the control manipulator takes the sampling inspection chip out of the test slot and places the sampling inspection chip in a defective bin.
Preferably, the chip testing process stacking or clamping checking method of the chip testing equipment comprises the following steps:
Firstly, enabling a test engineer to enable chip test equipment to enter an FT test mode, and carrying out open-short circuit test on a chip to be tested placed in a test groove through the open-short circuit test module;
the chip identification reading module is used for reading an identification in an FT mark register of a chip to be detected when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test groove;
thirdly, the chip identification reading module reads the identification in the FT mark register of the chip to be detected when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test slot, and if the test passes the identification code, the controller outputs the occurrence information of the material stacking or material clamping phenomenon; otherwise, performing the fourth step;
Fourthly, testing other test items of FT tests on the chip to be tested placed in the test groove by a test engineer;
Fifthly, when all test items of the FT test of the chip to be tested placed in the test slot are completed, if all the test items of the FT test of the chip to be tested pass, the controller controls the identification writing module to write a test passing identification code into the FT mark register of the chip; and if the FT test of the chip to be detected has a failure test item, the controller outputs test failure information.
Preferably, in the third step, when the controller outputs information of occurrence of material stacking or material clamping, the FT test is stopped, and the chip to be tested placed in the test slot is taken out and placed in the defective bin;
And fifthly, stopping the FT test when the controller outputs the test failing information, and taking out the chip to be detected placed in the test groove and placing the chip in a defective bin.
Preferably, in the fifth step, when all the test items of the FT test of the chip to be tested placed in the test slot are completed, if all the test items of the FT test of the chip to be tested pass, the controller controls the identification writing module to write a test passing identification code into the FT flag register of the chip, and controls the manipulator to take the chip to be tested from the test slot and place the chip in the good product box.
Preferably, in the first step, the identifier in the FT flag register of the chip to be tested is written as an initial identifier, and then the chip test device enters the FT test mode, and the open-short circuit test module performs the open-short circuit test on the chip to be tested placed in the test slot.
Preferably, in the first step, when the chip to be tested is subjected to CP test, the controller controls the identifier writing module to write an initial identifier into the FT flag register of the chip;
And step three, the chip identification reading module reads the identification in the FT mark register of the chip to be detected when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test slot, if the test passes the identification code, the controller outputs the occurrence information of the material overlapping or material clamping phenomenon, and if the test passes the identification code, the step four is performed.
Preferably, the initial identification code is oxFF and the test passes the identification code ox78.
Preferably, the method further comprises the steps of:
sixth, the test engineer makes the chip test equipment enter an EQC test mode, and takes the sampling inspection chip from the good product box and places the sampling inspection chip in the test groove;
seventhly, a test engineer performs open-short circuit test on the sampling test chip placed in the test slot through the open-short circuit test module;
the chip identification reading module reads an identification in an FT mark register of the sampling test chip when the sampling test chip placed in the test slot is subjected to the open-short test of the EQC test by the open-short test module;
A step nine of outputting FT test normal information by the controller if the test passes the identification code when the chip identification reading module reads the identification in the FT flag register of the sampling test chip when the sampling test chip placed in the test slot completes the open-short test of the EQC test by the open-short test module; otherwise, outputting FT test missing information;
test engineers test the test items of the EQC test on the sampling test chips placed in the test slots.
Preferably, in step nine, if the controller outputs the FT test missing information, the controller controls the manipulator to take the spot check chip from the test slot and place it in the defective bin.
Preferably, in step ten, when all test items of the EQC test of the spot check chip placed in the test slot are completed, if all test items of the EQC test of the spot check chip pass, the controller controls the manipulator to take the spot check chip from the test slot and place the spot check chip in the good product box; and if the EQC test of the sampling inspection chip has a failure test item, the control manipulator takes the sampling inspection chip out of the test slot and places the sampling inspection chip in a defective bin.
According to the chip testing equipment, the FT testing mode is entered during FT testing, after the open short testing module completes the open short testing, the identification in the FT identification register of the chip to be tested is read, whether the chip is overlapped or blocked is judged according to whether the identification in the FT identification register of the chip to be tested is a test passing identification code, chips with overlapped or blocked materials in FT (Final Test) testing processes can be timely screened out, testing engineers can be prompted to test grooves to generate the blocking or overlapping phenomena, timely processing is facilitated, chips which are not tested and chips damaged due to the occurrence of the overlapping or blocking phenomena are prevented from flowing into the market, the reliability of the chip testing process is improved, and follow-up tracking and checking of whether the chips are chips passing the FT testing are facilitated.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the following brief description of the drawings is given for the purpose of the present invention, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without the need for inventive work for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional anti-stacking IC test device;
FIG. 2 is a schematic diagram of a chip test apparatus according to the present invention;
fig. 3 is a flow chart of a method for inspecting a stack or a card during a chip test of the chip test apparatus of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
As shown in fig. 2, the chip test apparatus includes a test socket, an open-short circuit test module, an identification writing module, a chip identification reading module, and a controller;
the test seat is provided with a test groove for accommodating a chip and is used for placing the chip to be detected;
The identification writing module is used for writing an identification into the FT mark register of the chip;
the open short circuit test module is used for carrying out an open short circuit (FT) test on the chip to be tested placed in the test groove;
the chip identification reading module is used for reading the identification in the FT mark register of the chip to be detected when the open short circuit test module completes the open short circuit (open short) test of FT (Final Test) tests on the chip to be detected placed in the test slot and all test items of the FT test are completed;
The controller is used for outputting the occurrence information of the stacking or clamping phenomenon if the identification in the FT mark register of the chip to be detected, which is read by the chip identification reading module when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test slot, is a test passing identification code in the FT test mode;
The controller is used for controlling the identification writing module to write a test passing identification code into the FT mark register of the chip if all the test items of the FT test of the chip to be tested are passed when all the test items of the FT test of the chip to be tested placed in the test slot are finished in the FT test mode; if the FT test of the chip to be detected has a failure test item, outputting test failure information.
The chip testing process stacking or clamping checking method of the chip testing equipment, as shown in fig. 3, comprises the following steps:
firstly, enabling a test engineer to enable chip test equipment to enter an FT test mode, and carrying out open short test on a chip to be tested placed in a test groove through the open short test module;
the chip identification reading module is used for reading an identification in an FT mark register of a chip to be detected when the open-short circuit test module completes FT (Final Test) open-short circuit test of the chip to be detected placed in the test groove;
thirdly, the chip identification reading module reads the identification in the FT mark register of the chip to be detected when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test slot, and if the test passes the identification code, the controller outputs the occurrence information of the material stacking or material clamping phenomenon; otherwise, performing the fourth step;
Fourthly, testing other test items of FT tests on the chip to be tested placed in the test groove by a test engineer;
fifthly, when all test items of the FT test of the chip to be tested placed in the test slot are completed, if all the test items of the FT test of the chip to be tested pass, the controller controls the identification writing module to write a test passing identification code into the FT mark register of the chip; and if the FT test of the chip to be detected has a failure test item, the controller outputs test failure information.
Preferably, in the third step, when the controller outputs information of occurrence of material stacking or material clamping, the FT test is stopped, and the chip to be tested placed in the test slot is taken out and placed in the defective bin;
And fifthly, stopping the FT test when the controller outputs the test failing information, and taking out the chip to be detected placed in the test groove and placing the chip in a defective bin.
Preferably, in the fifth step, when all the test items of the FT test of the chip to be tested placed in the test slot are completed, if all the test items of the FT test of the chip to be tested pass, the controller controls the identification writing module to write a test passing identification code into the FT flag register of the chip, and controls the manipulator to take the chip to be tested from the test slot and place the chip in the good product box.
The chip test device of the first embodiment writes a test passing identification code into the FT flag register of the chip to be tested in the test slot when the last test item of the FT test flow is completed through program setting; firstly, a test engineer performs open short (open short) test on a chip to be tested placed in a test slot through an open short test module, and when the open short test module completes the open short (open short) test of the FT test on the chip to be tested placed in the test slot, a chip identification reading module reads an identification in an FT (short) mark register of the chip to be tested, if the identification in the FT mark register of the chip to be tested is a test passing identification code, the phenomenon of material stacking or material clamping is indicated to occur, namely the chip is subjected to the FT test; if the identification in the FT flag register of the chip to be detected is not the test passing identification code, the phenomenon of material overlapping does not occur, namely the chip is not subjected to FT test.
According to the chip testing equipment of the first embodiment, the FT testing mode is entered during FT testing, after the open short circuit testing module completes the open short circuit (open short) testing, the identification in the FT identification register of the chip to be tested is read, whether the chip is overlapped or blocked is judged according to whether the identification in the FT identification register of the chip to be tested passes through the identification code, chips which are overlapped or blocked in the FT (Final Test) testing process can be timely screened out, a testing engineer can be prompted that the chip is blocked or overlapped in the testing groove, timely processing is facilitated, chips which are not tested and chips damaged due to the occurrence of the overlapping or blocking phenomenon are prevented from flowing into the market, the reliability of the chip testing process is improved, and follow-up tracking and checking of whether the chips pass through the FT testing are facilitated.
Example two
Based on the chip test device of the first embodiment, the to-be-tested chip is identified as an initial identification code in the FT flag register before starting FT (Final Test) test, and the test is distinguished from the initial identification code by the identification code;
and the controller is used for indicating that the phenomenon of material overlapping or material clamping does not occur and outputting information of the phenomenon of material overlapping or material clamping does not occur if the identification in the FT mark register of the chip to be detected, which is read by the chip identification reading module when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test groove, is an initial identification code in the FT test mode.
In the first step, the identification in the FT flag register of the chip to be tested is written as the initial identification code, then the chip test equipment enters the FT test mode, and the open-short circuit test module is used for carrying out the open-short circuit test on the chip to be tested which is placed in the test slot.
In the first step, when a chip to be tested is subjected to a CP (Circuit testing or intermediate testing) test, a controller controls the identification writing module to write an initial identification code into an FT flag register of the chip;
And step three, the chip identification reading module reads the identification in the FT mark register of the chip to be detected when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test slot, if the test passes the identification code, the controller outputs the information of occurrence of material overlapping or material clamping phenomenon, and the step four is performed.
Preferably, the initial identification code is oxFF and the test passes the identification code ox78.
The chip test apparatus of the second embodiment makes the identification in the FT flag register of the chip to be tested be the initial identification code before starting FT (Final Test) test; when the open short circuit test module completes the open short circuit (open short) test of the FT test on the chip to be tested placed in the test groove, the chip identification reading module reads the identification in the FT identification register of the chip to be tested, and if the identification in the FT identification register of the chip to be tested is an initial identification code, the phenomenon of material overlapping does not occur, namely the chip is not tested.
Example III
Based on the chip test device of the first embodiment or the second embodiment, in the EQC (spot check) test mode, the controller reads the identifier in the FT flag register of the spot check chip when the open short circuit test module completes the open short circuit (open short) test of the EQC test on the spot check chip placed in the test slot, and if the test passes the identification code, it is indicated that no FT test omission occurs, and outputs FT test normal information; and if the test passing identification code is not the test passing identification code, outputting FT test missing test information.
Preferably, in the EQC test mode, when all test items of the FT test of the sampling test chip placed in the test slot are completed, if all test items of the EQC test of the sampling test chip pass, the controller controls the manipulator to take the sampling test chip from the test slot and place the sampling test chip in the good product box; and if the EQC test of the sampling inspection chip has a failure test item, the control manipulator takes the sampling inspection chip out of the test slot and places the sampling inspection chip in a defective bin.
Preferably, the chip testing process stacking or clamping checking method of the chip testing device further comprises the steps of:
sixth, the test engineer makes the chip test equipment enter an EQC test mode, and takes the sampling inspection chip from the good product box and places the sampling inspection chip in the test groove;
seventhly, a test engineer performs open-short circuit test on the sampling test chip placed in the test slot through the open-short circuit test module;
the chip identification reading module reads an identification in an FT mark register of the sampling test chip when the sampling test chip placed in the test slot is subjected to the open-short test of the EQC test by the open-short test module;
A step nine of outputting FT test normal information by the controller if the test passes the identification code when the chip identification reading module reads the identification in the FT flag register of the sampling test chip when the sampling test chip placed in the test slot completes the open-short test of the EQC test by the open-short test module; otherwise, outputting FT test missing information;
test engineers test the test items of the EQC test on the sampling test chips placed in the test slots.
Preferably, in step nine, if the controller outputs the FT test missing information, the controller controls the manipulator to take the spot check chip from the test slot and place it in the defective bin.
Preferably, in step ten, when all test items of the EQC test of the spot check chip placed in the test slot are completed, if all test items of the EQC test of the spot check chip pass, the controller controls the manipulator to take the spot check chip from the test slot and place the spot check chip in the good product box; and if the EQC test of the sampling inspection chip has a failure test item, the control manipulator takes the sampling inspection chip out of the test slot and places the sampling inspection chip in a defective bin.
After the FT test is completed, the chip test apparatus of the third embodiment may enter an EQC (spot check) test mode, and in the EQC (spot check) test mode, check whether the FT test has a missing test chip and timely check whether a missing test phenomenon occurs by checking whether the identifier in the FT flag register of the spot check chip is a test passing identifier, so as to facilitate subsequent tracking and checking whether the chip is a chip through which the FT test passes.
The above are only preferred embodiments of the present application, and are not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (12)
1. The chip testing equipment is characterized by comprising a testing seat, an open-short circuit testing module, an identification writing module, a chip identification reading module and a controller;
the test seat is provided with a test groove for accommodating a chip and is used for placing the chip to be detected;
The identification writing module is used for writing an identification into the FT mark register of the chip;
The open-short circuit test module is used for carrying out an open-short circuit test of FT test on the chip to be tested placed in the test groove;
The chip identification reading module is used for reading the identification in the FT mark register of the chip to be detected when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test slot and all test items of the FT test are completed;
the chip to be detected is characterized in that before FT test is started, the identification in the FT mark register is an initial identification code, and the test is different from the initial identification code through the identification code;
The controller is used for outputting the occurrence information of the stacking or clamping phenomenon if the identification in the FT mark register of the chip to be detected, which is read by the chip identification reading module when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test slot, is a test passing identification code in the FT test mode;
the controller is used for controlling the identification writing module to write a test passing identification code into the FT mark register of the chip if all the test items of the FT test of the chip to be tested are passed when all the test items of the FT test of the chip to be tested placed in the test slot are finished in the FT test mode; if the FT test of the chip to be detected has a failure test item, outputting test failure information.
2. The chip testing apparatus according to claim 1, wherein,
The controller is used for reading the mark in the FT mark register of the sampling test chip when the sampling test chip placed in the test slot is subjected to the open-short circuit test by the open-short circuit test module in the EQC test mode, and outputting FT test normal information if the test passes the identification code; and if the test passing identification code is not the test passing identification code, outputting FT test missing test information.
3. The chip testing apparatus according to claim 2, wherein,
The controller is used for controlling the manipulator to take the sampling inspection chip from the test slot and put the sampling inspection chip into a good product box if all test items of the sampling inspection chip for the test slot pass through when all test items of the FT test of the sampling inspection chip placed in the test slot are finished in the EQC test mode; and if the EQC test of the sampling inspection chip has a failure test item, the control manipulator takes the sampling inspection chip out of the test slot and places the sampling inspection chip in a defective bin.
4. A method for inspecting a stacking material or a clamping material in a chip testing process, which is applied to the chip testing equipment of claim 1, and comprises the following steps:
Firstly, enabling a test engineer to enable chip test equipment to enter an FT test mode, and carrying out open-short circuit test on a chip to be tested placed in a test groove through the open-short circuit test module;
the chip identification reading module is used for reading an identification in an FT mark register of a chip to be detected when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test groove;
thirdly, the chip identification reading module reads the identification in the FT mark register of the chip to be detected when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test slot, and if the test passes the identification code, the controller outputs the occurrence information of the material stacking or material clamping phenomenon; otherwise, performing the fourth step;
Fourthly, testing other test items of FT tests on the chip to be tested placed in the test groove by a test engineer;
Fifthly, when all test items of the FT test of the chip to be tested placed in the test slot are completed, if all the test items of the FT test of the chip to be tested pass, the controller controls the identification writing module to write a test passing identification code into the FT mark register of the chip; and if the FT test of the chip to be detected has a failure test item, the controller outputs test failure information.
5. The method for inspecting a die test process stack or stuck object according to claim 4,
Step three, when the controller outputs information of occurrence of material stacking or material clamping, stopping FT test, and taking out the chip to be detected placed in the test groove and placing the chip in a defective bin;
And fifthly, stopping the FT test when the controller outputs the test failing information, and taking out the chip to be detected placed in the test groove and placing the chip in a defective bin.
6. The method for inspecting a die test process stack or stuck object according to claim 4,
And fifthly, when all test items of the FT test of the chip to be tested placed in the test groove are completed, if all the test items of the FT test of the chip to be tested pass, the controller controls the identification writing module to write a test passing identification code into the FT mark register of the chip, and controls the manipulator to take the chip to be tested from the test groove and place the chip in a good product box.
7. The method for inspecting a die test process stack or stuck object according to claim 4,
In the first step, firstly, writing the mark in the FT mark register of the chip to be detected as an initial identification code, then enabling chip testing equipment to enter an FT testing mode, and carrying out open-short circuit testing on the chip to be detected placed in the testing groove through the open-short circuit testing module.
8. The method for inspecting a die test process stack or stuck object according to claim 7,
In the first step, when a chip to be detected is subjected to CP test, a controller controls the identification writing module to write an initial identification code into an FT mark register of the chip;
And step three, the chip identification reading module reads the identification in the FT mark register of the chip to be detected when the open-short circuit test module completes the open-short circuit test of the FT test on the chip to be detected placed in the test slot, if the test passes the identification code, the controller outputs the occurrence information of the material overlapping or material clamping phenomenon, and if the test passes the identification code, the step four is performed.
9. The method for inspecting a die test process stack or stuck object according to claim 7,
The initial identification code is oxFF and the test passes the identification code ox78.
10. The method for inspecting a die test process stack or stuck object according to claim 6,
The method also comprises the steps of:
sixth, the test engineer makes the chip test equipment enter an EQC test mode, and takes the sampling inspection chip from the good product box and places the sampling inspection chip in the test groove;
seventhly, a test engineer performs open-short circuit test on the sampling test chip placed in the test slot through the open-short circuit test module;
The chip identification reading module reads an identification in an FT mark register of the sampling test chip when the sampling test chip placed in the test slot is subjected to the open-short test of the EQC test by the open-short test module;
A step nine of outputting FT test normal information by the controller if the test passes the identification code when the chip identification reading module reads the identification in the FT flag register of the sampling test chip when the sampling test chip placed in the test slot completes the open-short test of the EQC test by the open-short test module; otherwise, outputting FT test missing information;
test engineers test the test items of the EQC test on the sampling test chips placed in the test slots.
11. The method for inspecting a die test process stack or stuck object according to claim 10,
And step nine, if the controller outputs FT test missing information, the controller controls the manipulator to take the spot check chip from the test slot and place the spot check chip in a defective bin.
12. The method for inspecting a die test process stack or stuck object according to claim 10,
In step ten, when all test items of the EQC test of the sampling test chip placed in the test slot are completed, if all test items of the EQC test of the sampling test chip pass, the controller controls the mechanical arm to take the sampling test chip from the test slot and place the sampling test chip in a good product box; and if the EQC test of the sampling inspection chip has a failure test item, the control manipulator takes the sampling inspection chip out of the test slot and places the sampling inspection chip in a defective bin.
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