CN113281634A - Chip testing equipment and chip testing process stacking or blocking inspection method thereof - Google Patents
Chip testing equipment and chip testing process stacking or blocking inspection method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000007689 inspection Methods 0.000 title claims abstract description 42
- 230000000903 blocking effect Effects 0.000 title claims abstract description 32
- 239000000463 material Substances 0.000 claims abstract description 60
- 230000002950 deficient Effects 0.000 claims description 15
- 238000005070 sampling Methods 0.000 claims description 9
- 239000013256 coordination polymer Substances 0.000 claims description 3
- 238000013100 final test Methods 0.000 description 133
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2894—Aspects of quality control [QC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/01—Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/54—Testing for continuity
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Abstract
The invention discloses a chip testing device, under an FT testing mode, if a chip identification reading module reads an identification in an FT (field programmable gate) flag register of a chip to be tested, which is read when an open short circuit testing module completes the open short circuit testing of the FT testing on the chip to be tested placed in a testing groove, as a testing passing identification code, a controller of the chip identification reading module outputs information of material overlapping or material blocking phenomena; when all test items of the FT test of the chip to be tested placed in the test slot are finished, if all the test items of the FT test of the chip to be tested pass, the controller controls the identification writing module to write the test passing identification code into the FT flag register of the chip, and if the FT test of the chip to be tested has a failure test item, the controller outputs test failing information. The invention also discloses a material overlapping or blocking inspection method in the chip testing process of the chip testing equipment. The invention is convenient for finding the chip stacking or blocking in time and for follow-up tracking and checking whether the chip is a chip passing the FT test.
Description
Technical Field
The invention relates to a chip testing technology, in particular to a chip testing device and a chip testing (Final Test, namely FT) process material stacking or material blocking inspection method thereof.
Background
Due to market demands, the thickness or the size of part of the chips is too thin, so that the chips are easy to be stacked or blocked in a mechanized factory Test (Final Test).
The stacking phenomenon, that is, two chips are stacked up and down in a test socket (socket), results in that the chip below the test socket is actually tested twice, and the chip above the test socket is actually not tested but is driven into a braid as a good test product to flow into the market. The material jamming phenomenon, that is, a chip is jammed in the test socket, may cause the chip to be tested continuously.
The current general material stacking phenomenon detection method is to monitor material stacking through hardware detection equipment (sensor), when a product exists in a test seat of a test machine, a gap between a press rod and the hardware detection equipment is provided with one product, and at the moment, a machine table of the test machine alarms material stacking.
The chinese patent application cn201911124364.x discloses a cn201911124364.x stacking prevention IC testing device, as shown in fig. 1 to 4, which includes a rack, a lifting and lowering device 20, a testing seat 30, a main controller and a stacking prevention detection device 42 installed at each position on the rack, wherein the testing seat 30 has a chip-accommodating test slot 31, the testing seat 30 is located below the lifting and lowering device 20, the stacking prevention detection device 42 detects the storage condition of chips in the test slot 31 and detects the position of the lifting and lowering device 20, the main controller is electrically connected to the lifting and lowering device 20 and the stacking prevention detection device 42, the main controller controls the lifting and lowering device 20 to load or unload chips on the test slot 31, the stacking prevention detection device 42 detects that chips are stored in the test slot 31 and detects that the lifting and lowering device 20 is in an open circuit state when leaving the chip storage position, the main controller controls the stacking prevention IC testing device to stop according to the open circuit state, so the chip test is accomplished and after the action of taking away the chip in test groove 31 is taken in the execution of lifting and pressing device 20, if there is the chip when leaving in test groove 31, then can lead to the machine to be unable to operate, takes out until leaving the chip, and the machine just can continue the operation, avoids appearing the chip and piles up and the risk that the chip that arouses does not survey just to flow, promotes the quality of product. This prevent folding material IC test equipment, whether chip folding material appears in the test groove 31 is judged to the break-make state that prevents folding material detection device 42 through hardware, and is with high costs, and the structure is complicated.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a chip testing device and a chip testing process stacking or blocking inspection method thereof, which are convenient for a test engineer to find the stacking or blocking of chips in time and conveniently trace and inspect whether the chips pass an FT test or not in the follow-up process.
In order to solve the technical problem, the chip testing device provided by the invention comprises a testing seat, an open-short circuit testing module, an identification writing module, a chip identification reading module and a controller;
the test seat is provided with a test slot for accommodating a chip and is used for placing the chip to be tested;
the identification writing module is used for writing an identification into an FT (field programmable) flag register of the chip;
the open short circuit testing module is used for carrying out open short circuit testing of an FT test on a chip to be tested placed in the testing groove;
the chip identification reading module is used for reading the identification in the FT mark register of the chip to be tested when the open short circuit testing module completes the open short circuit test of the FT test on the chip to be tested placed in the test slot and when all test items of the FT test are completed;
the controller outputs material stacking or material blocking phenomenon occurrence information if the identification read by the chip identification reading module in the FT mark register of the chip to be tested is a test passing identification code when the open short circuit test module completes the open short circuit test of the FT test on the chip to be tested placed in the test slot in the FT test mode;
the controller controls the identification writing module to write a test passing identification code into the FT mark register of the chip if all test items of the FT test of the chip to be tested pass through when all test items of the FT test of the chip to be tested placed in the test slot are finished in the FT test mode; and if the FT test of the chip to be tested has a failure test item, outputting test failure information.
Preferably, before the FT test is started, the identification in the FT flag register of the chip to be tested is an initial identification code, and the test passing identification code is different from the initial identification code;
and under the FT test mode, if the identification read by the chip identification reading module in the FT mark register of the chip to be tested, which is read when the open short circuit test module completes the open short circuit test of the FT test on the chip to be tested placed in the test slot, is the initial identification code, the controller outputs information without material overlapping or material blocking.
Preferably, in the EQC test mode, the chip identifier reading module reads the identifier in the FT flag register of the spot check chip when the open-short test module completes the open-short test of the EQC test on the spot check chip placed in the test slot, and if the test passes the identification code, outputs FT test normal information; and if the test pass identification code is not the test pass identification code, outputting FT test missing test information.
Preferably, in the EQC test mode, when all the test items of the FT test on the selective probing chip placed in the test slot are completed, if all the test items of the EQC test on the selective probing chip pass, the controller controls the manipulator to take the selective probing chip away from the test slot and place the selective probing chip in the good product box; and if the EQC test of the random inspection chip has a failure test item, controlling the manipulator to take the random inspection chip out of the test slot and place the random inspection chip in a defective box.
Preferably, the method for inspecting stack or block material in the chip testing process of the chip testing device comprises the following steps:
enabling the chip testing equipment to enter an FT testing mode by a testing engineer, and carrying out open short circuit testing on the chip to be tested placed in the testing groove through the open short circuit testing module;
the chip identification reading module reads the identification in the FT mark register of the chip to be tested when the open short circuit testing module completes the open short circuit test of the FT test on the chip to be tested placed in the test slot;
the chip identification reading module reads the identification in the FT mark register of the chip to be detected when the open short circuit testing module completes the open short circuit test of the FT test on the chip to be detected placed in the test slot, and if the identification passes the test, the controller outputs the information of the occurrence of the material overlapping or material blocking phenomenon; otherwise, performing the step four;
testing other test items of the FT test on the chip to be tested placed in the test slot by a test engineer;
when all test items of the FT test of the chip to be tested placed in the test slot are finished, if all test items of the FT test of the chip to be tested pass, the controller controls the identification writing module to write a test passing identification code into the FT mark register of the chip; and if the FT test of the chip to be tested has a failure test item, the controller outputs test failure information.
Preferably, in the third step, when the controller outputs information about material stacking or material blocking, the FT test is stopped, and the chip to be tested placed in the test slot is taken out and placed in a defective box;
and step five, when the controller outputs the test failure information, stopping the FT test, and taking out the chips to be tested placed in the test slots and placing the chips in a defective box.
Preferably, in the fifth step, when all test items of the FT test on the chip to be tested placed in the test slot are completed, if all test items of the FT test on the chip to be tested pass, the controller controls the identification writing module to write the test pass identification code into the FT flag register of the chip, and controls the manipulator to take the chip to be tested away from the test slot and place the chip in the good product box.
Preferably, in the first step, the identification in the FT flag register of the chip to be tested is written as the initial identification code, then the chip testing device enters the FT testing mode, and the open-short circuit testing module performs open-short circuit testing on the chip to be tested placed in the test slot.
Preferably, in the first step, when the CP test is performed on the chip to be tested, the controller controls the identifier writing module to write the initial identification code into the FT flag register of the chip;
in the third step, the chip identification reading module reads the identification in the FT flag register of the chip to be tested when the open short circuit testing module completes the open short circuit test of the FT test on the chip to be tested placed in the test slot, if the identification passes the test, the controller outputs the information of material overlapping or material blocking, and if the identification is the initial identification, the fourth step is performed.
Preferably, the initial identifier is oxFF and the test passes identifier ox 78.
Preferably, the method further comprises the following steps:
enabling the chip testing equipment to enter an EQC testing mode by a testing engineer, and taking a sampling test chip from a good product box and placing the sampling test chip in a test slot;
testing engineer tests open short circuit of the sampling inspection chip placed in the test slot through the open short circuit testing module;
the chip identification reading module reads the identification in the FT flag register of the spot check chip when the open short circuit test module completes the open short circuit test of the EQC test on the spot check chip placed in the test slot;
the chip identification reading module reads the identification in the FT flag register of the spot check chip when the open short circuit test module completes the open short circuit test of the EQC test on the spot check chip placed in the test slot, and if the identification passes the test, the controller outputs FT test normal information and the step ten is carried out; otherwise, outputting FT test missing test information;
and tentatively testing other test items of the EQC test on the spot inspection chip placed in the test slot by the test engineer.
Preferably, in the ninth step, if the controller outputs FT test missing information, the controller controls the manipulator to take the spot check chip away from the test slot and place the spot check chip in the defective box.
Preferably, in the tenth step, when all the test items of the EQC test on the selective chip placed in the test slot are completed, if all the test items of the EQC test on the selective chip pass through, the controller controls the manipulator to take away the selective chip from the test slot and place the selective chip in the good product box; and if the EQC test of the random inspection chip has a failure test item, controlling the manipulator to take the random inspection chip out of the test slot and place the random inspection chip in a defective box.
According to the chip testing device, an FT testing mode is entered during an FT test, after an open short circuit (open short) test is completed by an open short circuit testing module, an identification in an FT flag register of a chip to be tested is read, whether material overlapping or material blocking occurs is judged according to whether the identification in the FT flag register of the chip to be tested is a test passing identification code, so that not only can the chips which are subjected to material overlapping or material blocking in the FT (final test) testing process be screened out in time, but also a test engineer can be prompted to have the material blocking or material overlapping, the test slots can be conveniently and timely processed, the chips which are not tested and the chips which are damaged due to the material overlapping or material blocking can be prevented from flowing into the market, the reliability of the chip testing process is improved, and the follow-up tracking and checking whether the chips are the chips which pass the FT test can be conveniently carried out.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the present invention are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a conventional stack-proof IC testing apparatus;
FIG. 2 is a schematic structural diagram of a chip testing apparatus according to the present invention;
FIG. 3 is a flow chart of a chip testing process stack or card inspection method of the chip testing apparatus of the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
As shown in fig. 2, the chip testing apparatus includes a testing socket, an open/short circuit testing module, an identifier writing module, a chip identifier reading module, and a controller;
the test seat is provided with a test slot for accommodating a chip and is used for placing the chip to be tested;
the identification writing module is used for writing an identification into an FT (field programmable) flag register of the chip;
the open short circuit testing module is used for carrying out open short circuit (open short) testing on the to-be-tested chip placed in the testing groove;
the chip identification reading module is used for reading the identification in the FT mark register of the chip to be detected when the open short circuit testing module completes the open short circuit (open short) test of the FT (final test) test on the chip to be detected placed in the test slot and when all test items of the FT test are completed;
the controller outputs material stacking or material blocking phenomenon occurrence information if the identification read by the chip identification reading module in the FT mark register of the chip to be tested is a test passing identification code when the open short circuit test module completes the open short circuit test of the FT test on the chip to be tested placed in the test slot in the FT test mode;
the controller controls the identification writing module to write a test passing identification code into the FT mark register of the chip if all test items of the FT test of the chip to be tested pass through when all test items of the FT test of the chip to be tested placed in the test slot are finished in the FT test mode; and if the FT test of the chip to be tested has a failure test item, outputting test failure information.
The method for checking stacking or blocking in the chip testing process of the chip testing equipment, as shown in fig. 3, comprises the following steps:
enabling the chip testing equipment to enter an FT testing mode by a testing engineer, and carrying out open short circuit (open short) testing on the chip to be tested placed in the testing groove through the open short circuit testing module;
the chip identification reading module reads the identification in the FT mark register of the chip to be detected when the open short circuit testing module completes the open short circuit test of the FT (Final test) test on the chip to be detected placed in the test slot;
the chip identification reading module reads the identification in the FT mark register of the chip to be detected when the open short circuit testing module completes the open short circuit test of the FT test on the chip to be detected placed in the test slot, and if the identification passes the test, the controller outputs the information of the occurrence of the material overlapping or material blocking phenomenon; otherwise, performing the step four;
testing other test items of the FT test on the chip to be tested placed in the test slot by a test engineer;
when all test items of the FT test of the chip to be tested placed in the test slot are finished, if all test items of the FT test of the chip to be tested pass, the controller controls the identification writing module to write a test passing identification code into the FT flag register of the chip; and if the FT test of the chip to be tested has a failure test item, the controller outputs test failure information.
Preferably, in the third step, when the controller outputs information about material stacking or material blocking, the FT test is stopped, and the chip to be tested placed in the test slot is taken out and placed in a defective box;
and step five, when the controller outputs the test failure information, stopping the FT test, and taking out the chips to be tested placed in the test slots and placing the chips in a defective box.
Preferably, in the fifth step, when all test items of the FT test on the chip to be tested placed in the test slot are completed, if all test items of the FT test on the chip to be tested pass, the controller controls the identification writing module to write the test pass identification code into the FT flag register of the chip, and controls the manipulator to take the chip to be tested away from the test slot and place the chip in the good product box.
According to the chip testing device in the first embodiment, the program is set to write the test passing identification code under the FT flag register of the chip to be tested in the test slot when the last test item of the FT test process is completed; a test engineer firstly carries out open short circuit (open short) test on a chip to be tested placed in a test slot through an open short circuit test module, a chip identification reading module reads an identification in an FT (open short) register of the chip to be tested when the open short circuit test module completes the open short circuit (open short) test of the FT test on the chip to be tested placed in the test slot, and if the identification in the FT register of the chip to be tested is a test passing identification code, the phenomenon of material overlapping or material blocking is indicated, namely the chip is subjected to the FT test; if the identification in the FT mark register of the chip to be tested does not pass the test identification code, the phenomenon of material overlapping does not occur, namely the chip has not been subjected to the FT test.
In the chip testing device according to the first embodiment, the FT testing mode is entered during the FT testing, after the open short circuit testing module completes the open short circuit (open short) testing, the identifier in the FT flag register of the chip to be tested is read first, and whether the stacking or jamming occurs is determined according to whether the identifier in the FT flag register of the chip to be tested is the test pass identification code, so that not only can the chip which is stacked or jammed during the FT (final test) testing process be screened out in time, but also a test engineer can be prompted to have the jamming or stacking phenomenon, so that the chip which is not tested and the chip which is damaged due to the stacking or jamming phenomenon are prevented from flowing into the market, the reliability of the chip testing process is improved, and the subsequent tracking and checking whether the chip is a test slot which passes the FT testing is facilitated.
Example two
Based on the chip testing equipment of the first embodiment, before starting an FT (final test) test, the identification in an FT flag register of the chip to be tested is an initial identification code, and the test passing identification code is different from the initial identification code;
and under the FT test mode, if the identification read by the chip identification reading module in the FT flag register of the chip to be tested, which is read when the open short circuit test module completes the open short circuit test of the FT test on the chip to be tested placed in the test slot, is the initial identification code, the controller indicates that no material overlapping or material blocking phenomenon occurs, and outputs information that no material overlapping or material blocking phenomenon occurs.
Preferably, in the method for checking stacking or blocking in the chip testing process of the chip testing equipment, in the first step, the identification in the FT flag register of the chip to be tested is written as the initial identification code, then the chip testing equipment enters into the FT testing mode, and the open short circuit testing module is used for carrying out open short circuit testing on the chip to be tested placed in the testing groove.
Preferably, in the method for checking stack or card in the chip testing process of the chip testing device, in the first step, when a CP (Circuit testing or intermediate testing) test is performed on a chip to be tested, the controller controls the identifier writing module to write an initial identification code into the FT flag register of the chip;
in the third step, the chip identification reading module reads the identification in the FT flag register of the chip to be tested when the open short circuit testing module completes the open short circuit test of the FT test on the chip to be tested placed in the test slot, if the identification passes the test, the controller outputs the information of occurrence of the material overlapping or material blocking phenomenon, and if the identification passes the test, the controller outputs the information of occurrence of no material overlapping or material blocking phenomenon, and the fourth step is performed.
Preferably, the initial identifier is oxFF and the test passes identifier ox 78.
The chip testing device of the second embodiment makes the mark in the FT flag register of the chip to be tested an initial identification code before starting the FT (final test) test; the chip identification reading module reads the identification in the FT flag register of the chip to be tested when the open short circuit testing module completes the open short circuit (open short) test of the FT test on the chip to be tested placed in the test slot, and if the identification in the FT flag register of the chip to be tested is the initial identification code, the phenomenon of material overlapping does not occur, namely the chip is not tested.
EXAMPLE III
Based on the chip testing device according to the first embodiment or the second embodiment, in an EQC (spot test) test mode, the controller reads, by the chip identifier reading module, the identifier in the FT flag register of the spot test chip, which is read by the open short circuit testing module when the open short circuit testing module completes an open short circuit (open short) test of the EQC test on the spot test chip placed in the test slot, and if the identifier passes the test, it indicates that no FT test missing occurs, and outputs normal FT test information; and if the test pass identification code is not the test pass identification code, outputting FT test missing test information.
Preferably, in the EQC test mode, when all the test items of the FT test on the selective probing chip placed in the test slot are completed, if all the test items of the EQC test on the selective probing chip pass, the controller controls the manipulator to take the selective probing chip away from the test slot and place the selective probing chip in the good product box; and if the EQC test of the random inspection chip has a failure test item, controlling the manipulator to take the random inspection chip out of the test slot and place the random inspection chip in a defective box.
Preferably, the method for inspecting stack or block material in the chip testing process of the chip testing device further comprises the following steps:
enabling the chip testing equipment to enter an EQC testing mode by a testing engineer, and taking a sampling test chip from a good product box and placing the sampling test chip in a test slot;
testing engineer tests open short circuit of the sampling inspection chip placed in the test slot through the open short circuit testing module;
the chip identification reading module reads the identification in the FT flag register of the spot check chip when the open short circuit test module completes the open short circuit test of the EQC test on the spot check chip placed in the test slot;
the chip identification reading module reads the identification in the FT flag register of the spot check chip when the open short circuit test module completes the open short circuit test of the EQC test on the spot check chip placed in the test slot, and if the identification passes the test, the controller outputs FT test normal information and the step ten is carried out; otherwise, outputting FT test missing test information;
and tentatively testing other test items of the EQC test on the spot inspection chip placed in the test slot by the test engineer.
Preferably, in the ninth step, if the controller outputs FT test missing information, the controller controls the manipulator to take the spot check chip away from the test slot and place the spot check chip in the defective box.
Preferably, in the tenth step, when all the test items of the EQC test on the selective chip placed in the test slot are completed, if all the test items of the EQC test on the selective chip pass through, the controller controls the manipulator to take away the selective chip from the test slot and place the selective chip in the good product box; and if the EQC test of the random inspection chip has a failure test item, controlling the manipulator to take the random inspection chip out of the test slot and place the random inspection chip in a defective box.
The chip testing device of the third embodiment may enter an EQC (selective call) testing mode after the FT test is completed, and in the EQC (selective call) testing mode, by checking whether the identifier in the FT flag register of the selective call chip is the test-passing identification code, it is checked whether the FT test has the missing test chip to check whether the missing test phenomenon occurs in time, so that it is convenient for a subsequent trace to check whether the chip is the FT test-passing chip.
The above are merely preferred embodiments of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (13)
1. A chip test device is characterized by comprising a test seat, an open-short circuit test module, an identification writing module, a chip identification reading module and a controller;
the test seat is provided with a test slot for accommodating a chip and is used for placing the chip to be tested;
the identification writing module is used for writing an identification into an FT (field programmable) flag register of the chip;
the open short circuit testing module is used for carrying out open short circuit testing of an FT test on a chip to be tested placed in the testing groove;
the chip identification reading module is used for reading the identification in the FT mark register of the chip to be tested when the open short circuit testing module completes the open short circuit test of the FT test on the chip to be tested placed in the test slot and when all test items of the FT test are completed;
the controller outputs material stacking or material blocking phenomenon occurrence information if the identification read by the chip identification reading module in the FT mark register of the chip to be tested is a test passing identification code when the open short circuit test module completes the open short circuit test of the FT test on the chip to be tested placed in the test slot in the FT test mode;
the controller controls the identification writing module to write a test passing identification code into the FT mark register of the chip if all test items of the FT test of the chip to be tested pass through when all test items of the FT test of the chip to be tested placed in the test slot are finished in the FT test mode; and if the FT test of the chip to be tested has a failure test item, outputting test failure information.
2. The chip test apparatus according to claim 1,
before starting FT test, the identification in the FT mark register of the chip to be tested is an initial identification code, and the test passing identification code is different from the initial identification code;
and under the FT test mode, if the identification read by the chip identification reading module in the FT mark register of the chip to be tested, which is read when the open short circuit test module completes the open short circuit test of the FT test on the chip to be tested placed in the test slot, is the initial identification code, the controller outputs information without material overlapping or material blocking.
3. The chip test apparatus according to claim 1,
the controller is used for reading the identification in the FT flag register of the spot check chip when the open short circuit test module completes the open short circuit test of the EQC test on the spot check chip placed in the test slot in the EQC test mode, and outputting FT test normal information if the test passes the identification code; and if the test pass identification code is not the test pass identification code, outputting FT test missing test information.
4. The chip test apparatus according to claim 3,
the controller controls the manipulator to take the selective inspection chip out of the test slot and place the selective inspection chip in a good product box if all the test items of the EQC test of the selective inspection chip pass through when all the test items of the FT test of the selective inspection chip placed in the test slot are finished in the EQC test mode; and if the EQC test of the random inspection chip has a failure test item, controlling the manipulator to take the random inspection chip out of the test slot and place the random inspection chip in a defective box.
5. The method for inspecting the stack or the jam in the chip testing process of the chip testing device as claimed in claim 1, comprising the steps of:
enabling the chip testing equipment to enter an FT testing mode by a testing engineer, and carrying out open short circuit testing on the chip to be tested placed in the testing groove through the open short circuit testing module;
the chip identification reading module reads the identification in the FT mark register of the chip to be tested when the open short circuit testing module completes the open short circuit test of the FT test on the chip to be tested placed in the test slot;
the chip identification reading module reads the identification in the FT mark register of the chip to be detected when the open short circuit testing module completes the open short circuit test of the FT test on the chip to be detected placed in the test slot, and if the identification passes the test, the controller outputs the information of the occurrence of the material overlapping or material blocking phenomenon; otherwise, performing the step four;
testing other test items of the FT test on the chip to be tested placed in the test slot by a test engineer;
when all test items of the FT test of the chip to be tested placed in the test slot are finished, if all test items of the FT test of the chip to be tested pass, the controller controls the identification writing module to write a test passing identification code into the FT mark register of the chip; and if the FT test of the chip to be tested has a failure test item, the controller outputs test failure information.
6. The method of claim 5, wherein the chip testing process stack or card inspection,
in the third step, when the controller outputs information about material stacking or material blocking, the FT test is stopped, and the chip to be tested placed in the test slot is taken out and placed in a defective box;
and step five, when the controller outputs the test failure information, stopping the FT test, and taking out the chips to be tested placed in the test slots and placing the chips in a defective box.
7. The method of claim 5, wherein the chip testing process stack or card inspection,
and step five, when all the test items of the FT test of the chip to be tested placed in the test slot are finished, if all the test items of the FT test of the chip to be tested pass, the controller controls the identification writing module to write the test passing identification code into the FT flag register of the chip, and controls the manipulator to take the chip to be tested out of the test slot and place the chip in a good product box.
8. The method of claim 5, wherein the chip testing process stack or card inspection,
in the first step, firstly, an identification in an FT mark register of a chip to be tested is written as an initial identification code, then the chip testing equipment enters an FT testing mode, and the open-short circuit testing module is used for carrying out open-short circuit testing on the chip to be tested placed in the testing groove.
9. The method of claim 8, wherein the chip testing process stack or card inspection,
in the first step, when a CP test is carried out on a chip to be detected, a controller controls an identification writing module to write an initial identification code into an FT (field programmable) flag register of the chip;
in the third step, the chip identification reading module reads the identification in the FT flag register of the chip to be tested when the open short circuit testing module completes the open short circuit test of the FT test on the chip to be tested placed in the test slot, if the identification passes the test, the controller outputs the information of material overlapping or material blocking, and if the identification is the initial identification, the fourth step is performed.
10. The method of claim 8, wherein the chip testing process stack or card inspection,
the initial identifier is oxFF and the test passes identifier ox 78.
11. The method of claim 7, wherein the chip testing process stack or card inspection,
further comprising the steps of:
enabling the chip testing equipment to enter an EQC testing mode by a testing engineer, and taking a sampling test chip from a good product box and placing the sampling test chip in a test slot;
testing engineer tests open short circuit of the sampling inspection chip placed in the test slot through the open short circuit testing module;
the chip identification reading module reads the identification in the FT flag register of the spot check chip when the open short circuit test module completes the open short circuit test of the EQC test on the spot check chip placed in the test slot;
the chip identification reading module reads the identification in the FT flag register of the spot check chip when the open short circuit test module completes the open short circuit test of the EQC test on the spot check chip placed in the test slot, and if the identification passes the test, the controller outputs FT test normal information and the step ten is carried out; otherwise, outputting FT test missing test information;
and tentatively testing other test items of the EQC test on the spot inspection chip placed in the test slot by the test engineer.
12. The method of claim 11, wherein the chip testing process stack or card inspection,
and step nine, if the controller outputs the FT test missing information, the controller controls the manipulator to take the spot check chip out of the test slot and place the spot check chip in a defective box.
13. The method of claim 11, wherein the chip testing process stack or card inspection,
step ten, when all the test items of the EQC test of the spot check chip placed in the test slot are finished, if all the test items of the EQC test of the spot check chip pass, the controller controls the manipulator to take the spot check chip away from the test slot and place the spot check chip in a good product box; and if the EQC test of the random inspection chip has a failure test item, controlling the manipulator to take the random inspection chip out of the test slot and place the random inspection chip in a defective box.
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