CN115775589A - Data path detection method, device, equipment and storage medium - Google Patents
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Abstract
The present disclosure provides a data path detection method, apparatus, device, and storage medium, which are applied to a detection process of a data path of a semiconductor integrated circuit. The data path detection method comprises the following steps: the detection device sends a cutting signal to the cutting unit; the disconnection unit disconnects the bit line sensing circuit from the bit line in the data path based on the received disconnection signal; the detection device writes test data into the bit line sensing circuit; under a preset condition, the detection device reads target data of the bit line sensing circuit; and detecting defects of the data path according to the test data and the target data. By adopting the data path detection method in the disclosure, even if the memory array of the semiconductor integrated circuit has problems, the defects of the data path can still be quickly detected, the overall test time of the semiconductor integrated circuit is saved, and the detection efficiency is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a data path detection method, apparatus, device, and storage medium.
Background
Dynamic Random Access Memory (DRAM) is a chip with high density repetitive Memory array cells. With the increasing demand of the application end, the memory array unit is continuously miniaturized, which provides a great challenge for the manufacturing process. Therefore, if the internal storage array has a problem, the problem is usually difficult to test, and it cannot be determined whether the storage array fails or the data path fails, which affects the overall development time of the product.
Disclosure of Invention
The following is a summary of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.
The disclosure provides a data path detection method, apparatus, device and storage medium.
According to a first aspect of an embodiment of the present disclosure, there is provided a data path detection method, including:
the detection device sends a cutting signal to the cutting unit;
the disconnection unit disconnects a bit line sensing circuit from a bit line in the data path based on the received disconnection signal;
the detection device writes test data into the bit line sensing circuit;
under a preset condition, the detection device reads target data of the bit line sensing circuit;
and detecting the defects of the data path according to the test data and the target data.
According to some embodiments of the present disclosure, the cut-off unit includes an N-type MOS transistor or a P-type MOS transistor.
According to some embodiments of the present disclosure, the cut-off unit includes an N-type MOS transistor, and the detecting device sends a cut-off signal to the cut-off unit, including:
the detection device sends a low-level signal to a grid electrode of the N-type MOS tube;
or,
the cutting unit includes P type MOS pipe, detection device sends cutting signal to cutting unit, includes:
and the detection device sends a high-level signal to the grid electrode of the P-type MOS tube.
According to some embodiments of the present disclosure, the detection device writes test data into the bit line sensing circuit, including;
the detection device sends an activation instruction to start a word line in the memory array.
According to some embodiments of the present disclosure, the detecting device writes test data into the bit line sensing circuit, further comprising:
the detection device sends a write command to write test data into the bit line sensing circuit through a write port of the data path.
According to some embodiments of the present disclosure, the reading of the target data of the bit line sensing circuit by the detecting device under the preset condition comprises:
the detection device sends a read command to read target data in the bit line sensing circuit.
According to some embodiments of the present disclosure, the detecting device detects the defect of the data path according to the test data and the target data, including:
and if the test data is inconsistent with the target data, the detection device judges that the data path has defects.
According to some embodiments of the disclosure, the defect comprises a short defect or an open defect.
A second aspect of the present disclosure provides a data path detecting apparatus applied to a detection process of a data path of a semiconductor integrated circuit, the data path detecting apparatus including:
the sending module is used for sending a cutting signal to the cutting unit so that the cutting unit cuts off the connection between the bit line sensing circuit and the bit line in the data path after receiving the cutting signal;
a write module for writing test data into the bit line sensing circuit;
the reading module is used for reading the target data of the bit line sensing circuit under a preset condition;
and the judging module is used for detecting the defects of the data path according to the test data and the target data.
According to some embodiments of the disclosure, the cut-off unit includes an N-type MOS transistor or a P-type MOS transistor, and the transmitting module is configured to:
sending a low level signal to a grid electrode of the N-type MOS tube; or,
the sending module is used for:
and sending a high-level signal to the grid electrode of the P-type MOS tube.
According to some embodiments of the disclosure, the sending module is further to:
an activate command is issued to turn on a word line in the memory array.
According to some embodiments of the disclosure, the sending module is further to:
sending a write-in command;
the write module is to:
test data is written into the bit line sensing circuit through a write port of the data path.
According to some embodiments of the disclosure, the transmitting module is to:
sending a reading command;
the reading module is used for:
target data in the bit line sensing circuit is read.
According to some embodiments of the disclosure, the determining module is to:
and if the test data is inconsistent with the target data, judging that the data path has defects.
According to some embodiments of the disclosure, the data path comprises a data path in a dynamic random access memory.
A third aspect of the present disclosure provides a data path detecting device including:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to perform the data path detection method as described in the first aspect.
According to a fourth aspect of embodiments of the present disclosure, there is provided a non-transitory computer-readable storage medium having instructions thereon, which, when executed by a processor of a terminal, enable a detection device to perform the data path detection method according to the first aspect.
The data path detection method, the device, the equipment and the storage medium provided by the embodiment of the disclosure solve the problem that the defects of the data path cannot be tested under the condition that the storage array of the semiconductor integrated circuit has a fault in the prior art. By using the data path detection method disclosed by the disclosure, the defects of the data path can be quickly detected, the overall test time of the semiconductor integrated circuit is saved, and the detection efficiency is improved.
Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to indicate like elements. The drawings in the following description are directed to some, but not all embodiments of the disclosure. For a person skilled in the art, other figures can be derived from these figures without inventive effort.
Fig. 1 is a circuit diagram illustrating a conventional bit line sensing circuit according to an example.
FIG. 2 is a flow diagram illustrating a data entry and read process according to an example embodiment.
Fig. 3 is a flow chart illustrating a data path detection method according to an example embodiment.
Fig. 4 is a circuit diagram of a bit line sensing circuit showing a cut-off unit as an N-type MOS transistor according to an exemplary embodiment.
Fig. 5 is a circuit diagram illustrating a bit line sensing circuit in which a cut-off unit is a P-type MOS transistor according to an exemplary embodiment.
FIG. 6 is a block diagram illustrating a data path detection apparatus according to an example embodiment.
Fig. 7 is a block diagram illustrating a data path detection device in accordance with an example embodiment.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the embodiments described are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.
Dynamic Random Access Memory (DRAM) is a chip with high density repetitive Memory array cells. With the increasing demand of the application end, the memory array units are continuously scaled down, which presents a great challenge to the manufacturing process. As shown in fig. 1, in the conventional bit line sensing circuit, the bit lines and the bit line sensing circuit cannot be disconnected in the data writing and reading processes, i.e., data is written through an external data port and directly written into a target memory array through a data path, and is read out from the target memory array through the data path. If the internal storage array has problems, the problems are usually difficult to test, and the failure of the storage array or the failure of the data path cannot be judged, so that the overall research and development time of the product is influenced.
In order to solve the above problem, the present disclosure provides a data path detection method. In the data path detection method, the cut-off unit may disconnect or connect the bit line sensing circuit and the bit line in the data path. When the data path is disconnected, i.e., the connection of the bit line to the bit line sensing circuit is disconnected, the target data may be written into the bit line sensing circuit. During detection, target data in the bit line sensing circuit is read and compared with test data, so that whether a data path has a fault or not is known. By adopting the data path detection method disclosed by the disclosure, the problem can be quickly detected, the detection efficiency is improved, and the overall research and development time of the product is not influenced.
Before explaining the technical content related to the present disclosure, a brief description is given to the data input and read process, and as shown in fig. 2, the process of writing write data from the data port DQ to Dbus and storing the write data on the bit line, and reading the write data from the bit line to Dbus and reading the write data through the data port DQ is shown. In the process, a bit line sensing circuit is involved, the bit line sensing circuit comprises a cutting unit, the cutting unit is connected with a detection device, and the detection device sends a cutting signal to the cutting unit to control the cutting unit to cut off the connection between the bit line sensing circuit and the bit line in the data path. The cutting unit may be any component having a function of cutting off a circuit, and this embodiment is not limited in particular.
The specific process of data input and reading is as follows: the bit line is first disconnected from the bit line sensing circuit. Data is written into the Dbus from a data end DQ, and the data is written into the bidirectional drive circuit between the Dbus and the Bbus and transmitted to the Bbus through an enable signal from the Dbus to the Bbus; enabling data to be written into a bidirectional driving circuit between the Bbus and the Cbus through the Bbus through an enabling signal from the Bbus to the Cbus and then transmitting the data to the Cbus; then data is written to the bidirectional drive circuit between Cbus low eight bit < 7> and Cbus high eight bit < 8> by Cbus low eight bit <0 > to Cbus high eight bit <15 > enable signal; data are written into a bidirectional driving circuit between the Cbus and the Abus through the Cbus-to-Abus enabling signal and then are transmitted to the Abus; and then writing data into the YIO write drive circuit according to the global data line YIO write enable signal and the YIEQ signal, writing the data into the local read-write conversion module according to the local data line LIO write drive signal, and finally writing the data into the bit line sensing circuit according to the column selection signal Csl to finish the writing of the target data.
When reading data, the bit line is disconnected from the bit line sensing circuit. Target data is read out of the bit line sensing circuit through the data path in accordance with the connection signal Iso of the cut-off unit, the local data line LIO read drive signal, the global data line YIO read drive signal, the Abus to Cbus enable signal, cbus high octet <15 > to Cbus low octet < 7> enable signal, cbus to Bbus enable signal, and Bbus to Dbus enable signal, in that order. And finishing reading the target data.
According to an exemplary embodiment, as shown in fig. 3, the present embodiment provides a data path detection method, including the following steps:
s110, the detection device sends a cutting signal to a cutting unit.
S120, the cutting unit cuts off the connection between the bit line sensing circuit and the bit line in the data path based on the received cutting signal.
S130, the detection device writes the test data into the bit line sensing circuit.
S140, under the preset condition, the detection device reads the target data of the bit line sensing circuit.
And S150, detecting the defects of the data path according to the test data and the target data.
In the detection process, the detection device is connected with the dynamic random access memory, and signals are written into or read from the dynamic random access memory so as to detect the dynamic random access memory.
In step S110, before the detection device detects the defect in the data path, a cut-off signal is first sent to a cut-off unit, which may be an electrical component such as an NMSO transistor (i.e., N-type MOS transistor) or a PMOS transistor (i.e., P-type MOS transistor) that can control the on/off of the circuit. When the detection device sends a cut-off signal, for example, a tmReadLio command may be sent, which may cause the cut-off unit to lose the connection and electrical connection function, thereby disconnecting the circuit using the cut-off unit for connection, so that the read operation and the write operation performed in the subsequent steps can only be performed in the bit line sensing circuit.
In step S120, referring to fig. 4 and 5, the disconnection unit 334 disconnects the bit line sensing circuit 333 from the bit line in the data path based on the received disconnection signal. For example, when the cut-off unit 334 is an NMOS transistor, the bit line sensing circuit 333 may be cut off from the bit line in the data path by sending a low level to the gate voltage of the NMOS transistor; for another example, when the cut-off unit 334 is a PMOS transistor, the connection between the bit line sensing circuit 333 and the bit line in the data path can be cut off by sending a high level to raise the gate voltage of the PMOS transistor. The bit line sensing circuit in the data path is disconnected from the bit line, and the data path can be detected whether a defect exists. The data path may be, for example, a path between Dbus to the bit line sensing circuit in fig. 2. After the connection between the bit line and the bit line sensing circuit is disconnected, whether the data path has a fault or not can be judged by reading and detecting the data in the data path, so that the detection of the whole data path is realized.
After completing the disconnection of the bit line sensing circuit 333 from the bit line in the data path, the detection apparatus sends an Active command (Active cmd) to turn on a word line in the memory array.
In step S130, the detection apparatus transmits a Write instruction (Write cmd). Data may now be written to bit line sensing circuit 333 through the data path. As shown in FIG. 2, the data path to bit line sensing circuit 333 is fully turned on, and data can be written to bit line sensing circuit 333.
In step S140, after the bit line sensing circuit 333 disconnects the bit line, the data that has been written is saved in the bit line sensing circuit 333. In this step, when the preset condition indicates that the bit line sensing circuit 333 and the bit line are in a disconnected state, at this time, the detection apparatus sends a Read command (Read cmd) to the bit line sensing circuit 333 to Read out the stored target data, so as to provide data support for the subsequent defect determination process. The target data read in this step is data written into the bit line sensing circuit 333 through the data path, and by comparing the target data with the test data, it is possible to visually reflect whether the data path and the bit line sensing circuit 333 have a problem.
In step S150, the target data of the bit line sensing circuit 333 is read and compared with the test data to detect whether the target data is consistent with the test data, so as to determine whether the data path has a defect. If the target data is not consistent with the test data, it is said that the target data is wrongly written or read through the data path, which causes data change, indicating that the data path or the bit line sensing circuit has defects. If the target data is consistent with the test data, it is indicated that all of the target data is normal in the writing and reading processes through the data path, i.e. the data path and the bit line sensing circuit have no defects.
The defect existing in the data path may be a short-circuit defect or an open-circuit defect, and the detection device may perform further detection and determination subsequently.
According to an exemplary embodiment, referring to fig. 4, the cut-off unit 334 in the present embodiment includes an N-type MOS transistor. The source electrode of the N-type MOS tube is connected with the bit line sensing circuit, the drain electrode of the N-type MOS tube is connected with the bit line, and the grid electrode of the N-type MOS tube is connected with the cut-off signal. When the cut-off unit 334 receives the cut-off signal, it sends a low level to the gate of the N-type MOS transistor, causing the N-type MOS transistor to be non-conductive, thereby cutting off the connection between the bit line sensing circuit 333 and the bit line in the data path. Since the local data line LIO is always in communication with the bit line sensing circuit 333, data is held in the bit line sensing circuit 333. The detection device may read the target data in the bit line sensing circuit 333. And finally, judging the defects of the data path according to the comparison result of the detection of the test data and the target data, namely judging whether the data path has errors.
According to an exemplary embodiment, as shown in fig. 5, the cut-off unit 334 in the present embodiment includes a P-type MOS transistor. The source electrode of the P-type MOS tube is connected with the bit line sensing circuit, the drain electrode of the P-type MOS tube is connected with the bit line, and the grid electrode of the P-type MOS tube is connected with the cut-off signal. When the cut-off unit 334 receives the cut-off signal, it sends a high level to the gate of the P-type MOS transistor, causing the P-type MOS transistor to be non-conductive, thereby cutting off the connection between the bit line sensing circuit 333 and the bit line in the data path. Since the local data line LIO is always in communication with the bit line sensing circuit 333, the written data can be held in the write data to bit line sensing circuit 333. Under a predetermined condition, the detecting apparatus can read the target data in the bit line sensing circuit 333, and finally detect the defect of the data path according to the test data and the target data, for example, compare whether the test data is consistent with the read target data to determine whether the data path has a defect.
FIG. 6 illustrates a block diagram of a data path detection apparatus in accordance with an exemplary embodiment. As shown in fig. 6, the apparatus includes at least a sending module 301, a writing module 302, a reading template 303, and a determining module 304. The sending module 301 is configured to send a cut-off signal to the cutting unit, so that the cutting unit cuts off the connection between the bit line sensing circuit and the bit line in the data path after receiving the cut-off signal. The write module 302 is used to write test data into the bit line sensing circuit. The reading module 303 is configured to read target data of the bit line sensing circuit under a preset condition. And a determining module 304, configured to detect a defect of the data path according to the test data and the target data.
When the cut-off unit is an N-type MOS transistor, the sending module 301 is configured to send a low level signal to the N-type MOS transistor. And when the cutting unit is a P-type MOS tube, sending a high-level signal to the P-type MOS tube. The transmit module 301 also transmits an activate command to open a word line in the memory array. The write module 302 writes the target data into the bit line sensing circuits. The read module 303 receives a read command to read target data in the bit line sensing circuit. If the test data is inconsistent with the target data, the determining module 304 determines whether the data path has a defect.
FIG. 7 is a block diagram illustrating an apparatus, namely a computer apparatus 400, for data path detection in accordance with an exemplary embodiment. For example, the computer device 400 may be provided as a terminal device. Referring to fig. 7, the computer apparatus 400 includes a processor 401, and the number of processors may be set to one or more as necessary. The computer device 400 further comprises a memory 402 for storing instructions, e.g. application programs, executable by the processor 401. The number of the memories can be set to one or more according to needs. Which may store one or more applications. The processor 401 is configured to execute instructions to perform the data path detection method described above.
As will be appreciated by one of skill in the art, embodiments of the present disclosure may be provided as a method, apparatus (device), or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied in the media. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, including, but not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the computer, and the like. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
In an exemplary embodiment, a non-transitory computer readable storage medium comprising instructions, such as a memory 402 comprising instructions, executable by a processor 401 of a device 400 to perform the above-described method is provided. For example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
A non-transitory computer readable storage medium, instructions in which, when executed by a processor of a terminal, enable a detection device to perform the data path detection method in the above embodiments.
The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" 8230; "does not exclude the presence of additional like elements in an article or device comprising the element.
While preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various changes and modifications may be made to the disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure also cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.
Claims (17)
1. A data path detection method applied to a detection process of a data path of a semiconductor integrated circuit, the data path detection method comprising:
the detection device sends a cutting signal to the cutting unit;
the disconnection unit disconnects a bit line sensing circuit from a bit line in the data path based on the received disconnection signal;
the detection device writes test data into the bit line sensing circuit;
under a preset condition, the detection device reads target data of the bit line sensing circuit;
and detecting the defects of the data path according to the test data and the target data.
2. The detection method according to claim 1, wherein the cut-off unit comprises an N-type MOS transistor or a P-type MOS transistor.
3. The method according to claim 2, wherein the cut-off unit comprises an N-type MOS transistor, and the detecting device sends a cut-off signal to the cut-off unit, comprising:
the detection device sends a low-level signal to a grid electrode of the N-type MOS tube;
or,
the cutting unit includes P type MOS pipe, detection device sends cutting signal to cutting unit, includes:
and the detection device sends a high-level signal to the grid electrode of the P-type MOS tube.
4. The method of claim 1, wherein the detecting device writes test data into the bit line sensing circuit, comprising:
the detection device sends an activation instruction to start a word line in the memory array.
5. The method of claim 4, wherein the detecting device writes test data into the bit line sensing circuit, further comprising:
the detection device sends a write command to write test data into the bit line sensing circuit through a write port of the data path.
6. The method according to claim 1, wherein the reading of the target data of the bit line sensing circuit by the detection device under the preset condition comprises:
the detection device sends a read command to read target data in the bit line sensing circuit.
7. The inspection method of claim 1, wherein the inspecting device inspects the data path for defects based on the test data and the target data, comprising:
and if the test data is inconsistent with the target data, the detection device judges that the data path has defects.
8. The inspection method of claim 1, wherein the defect comprises a short defect or an open defect.
9. A data path detection apparatus for use in a detection process of a data path of a semiconductor integrated circuit, the data path detection apparatus comprising:
the sending module is used for sending a cutting signal to the cutting unit so that the cutting unit cuts off the connection between the bit line sensing circuit and the bit line in the data path after receiving the cutting signal;
a write module for writing test data into the bit line sensing circuit;
the reading module is used for reading the target data of the bit line sensing circuit under a preset condition;
and the judging module is used for detecting the defects of the data path according to the test data and the target data.
10. The apparatus according to claim 9, wherein the cut-off unit comprises an N-type MOS transistor or a P-type MOS transistor, and the sending module is configured to:
sending a low level signal to a grid electrode of the N-type MOS tube; or,
the sending module is used for:
and sending a high-level signal to the grid electrode of the P-type MOS tube.
11. The data path detection device of claim 9, wherein the sending module is further configured to:
an activate command is issued to turn on a word line in the memory array.
12. The data path detection device of claim 11, wherein the sending module is further configured to:
sending a write-in command;
the write module is to:
test data is written into the bit line sensing circuit through a write port of the data path.
13. The data path detection device of claim 9, wherein the sending module is configured to:
sending a reading command;
the reading module is used for:
target data in the bit line sense circuit is read.
14. The data path detection device of claim 9, wherein the determining module is configured to:
and if the test data is inconsistent with the target data, judging that the data path has defects.
15. The data path detection device of claim 9, wherein the data path comprises a data path in a dynamic random access memory.
16. A data path detection device, characterized in that the detection device comprises:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to perform the detection method of any one of claims 1 to 8.
17. A non-transitory computer readable storage medium, wherein instructions in the storage medium, when executed by a processor of a terminal, enable a detection device to perform the detection method of any one of claims 1 to 8.
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