CN113258889A - Broadband power amplifier - Google Patents
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Abstract
The invention provides a broadband power amplifier, which adopts a novel output matching network based on an annular structure, overcomes the problem that the output impedance of a transistor changes violently along with the frequency in a broadband working frequency band, and realizes effective matching of the output impedance of the transistor. The input impedance curve of the output matching network is in the working frequency band range, and can fall into a high-efficiency impedance space of the transistor obtained by multiple times of harmonic source load traction, and effective control of second harmonic of the output matching network is achieved. The test result of the embodiment shows that when the input power is 28dBm, the saturated output power is 39.1-41.8 dBm within the frequency band range of 0.3-2.0GHz, the Drain Efficiency (DE) is between 60.8% -66.4%, the gain is between 11-13.9 dB, and the relative bandwidth is as high as 147.8%.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a broadband power amplifier.
Background
Power amplifiers are the main components in radio frequency transmission systems. The signal passes through a radio frequency power amplifier to obtain enough radio frequency output power, and then the signal can be fed to an antenna to be transmitted. In higher frequency bands such as radio frequency/microwave, the power amplifier realized based on lumped parameter elements is limited by the difficulty of realizing the device. The microstrip line has the advantages of small volume, light weight, wide use frequency band, high reliability, low manufacturing cost and the like, and is a high-frequency transmission line with wide application. The microstrip line has a distributed parameter effect, and the electrical characteristics of the microstrip line are closely related to the structural size. Therefore, microstrip power amplifiers are an important implementation form in higher frequency bands such as radio frequency/microwave. The main technical indicators of the microstrip power amplifier are bandwidth, efficiency, output power, and the like.
Disclosure of Invention
The purpose is to overcome the defect of insufficient bandwidth of the traditional microstrip power amplifier. The invention provides a novel microstrip power amplifier which can realize broadband performance. Compared with the existing similar power amplifier, the broadband high-efficiency power amplifier has the advantages of broadband, high efficiency and the like. Hereinafter, simply referred to as a broadband power amplifier.
The topology structure of the broadband power amplifier is shown in figure 1, and is characterized in that: a signal is Input from an Input port (Input), the Input port (Input) is connected to the left end of a first wire (T1), the right end of the first wire (T1) is connected to the left end of a first capacitor (C1), the right end of a first capacitor (C1) is connected to the left end of a second wire (T2), the right end of the second wire (T2) is connected to the lower end of a third wire (T3) and the left end of a fourth wire (T4) simultaneously, the right end of a fourth wire (T4) is connected to the left end of a first resistor (R1) and the left end of a second capacitor (C2) in parallel, the right end of the first resistor (R1) and the right end of a second capacitor (C2) are connected to the lower end of a fifth wire (T5) and the left end of a seventh wire (T7) in parallel, the upper end of the fifth wire (T5) is connected to the lower end of the second resistor (R2), the upper end of a sixth wire (R2) is connected to the upper end of a third wire (T4642) and the upper end of a gate (Vgs) is connected to the third wire (T3), the right end of the seventh wire segment (T7) is connected to the left end of the eighth wire segment (T8), the right end of the eighth wire segment (T8) is connected to the gate of the Field Effect Transistor (FET), the source of the Field Effect Transistor (FET) is grounded, the drain of the Field Effect Transistor (FET) is connected to the left end of the ninth wire segment (T9), the right end of the ninth wire segment (T9) is connected to the left end of the tenth wire segment (T10), the right end of the tenth wire segment (T10) is connected to the left end of the eleventh wire segment (T11) and the left end of the sixteenth wire segment (T16), the right end of the eleventh wire segment (T11) is connected to the upper end of the tenth wire segment (T12) and the left end of the thirteenth wire segment (T13), the right end of the thirteenth wire segment (T13) is connected to the upper end of the fourteenth wire segment (T14) and the left end of the fifteenth wire segment (T15), the right end of the sixteenth wire segment (T16) is connected to the lower end of the seventeenth wire segment (T18), the right end of an eighteenth wire joint (T18) is simultaneously connected with the lower end of a nineteenth wire joint (T19) and the left end of a twentieth wire joint (T20), the right end of a fifteenth wire joint (T15) and the right end of a twentieth wire joint (T20) are simultaneously connected with the left end of a twentieth wire joint (T21), the right end of a twentieth wire joint (T21) is simultaneously connected with the lower end of a twentieth wire joint (T22) and the left end of a twentieth wire joint (T23), the upper end of the twentieth wire joint (T22) is simultaneously connected with a grounded fourth capacitor (C4) and a drain bias voltage (Vds), the right end of a twentieth three wire joint (T23) is simultaneously connected with the lower end of a twentieth wire joint (T24) and the left end of a twentieth wire joint (T25), the right end of a twentieth wire joint (T632) is connected with the left end of a fifth capacitor (C5), the right end of a fifth capacitor (C5) is connected with the right end of a twenty load (T26), and the right end of a twenty load is connected with a twenty load output.
The output matching network of the broadband power amplifier is shown in fig. 2 and comprises a harmonic control network shown by a dashed box G, a twentieth wire joint (T22) connected in parallel and a fundamental matching network shown by a dashed box H. The harmonic control network is used for harmonic control, and the fundamental wave matching network is used for fundamental wave matching. Symbol ZA/θARepresents the characteristic impedance/electrical length, Z, of the tenth (T11), fifteenth (T15), sixteenth (T16) and twentieth (T20) line segmentsB/θBRepresenting the characteristic impedance/electrical length, Z, of the tenth (T12), fourteenth (T14), seventeenth (T17) and nineteenth (T19) wire segmentsC/θCRepresents the characteristic impedance/electrical length, Z, of the tenth (T13) and eighteenth (T18) nodesD/θDRepresenting the characteristic impedance/electrical length, Z, of the tenth (T10) and twentieth (T21) line segments1/θ1Representing the characteristic impedance/electrical length, Z, of the twentieth node (T23)2/θ2Representing the characteristic impedance/electrical length, Z, of the twenty-fifth line segment (T25)3/θ3Represents the twentieth node (T)24) Characteristic impedance/electrical length of. Z'load、Z″loadAnd ZinRespectively representing the input impedance seen in the corresponding direction. The electrical length of the twentieth wire segment (T22) is set to λ/4, where λ is the wideband power amplifier center frequency fMAt the waveguide wavelength.
The input impedance Z of the output matching network shown in FIG. 2 is derivedin. The network of the twenty-second wire-link (T22) in parallel and the fundamental matching network shown by the dashed box H is first analyzed, as shown in fig. 3. The input impedance Z "as shown is derived belowload. The ABCD matrix of the fundamental matching network shown by the dashed box H is marked as [ ABCD]NHIs shown as
[ABCD]NHElement A of (A)1、B1、C1And D1Are respectively as
An input impedance Z 'as shown can be obtained'loadIs composed of
Let the passband lower-side frequency of the wide-band power amplifier be fLThe upper side frequency of the passband is fHCenter frequency of fM＝(fL+fH)/2. These three frequencies are called fundamental frequencies, and the corresponding second harmonic frequencies are 2fL、2fMAnd 2fH. Let λ be fundamental central frequency fMAt the waveguide wavelength, the electrical length of the twentieth wire segment (T22) is set to be λ/4,. Thus, at the fundamental center frequency fMHere, Z ″)loadCan be regarded as Z'loadParallel to the short-circuit line of quarter wavelength. Note that the input impedance of the quarter-wave shorting line is infinite. Thus at the fundamental center frequency fMAt the position of the air compressor, the air compressor is started,
the harmonic control network shown by the dashed box G is then analyzed. The harmonic control network is formed by connecting three parts of networks: the tenth node (T10) is connected to the left end of the network (abbreviated as network F) shown by the dashed box F, and the right end of the network F is connected to the twentieth node (T21). Further, the network F is formed by connecting a network indicated by a dashed box E (simply referred to as network E) and a network indicated by a dashed box E '(simply referred to as network E') in parallel. The network E is symmetrical to the network E', which is shown in fig. 4. The ABCD matrices of the eleventh line segment (T11), the tenth line segment (T12), and the thirteenth line segment (T13) are:
wherein Z isA＝ZC。
Thus, the ABCD matrix of network E is denoted as matrix [ ABCD ]]NEThe expression is as follows:
wherein, [ ABCD]NEWherein elements A, B, C and D are each
The network F is formed by connecting the network E and the network E 'in parallel, and the network E' are symmetrical. Obtaining the ABCD matrix [ ABCD ] of the network F]NFComprises the following steps:
further, an ABCD matrix of the harmonic control network shown by a dotted line frame G is obtained and is marked as [ ABCD ]]NGThe expression is as follows:
wherein, [ ABCD]NGThe elements A ', B', C 'and D' are respectively
Input impedance Z looking into the left end of the harmonic control network as indicated by the dashed box GinIs shown as
The design steps of the broadband power amplifier are summarized as follows:
and Step 1, selecting a proper static working point, and determining a gate bias voltage Vgs and a drain bias voltage Vds.
And Step 2, after the bias voltage is determined, designing a proper bias network and a proper stabilizing circuit.
Step 3, determining the designed working frequency band fLAnd fHCalculating the center frequency of fM＝(fL+fH) And/2, finding the source end and the load end of the transistor at the fundamental frequency f by a method of multiple harmonic source load tractionL、fMAnd fHAnd second harmonic frequency 2fL、 2fMAnd 2fHA high efficiency impedance space.
Step 4, determining parameter Z1、Z2、Z3、ZA、ZBAnd ZDAnd theta1、θ2、θ3、θA、θB、θCAnd thetaDZ 'is calculated according to formulas (3) and (10)'loadAnd ZinAt the fundamental frequency fL、fMAnd fHAnd second harmonic 2fL、2fMAnd 2fHSo that it is within the high efficiency impedance space.
Step 5, combining the bias network, the stabilizing circuit and the matching network to perform overall schematic diagram simulation and optimization so as to enable the overall schematic diagram to meet design indexes; and finally, optimizing the layout, and then processing and testing the real object.
The broadband power amplifier has the beneficial effects that: on the premise of ensuring high efficiency, the broadband working characteristic can be obtained; the design process is simple, and the debugging is easy.
Drawings
FIG. 1: the structure schematic diagram of the broadband power amplifier;
FIG. 2: outputting a schematic diagram of a matching network structure;
FIG. 3: a schematic diagram of a network formed by a twenty-second wire joint (T22) connected in parallel and a fundamental wave matching network shown by a dashed box H;
FIG. 4: a network E schematic;
FIG. 5: the change curve diagram of the input impedance Zin of the output matching network in the frequency range of 0.3-2.0GHz is provided by the embodiment;
FIG. 6: the change curve diagram of the input impedance Zin of the output matching network in the frequency range of 2.1-4.0 GHz is provided by the embodiment;
FIG. 7: example simulation and test results plots.
Detailed Description
In order to embody the inventive and novel aspects of the present invention, the following embodiments are used to further carry out the technical solution and effects. In the analysis, the embodiments of the present invention will be described with reference to the drawings and specific examples, but the embodiments are not limited thereto.
Without loss of generality, the embodiment selects a common microstrip substrate with a relative dielectric constant of 3.66 and a substrate thickness of 0.508 mm.
The working frequency band of the embodiment is set to be 0.3-2.0 GHz. Thus, fLIs 0.3GHz, fHAt 2.0GHz and a center frequency fMAt 1.2GHz, these three frequencies are referred to as the fundamental frequencies.
At three fundamental frequencies, take θAAre 2 °, 5 ° and 7 °, θ, respectivelyBAre respectively 1 DEG, 2 DEG and 3 DEG thetaCAre respectively 1 DEG, 2 DEG and 3 DEG thetaDAre respectively 1 DEG, 3 DEG and 4 DEG, ZA、ZBAnd ZDThe values of (d) are set to 44 Ω, 94 Ω, and 60 Ω, respectively. Can be calculated according to the formula (10) to obtaininAt the fundamental frequency fL、fMAnd fHAnd second harmonic 2fL、2fMAnd 2fHThe impedance values are as follows:
these impedance values all fall within the high efficiency impedance space range. Graphs of the fundamental and second harmonic impedances at the output of the transistor after final tuning and optimization are shown in fig. 5 and 6. FIG. 5 shows a variation curve of the input impedance Zin of the output matching network in the frequency range of 0.3 to 2.0 GHz. FIG. 6 shows a variation curve of the input impedance Zin of the output matching network in the frequency range of 2.1 to 4.0 GHz. It can be seen from the figure that the input impedance Zin is at the fundamental frequency fL＝0.3GHz、fM1.2GHz and fHAll located in the high efficiency impedance space at 2.0 GHz. Furthermore, the input impedance Zin is approximately within the high efficiency impedance space at the second harmonic, enabling high efficiency power output over the entire design frequency band.
The gate bias voltage (Vgs) of the embodiment is-2.8V, the drain bias voltage (Vds) is 28V, and the transistor adopts a CGH40010F field effect transistor. After the continuous wave signal is added through the input end to carry out the drive test, a comparison graph of the actual measurement result and the simulation result is given in fig. 7. It can be seen that, in the range of 0.3 to 2.0GHz, when the input signal power is 28dBm, the saturated output power Pout is 39.1 to 41.8dBm, the drain efficiency DE of 60.8 to 66.4 percent is obtained, and the gain is 11.0 to 13.9 dB. The relative bandwidth of the embodiment is as high as 147.8%, and the characteristic of broadband operation is realized while high efficiency is maintained.
The embodiments listed above fully demonstrate that the broadband power amplifier of the present invention achieves the advantage of broadband operation on the premise of ensuring efficiency, and has the advantages of simple design process, etc., thereby representing significant technical progress. It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (4)
1. A wideband power amplifier, characterized by: a signal is Input from an Input port (Input), the Input port (Input) is connected to the left end of a first wire (T1), the right end of the first wire (T1) is connected to the left end of a first capacitor (C1), the right end of a first capacitor (C1) is connected to the left end of a second wire (T2), the right end of the second wire (T2) is connected to the lower end of a third wire (T3) and the left end of a fourth wire (T4) simultaneously, the right end of a fourth wire (T4) is connected to the left end of a first resistor (R1) and the left end of a second capacitor (C2) in parallel, the right end of the first resistor (R1) and the right end of a second capacitor (C2) are connected to the lower end of a fifth wire (T5) and the left end of a seventh wire (T7) in parallel, the upper end of the fifth wire (T5) is connected to the lower end of the second resistor (R2), the upper end of a sixth wire (R2) is connected to the upper end of a third wire (T4642) and the upper end of a gate (Vgs) is connected to the third wire (T3), the right end of the seventh wire segment (T7) is connected to the left end of the eighth wire segment (T8), the right end of the eighth wire segment (T8) is connected to the gate of the Field Effect Transistor (FET), the source of the Field Effect Transistor (FET) is grounded, the drain of the Field Effect Transistor (FET) is connected to the left end of the ninth wire segment (T9), the right end of the ninth wire segment (T9) is connected to the left end of the tenth wire segment (T10), the right end of the tenth wire segment (T10) is connected to the left end of the eleventh wire segment (T11) and the left end of the sixteenth wire segment (T16), the right end of the eleventh wire segment (T11) is connected to the upper end of the twelfth wire segment (T12) and the left end of the thirteenth wire segment (T13), the right end of the thirteenth wire segment (T13) is connected to the upper end of the fourteenth wire segment (T14) and the left end of the fifteenth wire segment (T15), the right end of the sixteenth wire segment (T16) is connected to the lower end of the seventeenth wire segment (T18), the right end of an eighteenth wire joint (T18) is simultaneously connected with the lower end of a nineteenth wire joint (T19) and the left end of a twentieth wire joint (T20), the right end of a fifteenth wire joint (T15) and the right end of a twentieth wire joint (T20) are simultaneously connected with the left end of a twentieth wire joint (T21), the right end of a twentieth wire joint (T21) is simultaneously connected with the lower end of a twentieth wire joint (T22) and the left end of a twentieth wire joint (T23), the upper end of the twentieth wire joint (T22) is simultaneously connected with a grounded fourth capacitor (C4) and a drain bias voltage (Vds), the right end of a twentieth three wire joint (T23) is simultaneously connected with the lower end of a twentieth wire joint (T24) and the left end of a twentieth wire joint (T25), the right end of a twentieth wire joint (T632) is connected with the left end of a fifth capacitor (C5), the right end of a fifth capacitor (C5) is connected with the right end of a twenty load (T26), and the right end of a twenty load is connected with a twenty load output.
2. Wideband power amplifier according to claim 1, symbol ZA/θARepresents the characteristic impedance/electrical length, Z, of the tenth (T11), fifteenth (T15), sixteenth (T16) and twentieth (T20) line segmentsB/θBRepresenting the characteristic impedance/electrical length, Z, of the tenth (T12), fourteenth (T14), seventeenth (T17) and nineteenth (T19) wire segmentsC/θCRepresents the characteristic impedance/electrical length, Z, of the tenth (T13) and eighteenth (T18) nodesD/θDShowing the tenth line segment (T10) and the second line segmentCharacteristic impedance/electrical length, Z, of twenty-one wire-link (T21)1/θ1Representing the characteristic impedance/electrical length, Z, of the twentieth node (T23)2/θ2Representing the characteristic impedance/electrical length, Z, of the twenty-fifth line segment (T25)3/θ3Representing the characteristic impedance/electrical length, Z ', of the twenty-fourth wire node (T24)'load、Z″loadAnd ZinRespectively representing the input impedance seen in the corresponding direction, the electrical length of the twenty-second wire segment (T22) is set to λ/4, where λ is the center frequency f of the broadband power amplifierMThe waveguide wavelength of (d); input impedance Z of output matching networkinIs shown as
Wherein matrix elements A, B, C, D, A ', B', C 'and D' are respectively
ZloadIs the output load.
3. The wideband power amplifier according to claim 1, the design steps are summarized as follows:
step 1, selecting a proper static working point, and determining a gate bias voltage Vgs and a drain bias voltage Vds;
step 2, after determining the bias voltage, designing a proper bias network and a proper stabilizing circuit;
step 3, determining the designed working frequency band fLAnd fHCalculating the center frequency of fM＝(fL+fH) And/2, finding the source end and the load end of the transistor at the fundamental frequency f by a method of multiple harmonic source load tractionL、fMAnd fHAnd second harmonic frequency 2fL、2fMAnd 2fHA high efficiency impedance space;
step 4, determining parameter Z1、Z2、Z3、ZA、ZBAnd ZDAnd theta1、θ2、θ3、θA、θB、θCAnd thetaDZ 'is calculated according to formulas (3) and (10)'loadAnd ZinAt the fundamental frequency fL、fMAnd fHAnd second harmonic 2fL、2fMAnd 2fHSo that it is within the high efficiency impedance space;
step 5, combining the bias network, the stabilizing circuit and the matching network to perform overall schematic diagram simulation and optimization so as to enable the overall schematic diagram to meet design indexes; and finally, optimizing the layout, and then processing and testing the real object.
4. The wide band power amplifier of claim 1, wherein the operating frequency band is set to 0.3-2.0GHz and the input impedance Z of the output matching networkinAt the fundamental frequency fL、fMAnd fHAnd second harmonic 2fL、2fMAnd 2fHThe impedance values are as follows:
when the input signal power is 28dBm, the saturated output power Pout is between 39.1 dBm and 41.8dBm, the drain efficiency DE of 60.8 percent to 66.4 percent is obtained, meanwhile, the gain is between 11.0 dB and 13.9dB, and the relative bandwidth is as high as 147.8 percent.
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