CN114070216A - Three-level millimeter wave high-gain GaN power amplifier chip based on coupling matrix comprehensive interstage matching - Google Patents
Three-level millimeter wave high-gain GaN power amplifier chip based on coupling matrix comprehensive interstage matching Download PDFInfo
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- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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Abstract
The invention discloses a coupling matrix comprehensive interstage matching-based three-stage millimeter wave high-gain GaN power amplifier chip, which comprises a two-stage drive amplifier, a final-stage power amplifier, a bias network, an input matching network, an interstage matching network and an output matching network; the interstage matching network consists of three sections of microstrip lines with specific characteristic impedance and series stopping capacitors, the series microstrip lines and the parallel open-circuit microstrip lines are directly coupled, so that the number of resonance points and the basic structure of topology are determined, corresponding coupling coefficients can be synthesized, and initial values of microstrip line parameters are given. Compared with the traditional single-tube power amplifier, the gain and the output power of the expanded amplifier can be effectively improved, and the efficiency is further improved; compared with the traditional broadband power amplifier structure, the broadband power amplifier has the advantages of simple circuit structure, easy realization of a theoretical analysis method and convenient processing, and can be applied to a 5G millimeter wave communication system.
Description
Technical Field
The invention relates to the technical field of millimeter wave GaN power amplifiers, in particular to a three-level millimeter wave high-gain GaN power amplifier chip based on coupling matrix comprehensive interstage matching.
Background
The fifth generation mobile communication has been gradually applied to various industrial production environments depending on its own high-speed data transmission and broadband spectrum utilization. As is well known, with the development of communication systems, the spectrum resource of Sub-6GHz is relatively limited, and therefore, in order to obtain the utilization rate of continuous spectrum, the development of 5G millimeter wave frequency band gradually becomes a mainstream trend in the industry at present. The millimeter wave frequency band can provide larger channel bandwidth (up to 400MHz) and higher frequency spectrum utilization rate, and brings more favorable influence to industrial application. Standards for fifth generation mobile communication have also been established in which the N258 band of 5G NRFR2, i.e., the 5G band of millimeter waves in our country, is determined to be 24.25-27.5 GHz. More complex modulation signals with higher orders are also widely used for 5G NR, such as 64, 128, 256QAM and modulation signals. As is well known, this will put higher demands on the performance and heat dissipation of various parts of the radio frequency system, wherein the radio frequency power amplifier occupies the main position in the communication system, and therefore, the research of the high-gain high-efficiency broadband power amplifier is crucial in order to reduce the complexity and energy consumption of the system and enhance the stability of the operation thereof. The efficiency can be improved, the stability of the system can be improved, the energy consumption can be reduced, the cost of the communication system can be further reduced by widening the frequency band, and the gain can be improved to provide larger output power. Nowadays, a millimeter wave frequency band power amplifier usually adopts a multi-stage driving mode to improve gain so as to meet the requirement of output power, and research and design on inter-stage matching mostly adopt a mode of connecting in parallel to a ground capacitor to increase bandwidth, so that attention on loss of an inter-stage matching network is less. However, in the design of a multi-stage power amplifier, the inter-stage matching loss and the bandwidth greatly limit the performance index of the whole power amplifier. The conventional design method cannot be compatible with the bandwidth and insertion loss performance of the matching structure at the same time, and for increasingly scarce spectrum resources, the method for designing the power amplifier is difficult to meet the requirements of the next generation mobile communication technology on low cost, low loss and high speed transmission rate.
Millimeter wave multistage power amplifiers have been the focus of current research, and the gain of the power amplifier is effectively improved by adding a driving stage. The conventional interstage matching design method cannot be compatible with the bandwidth and insertion loss performance of a matching structure at the same time, the actual operation process is complex, however, the interstage matching power amplifier based on coupling matrix synthesis obtains any topological structure meeting conditions by presetting the working bandwidth and return loss of the interstage matching network and the resonance point of the matching structure, the whole implementation process is simple, a structure which is in line with the expected interstage matching network is easy to obtain, and therefore the influence of interstage matching on the whole radio-frequency power amplifier can be greatly reduced.
At present, the rapid development of 5G mobile communication technology puts higher requirements on the gain, bandwidth and efficiency of a power amplifier. Therefore, how to design a high-gain high-efficiency broadband millimeter wave power amplifier also becomes a research hotspot.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a three-level millimeter wave high gain GaN power amplifier chip based on coupling matrix comprehensive interstage matching, so as to solve the technical problems mentioned in the background art, effectively expand the working bandwidth, and synthesize a coupling matrix corresponding to an interstage matching topology according to a set value of return loss, thereby obtaining a low-loss interstage matching network to reduce the influence on the performance of the overall circuit, and still maintain a high efficiency value, and the design theory is simple, and the matching structure is easy to implement.
In order to achieve the purpose, the invention adopts the following technical scheme:
a three-level millimeter wave high-gain GaN power amplifier chip based on coupling matrix comprehensive interstage matching comprises: the device comprises an input matching network, a field effect transistor T1, a first inter-stage matching network, a field effect transistor T2, a second inter-stage matching network, a field effect transistor T3 and an output matching network;
the input end of the input matching network is connected to the input signal RF, one side of the output end of the input matching network is connected to the grid electrode of the field effect transistor T1, and the other side of the output end of the input matching network is connected with the grid electrode supply voltage V through a first bias network N1B1Connecting;
the drain electrode of the field effect transistor T1 is connected to one side of the input end of the first inter-stage matching network;
the other side of the input end of the first inter-stage matching network is connected with a grid supply voltage V through a second bias network N2D1One side of the output end of the first bias network is connected to the grid of the field effect transistor T2, and the other side of the output end of the first bias network is connected with a grid supply voltage V through a second bias network N3B2Connecting;
the drain electrode of the field effect transistor T2 is connected to one side of the input end of the second inter-stage matching network;
the other side of the input end of the second inter-stage matching network is connected with the drain supply voltage V through a third bias network N4D2Connected with one side of the output end connected to the grid of the field effect transistor T3 and the other side of the output end connected with the grid supply voltage V through a third bias network N5B3Connecting;
the drain electrode of the field effect transistor T3 is connected to one side of the input end of the output matching network;
the other side of the input end of the output matching network is connected with the drain supply voltage V through a fourth bias network N6D3A connection is made, the output of which is connected to the output signal RF;
the grid width (W1, W2 and W3) ratio of the field effect transistor T1, the field effect transistor T2 and the field effect transistor T3 is 1:2:4, and the specific topological structures of the first-stage matching network and the second-stage matching network are determined by the following method: firstly, setting 3 resonance points of the first inter-stage matching network and the second inter-stage matching network, and presetting bandwidth and return loss, wherein the return loss is less than-20 dB;
then determining a corresponding coupling matrix by using a matrix synthesis method;
and finally, determining the specific topological structures of the first inter-stage matching network and the second inter-stage matching network according to the determined coupling matrix.
Further, a capacitor C is arranged between the input matching network and the input signal RFB1An electrical C is also provided between the output matching network and the output signal RFB4。
Further, the first inter-stage matching network specifically includes: series microstrip line M1 and capacitor CB2And a series microstrip line M3, wherein the capacitor C is arranged on the capacitor CB2And a parallel open-circuit microstrip line M2 is also arranged between the series microstrip lines M3.
Further, the matching network between the second levels specifically includes: series microstrip line M4 and capacitor CB3And a series microstrip line M6, wherein the capacitor C is arranged on the capacitor CB3And a parallel open-circuit microstrip line M5 is also arranged between the microstrip lines M6.
Further, in the first inter-stage matching network and the second inter-stage matching network, the characteristic impedance Z of the series microstrip linesAnd electrical length thetasThe following conditions need to be satisfied:
in the formula, fRNatural resonant frequency, f, being the resonance point0Is a center frequency, Mij(1. ltoreq. i, j. ltoreq.5) is expressed as the element of the corresponding row and column in the coupling matrix, θsIs the electrical length of the microstrip line, Z0Representing a characteristic impedance of the 50Ohm standard.
Further, the synthesis of the coupling matrix is based on a prototype of a chebyshev third-order low-pass filter, the coefficient of the corresponding coupling matrix is obtained through synthesis, and the expression of the coupling matrix with three resonance point characteristic paths is as follows:
further, the resonance frequency of the resonance point passes through the center frequency f of the low-pass filter0And bandwidth BW acquisition, its resonant frequency fRThe expression of (a) is:
in the formula, f0Is a center frequency, Mij(i is more than or equal to 1, j is less than or equal to 5) is the element of the corresponding row and column in the coupling matrix, and BW is the design bandwidth of the topological structure.
Further, the gate voltages of the fet T1 and the fet T2 in the deep class AB operating state are the gate supply voltages, and the drain voltages are the drain supply voltages
The invention has the beneficial effects that:
compared with the existing multistage millimeter wave power amplifier, the invention can determine the topological structure of the interstage network according to the preset bandwidth and return loss, and still keep high efficiency value; meanwhile, compared with the traditional high-efficiency power amplifier, the power amplifier has the advantages of simple design theory, easy realization of a matching structure and high reliability under the condition of similar performance.
Drawings
Fig. 1 is a topology structure diagram of a three-stage millimeter wave high-gain GaN power amplifier chip based on coupling matrix synthesis interstage matching provided in embodiment 1;
fig. 2 is a schematic diagram of a specific inter-stage matching topology and a corresponding coupling path provided in embodiment 1, where the left diagram is a schematic diagram of a coupling path, and correspondingly, the right diagram is a schematic diagram of an inter-stage matching topology;
fig. 3 is a schematic diagram of insertion loss and return loss of the theoretical interstage matching topology provided in example 1 under broadband characteristics;
fig. 4 is a measured curve of the saturated power, the saturated efficiency and the saturated gain of the power amplifier according to the embodiment 1;
fig. 5 is a diagram illustrating a large signal characteristic test result of the power amplifier provided in embodiment 1.
In the drawings:
the input matching network IMN, the field effect transistor T1, the field effect transistor T2, the field effect transistor T3, the first inter-stage matching network 1, the second inter-stage matching network 2, the first bias network N1, the second bias network N2, the second bias network N3, the third bias network N4, the third bias network N5, the fourth bias network N6 and the output matching network OMN.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 1 to 5, the present embodiment provides a three-level millimeter wave high gain GaN power amplifier chip based on coupling matrix synthesis interstage matching, which mainly includes four parts: the input matching network IMN, the field effect transistors T1, T2, T3, the first inter-stage matching network 1, the second inter-stage matching network 2 and the output matching network OMN, wherein the first inter-stage matching network 1 and the second inter-stage matching network 2 respectively comprise a second bias network N2, a third bias network N3, a third bias network N4 and a third bias network N5.
The input signal RF _ in is connected to the input terminal of the input matching network IMN, and the other terminal of the input matching network IMN is connected to the gate of the FET T1 and is connected to the gate supply voltage V via the first bias network N1B1The drain of the fet T1 is connected to the first inter-stage matching network 1, and the output of the output matching network OMN is grounded through the terminating load.
Inter-first-level matching networkThe concrete structure of 1 is as follows: a second DC blocking capacitor C is connected between the series microstrip line M1 and the series microstrip line M3B2The parallel microstrip line M2 is connected with a DC blocking capacitor CB2And between the serial microstrip line M3, the two ends of the serial microstrip line M1 and M2 are respectively connected with the drain of the field effect transistor T1 and the gate of the field effect transistor T2 through a second bias network N2 and N3.
The specific structure of the second inter-stage matching network 2 is as follows: a third DC blocking capacitor C is connected between the series microstrip line M4 and the series microstrip line M6B3The parallel microstrip line M5 is connected with a DC blocking capacitor CB3And between the serial microstrip line M6, two ends of the serial microstrip line M4 and M6 are respectively connected with a drain of the field effect transistor T2 and a gate of the field effect transistor T3 through third bias networks N4 and N5.
In this embodiment, a capacitor C is further provided between the input matching network and the input signal RFB1A capacitor C is also arranged between the output matching network and the output signal RFB4。
In this embodiment, the specific topological structures of the first inter-stage matching network and the second inter-stage matching network, in which the gate-to-width ratios of the fet T1, the fet T2, and the fet T3 are 1:2:4, are determined by the following method: firstly, setting 3 resonance points of a first-stage matching network and a second-stage matching network, and presetting bandwidth and return loss, wherein the return loss is less than-20 dB;
then determining a corresponding coupling matrix by using a matrix synthesis method;
and finally, according to the determined coupling matrix, determining the specific topological structures of the first inter-stage matching network and the second inter-stage matching network.
More specifically, in this embodiment, the synthesis of the coupling matrix is based on a prototype of the chebyshev third-order low-pass filter, and the synthesis is easy to obtain the coefficients of the corresponding coupling matrix, and the coupling matrix [ M ] of the characteristic path with three resonance points is:
more specifically, it relates toIn the present embodiment, the resonance frequency of the resonance point may pass through the center frequency f of the low-pass filter0And bandwidth BW acquisition, its resonant frequency fRThe calculation expression of (a) is:
wherein f isRNatural resonant frequency, f, being the resonance point0Is a center frequency, Mij(i is more than or equal to 1, j is less than or equal to 5) elements of corresponding rows and columns in the coupling matrix, and BW is the design bandwidth of the topological structure.
More specifically, in the present embodiment, the characteristic impedance Z of the series microstrip line in the first inter-stage matching network 1 and the second inter-stage matching network 2sAnd electrical length thetasThe following conditions need to be satisfied:
more specifically, in the present embodiment, the gate voltages of the fets T1 and T2 in the deep class AB operating state are the gate supply voltages, and the drain voltages are the drain supply voltages.
The basic structural unit provided in the present embodiment is formed by connecting microstrip lines M having specific characteristic impedance in series1And M3Parallel open-circuit microstrip line M with specific characteristic impedance2And a DC blocking capacitor CBThe low-loss broadband interstage matching network is realized, the interstage loss of the whole power amplifier is further reduced, and the optimal performance index is achieved.
As shown in fig. 3, a solid line legend and a dashed line legend respectively represent an insertion loss and a return loss diagram of a theoretical interstage matching topology under broadband characteristics. As can be seen from fig. 3, fig. 4 and fig. 5, the interstage matching network based on coupling matrix synthesis provided by this embodiment can effectively widen the bandwidth of the millimeter wave power amplifier while maintaining a high efficiency value.
Fig. 4 and 5 are results of a small signal test and a large signal characteristic test of the power amplifier provided in the present embodiment, respectively. As shown in fig. 4, the thick black line represents the small-signal gain S21, and the thin black line represents the return loss S11. The black triangle legend represents the efficiency curve at saturation, the black circle legend is the output power curve at saturation, and the black square legend is the large signal gain curve. The center frequency of the power amplifier of the specific embodiment is 2.05GHz, the bandwidth is 6GHz, the relative bandwidth is 22.6%, the full-band saturation power is 32.6-34.8dBm, the saturation efficiency is 22.1-38.8%, the signal power gain is 19.6-24.9dB, and the small signal gain is 30-35 dB. The difference between the power additional efficiency at high frequency and the simulation is about 6%, and the simulation results of other performances and the test results have good consistency.
In summary, compared with the traditional single-tube power amplifier, the gain and the output power of the amplifier can be effectively improved, and the efficiency is further improved. Compared with the traditional broadband power amplifier structure, the broadband power amplifier has the advantages of simple circuit structure, easy realization of a theoretical analysis method and convenient processing, and can be applied to a 5G millimeter wave communication system.
The invention is not described in detail, but is well known to those skilled in the art.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.
Claims (8)
1. A three-level millimeter wave high-gain GaN power amplifier chip based on coupling matrix comprehensive interstage matching is characterized in that the power amplifier comprises: the device comprises an input matching network, a field effect transistor T1, a first inter-stage matching network, a field effect transistor T2, a second inter-stage matching network, a field effect transistor T3 and an output matching network;
the input matching networkAn input terminal connected to the input signal RF, an output terminal connected to the gate of the FET T1, and an output terminal connected to the gate of the FET T1 via a first bias network N1B1Connecting;
the drain electrode of the field effect transistor T1 is connected to one side of the input end of the first inter-stage matching network;
the other side of the input end of the first inter-stage matching network is connected with a grid supply voltage V through a second bias network N2D1One side of the output end of the first bias network is connected to the grid of the field effect transistor T2, and the other side of the output end of the first bias network is connected with a grid supply voltage V through a second bias network N3B2Connecting;
the drain electrode of the field effect transistor T2 is connected to one side of the input end of the second inter-stage matching network;
the other side of the input end of the second inter-stage matching network is connected with the drain supply voltage V through a third bias network N4D2Connected with one side of the output end connected to the grid of the field effect transistor T3 and the other side of the output end connected with the grid supply voltage V through a third bias network N5B3Connecting;
the drain electrode of the field effect transistor T3 is connected to one side of the input end of the output matching network;
the other side of the input end of the output matching network is connected with the drain supply voltage V through a fourth bias network N6D3A connection is made, the output of which is connected to the output signal RF;
the grid width ratio of the field effect transistor T1, the field effect transistor T2 and the field effect transistor T3 is 1:2:4, and the specific topological structures of the first inter-stage matching network and the second inter-stage matching network are determined by the following method: firstly, setting 3 resonance points of the first inter-stage matching network and the second inter-stage matching network, and presetting bandwidth and return loss, wherein the return loss is less than-20 dB;
then determining a corresponding coupling matrix by using a matrix synthesis method;
and finally, according to the determined coupling matrix, determining the specific topological structures of the first inter-stage matching network and the second inter-stage matching network.
2. The three-stage millimeter wave high gain GaN power amplifier chip based on coupling matrix synthesis interstage matching of claim 1, wherein a capacitor C is further arranged between the input matching network and the input signal RFB1A capacitor C is arranged between the output matching network and the output signal RFB4。
3. The chip of claim 2, wherein the first inter-stage matching network specifically comprises, connected in sequence: series microstrip line M1 and capacitor CB2And a series microstrip line M3, wherein the capacitor C is arranged on the capacitor CB2And a parallel open-circuit microstrip line M2 is also arranged between the series microstrip lines M3.
4. The chip of claim 2, wherein the second inter-stage matching network comprises sequentially connected: series microstrip line M4 and capacitor CB3And a series microstrip line M6, wherein the capacitor C is arranged on the capacitor CB3And a parallel open-circuit microstrip line M5 is also arranged between the microstrip lines M6.
5. The GaN power amplifier chip of claim 3 or 4, wherein the characteristic impedance Z of the series microstrip line is between the first and second matching networkssAnd electrical length thetasThe following conditions need to be satisfied:
in the formula, the first step is that,fRnatural resonant frequency, f, being the resonance point0Is a center frequency, Mij(1. ltoreq. i, j. ltoreq.5) is expressed as the element of the corresponding row and column in the coupling matrix, θsIs the electrical length of the microstrip line, Z0Representing a characteristic impedance of the 50Ohm standard.
6. The chip of claim 1, wherein the integration of the coupling matrix is based on a prototype of a chebyshev third-order low-pass filter, and the coefficient of the corresponding coupling matrix is obtained by integration, and the expression of the coupling matrix with three resonance point characteristic paths is as follows:
7. the GaN power amplifier chip with three-level millimeter wave and high gain based on coupling matrix comprehensive interstage matching as claimed in claim 1, wherein the resonance frequency of the resonance point passes through the center frequency f of a low pass filter0And bandwidth BW acquisition, its resonant frequency fRThe expression of (a) is:
in the formula, f0Is a center frequency, Mij(i is more than or equal to 1, j is less than or equal to 5) is the element of the corresponding row and column in the coupling matrix, and BW is the design bandwidth of the topological structure.
8. The three-stage millimeter wave high gain GaN power amplifier chip based on coupling matrix synthesis interstage matching of claim 1, wherein the gate voltage of the field effect transistor T1 and the field effect transistor T2 in the deep AB operating state is the gate supply voltage, and the drain voltage is the drain supply voltage.
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