CN113258889B - Broadband power amplifier - Google Patents

Abstract

The invention provides a broadband power amplifier, which adopts a novel output matching network based on an annular structure, overcomes the problem that the output impedance of a transistor changes violently along with the frequency in a broadband working frequency band, and realizes effective matching of the output impedance of the transistor. The input impedance curve of the output matching network is in the working frequency band range, and can fall into a high-efficiency impedance space of the transistor obtained by multiple times of harmonic source load traction, and effective control of second harmonic of the output matching network is achieved. The test result of the embodiment shows that when the input power is 28dBm, the saturated output power is 39.1-41.8 dBm within the frequency band range of 0.3-2.0GHz, the Drain Efficiency (DE) is between 60.8% -66.4%, the gain is between 11-13.9 dB, and the relative bandwidth is as high as 147.8%.

Description

A broadband power amplifier

technical field

The invention belongs to the technical field of communication, and in particular relates to a microstrip power amplifier with broadband performance.

Background technique

The power amplifier is the main device in the radio frequency transmission system. The signal passes through the RF power amplifier and obtains enough RF output power to be fed to the antenna for transmission. In higher frequency bands such as radio frequency/microwave, power amplifiers based on lumped-parameter components are limited by the difficulty of implementing devices. Microstrip line has the advantages of small size, light weight, wide frequency bandwidth, high reliability and low manufacturing cost, and is a type of high-frequency transmission line that is widely used. The microstrip line has distributed parameter effects, and its electrical properties are closely related to the structure size. Therefore, in higher frequency bands such as radio frequency/microwave, the microstrip power amplifier is an important realization form. The main technical indicators of microstrip power amplifiers are bandwidth, efficiency and output power.

SUMMARY OF THE INVENTION

In order to overcome the shortcomings of insufficient bandwidth of traditional microstrip power amplifiers. The present invention provides a novel microstrip power amplifier capable of realizing broadband performance. Compared with existing similar power amplifiers, it has the advantages of broadband and high efficiency. Hereinafter, it is simply referred to as a broadband power amplifier.

The topology of the broadband power amplifier according to the present invention is shown in FIG. 1, and is characterized in that: the signal is input from the input port (Input), the input port (Input) is connected to the left end of the first line section (T1), and the first line section The right end of (T1) is connected to the left end of the first capacitor (C1), the right end of the first capacitor (C1) is connected to the left end of the second line segment (T2), and the right end of the second line segment (T2) is connected to the third line segment (T3) at the same time The lower end and the left end of the fourth wire section (T4), the right end of the fourth wire section (T4) is connected in parallel with the left end of the first resistor (R1) and the left end of the second capacitor (C2), and the right end of the first resistor (R1) and the right end of the second capacitor (C2) is connected in parallel to the lower end of the fifth line section (T5) and the left end of the seventh line section (T7), and the upper end of the fifth line section (T5) is connected to the lower end of the second resistor (R2). , the upper end of the second resistor (R2) is connected to the lower end of the sixth line section (T6), and the upper end of the sixth line section (T6) is connected to the grounded third capacitor (C3) and the gate bias voltage (Vgs) at the same time, the first The right end of the seven wire section (T7) is connected to the left end of the eighth wire section (T8), the right end of the eighth wire section (T8) is connected to the gate of the field effect transistor (FET), and the source of the field effect transistor (FET) is grounded, The drain of the field effect transistor (FET) is connected to the left end of the ninth line section (T9), the right end of the ninth line section (T9) is connected to the left end of the tenth line section (T10), and the right end of the tenth line section (T10) at the same time. Connect the left end of the eleventh wire section (T11) with the left end of the sixteenth wire section (T16), and the right end of the eleventh wire section (T11) and connect the upper end of the twelfth wire section (T12) with the thirteenth wire section ( The left end of T13), the right end of the thirteenth wire section (T13) is connected to the upper end of the fourteenth wire section (T14) and the left end of the fifteenth wire section (T15) at the same time, and the right end of the sixteenth wire section (T16) is connected at the same time The lower end of the seventeenth wire section (T17) and the left end of the eighteenth wire section (T18), and the right end of the eighteenth wire section (T18) are connected to the lower end of the nineteenth wire section (T19) and the twentieth wire section at the same time. The left end of (T20), the right end of the fifteenth wire section (T15) and the right end of the twentieth wire section (T20) are simultaneously connected to the left end of the twenty-first wire section (T21), and the twenty-first wire section (T21 ) is connected to the lower end of the twenty-second wire section (T22) and the left end of the twenty-third wire section (T23) at the same time, and the upper end of the twenty-second wire section (T22) is simultaneously connected to the grounded fourth capacitor (C4) and the drain Bias voltage (Vds), the right end of the twenty-third line segment (T23) is connected to the lower end of the twenty-fourth line segment (T24) and the left end of the twenty-fifth line segment (T25) at the same time, and the twenty-fifth line segment ( The right end of T25) is connected to the left end of the fifth capacitor (C5), the right end of the fifth capacitor (C5) is connected to the left end of the twenty-sixth line segment (T26), and the right end of the twenty-sixth line segment (T26) is connected to the output load ( Zload) for signal output.

The output matching network of the broadband power amplifier is shown in FIG. 2 , including the harmonic control network shown in the dashed box G, the 22nd line node (T22) connected in parallel, and the fundamental wave matching network shown in the dashed box H. The harmonic control network is used for harmonic control, and the fundamental matching network is used for fundamental matching. The symbol Z _A /θ _A represents the characteristic impedance/electrical length of the eleventh wire section (T11), the fifteenth wire section (T15), the sixteenth wire section (T16) and the twentieth wire section (T20), Z _B /θ _B represents the characteristic impedance/electrical length of the twelfth wire section (T12), the fourteenth wire section (T14), the seventeenth wire section (T17) and the nineteenth wire section (T19), Z _C /θ _C represents the characteristic impedance/electrical length of the thirteenth wire section (T13) and the eighteenth wire section (T18), Z _D /θ _D indicates the characteristics of the tenth wire section (T10) and the twenty-first wire section (T21) Impedance/electrical length, Z ₁ /θ ₁ represents the characteristic impedance/electrical length of the twenty-third wire section (T23), Z ₂ /θ ₂ represents the characteristic impedance/electrical length of the twenty-fifth wire section (T25), Z ₃ / _θ3 represents the characteristic impedance/electrical length of the twenty-fourth wire segment (T24). Z′ _load , Z″ _load and Z _in respectively represent the input impedance seen in the corresponding direction. The electrical length of the twenty-second wire segment (T22) is set to λ/4, where λ is the waveguide wavelength at the center frequency f _M of the broadband power amplifier .

The input impedance Z _in of the output matching network shown in FIG. 2 is derived below. First analyze the network composed of the 22nd wire node (T22) in parallel and the fundamental wave matching network shown in the dotted box H, as shown in Figure 3. The input impedance Z″ _load shown in the figure is derived below. The ABCD matrix of the fundamental wave matching network shown in the dotted box H is denoted as [ABCD] _NH , which is expressed as

The elements A ₁ , B ₁ , C ₁ and D ₁ of [ABCD] _NH are respectively

The input impedance Z' _load as shown in the figure can be obtained as

Assume that the lower side frequency of the passband of the broadband power amplifier is f _L , the upper side frequency of the pass band is f _H , and the center frequency is f _M =(f _L +f _H )/2. These three frequencies are called fundamental frequencies, and their corresponding second harmonic frequencies are 2f _L , 2f _M and 2f _H , respectively. Let λ be the waveguide wavelength at the center frequency f _M of the fundamental wave, and the electrical length of the twenty-second wire segment (T22) is set to be λ/4,. Therefore, at the fundamental center frequency f _M , the Z″ _load can be viewed as the parallel connection of the Z′ _load and the quarter-wave short. Note that the input impedance of the quarter-wave short is infinite. Therefore, at the fundamental wave At the center frequency f _M ,

Next, the harmonic control network shown in the dotted box G is analyzed. The harmonic control network is formed by connecting three parts: the tenth wire section (T10) is connected to the left end of the network (referred to as network F) shown by the dotted box F, and the right end of the network F is connected to the twenty-first wire section (T21 ). Further, the network F is formed in parallel by the network shown by the dashed box E (referred to as the network E) and the network shown by the dashed box E' (referred to as the network E'). The network E and the network E' are symmetrical, and the network E is shown in FIG. 4 . The ABCD matrices of the eleventh line segment (T11), the twelfth line segment (T12) and the thirteenth line segment (T13) are:

where Z _A =Z _C .

Therefore, the ABCD matrix of the network E is denoted as the matrix [ABCD] _NE , and its expression is as follows:

where the elements A, B, C and D in [ABCD] _NE are respectively

Network F is formed by parallel connection of network E and network E', and network E and network E' are symmetrical. The ABCD matrix [ABCD] _NF of the network F is obtained as:

Further, the ABCD matrix of the harmonic control network shown in the dotted box G is obtained, denoted as [ABCD] _NG , and its expression is as follows:

Among them, the elements A', B', C' and D' of [ABCD] _NG are respectively

The input impedance Z _in seen from the left end of the harmonic control network shown in the dashed box G is expressed as

The design steps of a broadband power amplifier are summarized as follows:

Step 1: Select an appropriate quiescent operating point and determine the gate bias voltage Vgs and drain bias voltage Vds.

Step 2: After determining the bias voltage, design an appropriate bias network and stabilization circuit.

Step 3: Determine the working frequency bands f _L and f _H of the design, calculate the center frequency as f _M = (f _L +f _H )/2, and find the source and load terminals of the transistor through the method of multiple harmonic source load pull High efficiency impedance space at fundamental frequencies f _L , f _M and f _H and second harmonic frequencies 2f _L , 2f _M and 2f _H.

Step 4: Determine the parameters Z ₁ , Z ₂ , Z ₃ , Z _A , Z _B and Z _D and θ ₁ , θ ₂ , θ ₃ , θ _A , θ _B , θ _C and θ _D , according to formula (3) and (10) Calculate the impedance values of Z′ _load and Z _in at the fundamental frequency f _L , f _M and f _H and the second harmonics 2f _L , 2f _M and 2f _H so that they are located in the high-efficiency impedance space.

Step 5: Combine the overall schematic diagram simulation and optimization of the bias network, the stabilization circuit and the matching network to make it meet the design specifications; finally, optimize the layout, and then carry out the physical processing and testing.

The beneficial effects of the broadband power amplifier of the present invention are: on the premise of ensuring high efficiency, the characteristics of broadband operation can be obtained; the design process is simple, and the debugging is easy.

Description of drawings

Figure 1: Schematic diagram of the structure of a broadband power amplifier;

Figure 2: Schematic diagram of the output matching network structure;

Figure 3: A schematic diagram of a network composed of the 22nd wire section (T22) in parallel and the fundamental wave matching network shown in the dotted box H;

Figure 4: Schematic diagram of network E;

Figure 5: Variation curve diagram of the input impedance Zin of the output matching network of the embodiment in the frequency range of 0.3 to 2.0 GHz;

Fig. 6: The variation curve of the input impedance Zin of the output matching network of the embodiment in the frequency range of 2.1-4.0GHz;

Figure 7: Example simulation and test results graph.

Detailed ways

In order to reflect the inventiveness and novelty of the present invention, the implementation and effects of the technical solutions are discussed below with the help of examples. In the analysis process, the description will be made with reference to the accompanying drawings and specific embodiments, but the embodiments of the present invention are not limited thereto.

Without loss of generality, a common microstrip substrate is selected in the embodiment, the relative permittivity of which is 3.66, and the thickness of the substrate is 0.508 mm.

The working frequency band of the embodiment is set to 0.3-2.0 GHz. Therefore, f _L is 0.3 GHz, f _H is 2.0 GHz, and the center frequency f _M is 1.2 GHz, and these three frequencies are called fundamental frequencies.

At the three fundamental frequencies, the values of θ _A are 2°, 5° and 7°, the values of θ _B are 1°, 2° and 3°, and the values of θ _C are 1° and 2°. and 3°, the values of θ _D are 1°, 3° and 4°, respectively, and the values of Z _A , Z _B and Z _D are set to 44Ω, 94Ω and 60Ω, respectively. According to formula (10), it can be calculated that the impedance values of Z _in at the fundamental frequencies f _L , f _M and f _H and the second harmonics 2f _L , 2f _M and 2f _H are respectively as follows:

These impedance values all fall within the high-efficiency impedance space. Figures 5 and 6 show the graphs of the fundamental and second harmonic impedances at the output of the transistor after tuning and optimization. Figure 5 shows the change curve of the input impedance Zin of the output matching network in the frequency range of 0.3 to 2.0 GHz. Figure 6 shows the change curve of the input impedance Zin of the output matching network in the frequency range of 2.1 to 4.0 GHz. It can be seen from the figure that the input impedance Zin is located in the high-efficiency impedance space at the fundamental frequency at f _L =0.3 GHz, f _M =1.2 GHz and f _H =2.0 GHz. In addition, the input impedance Zin is located approximately in the high-efficiency impedance space at the second harmonic, thereby enabling high-efficiency power output over the entire design frequency range.

The gate bias voltage (Vgs) of the embodiment is -2.8V, the drain bias voltage (Vds) is 28V, and the transistors are CGH40010F field effect transistors. After the drive test is performed by adding a continuous wave signal at the input, Figure 7 shows the comparison between the measured results and the simulation results. It can be seen that in the range of 0.3 to 2.0 GHz, when the input signal power is 28 dBm, the saturated output power Pout is between 39.1 to 41.8 dBm, and the drain efficiency DE of 60.8% to 66.4% is obtained. Between 11.0 and 13.9dB. The relative bandwidth of the embodiment is as high as 147.8%, and the characteristics of broadband operation are realized while maintaining high efficiency.

The above-listed embodiments fully demonstrate that the broadband power amplifier of the present invention achieves the advantages of broadband operation under the premise of ensuring efficiency, and also has the advantages of simple design process and other advantages, and reflects significant technical progress. Those of ordinary skill in the art will appreciate that the embodiments described herein are intended to assist readers in understanding the principles of the present invention, and it should be understood that the scope of protection of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations without departing from the essence of the present invention according to the technical teaching disclosed in the present invention, and these modifications and combinations still fall within the protection scope of the present invention.

Claims (1)

1. A wideband power amplifier, characterized by: a signal is Input from an Input port (Input), the Input port (Input) is connected to the left end of a first wire (T1), the right end of the first wire (T1) is connected to the left end of a first capacitor (C1), the right end of a first capacitor (C1) is connected to the left end of a second wire (T2), the right end of the second wire (T2) is connected to the lower end of a third wire (T3) and the left end of a fourth wire (T4), the right end of a fourth wire (T4) is connected to the left end of a first resistor (R1) and the left end of a second capacitor (C2), the right end of the first resistor (R1) and the right end of a second capacitor (C2) are connected to the lower end of a fifth wire (T5) and the left end of a seventh wire (T7), the upper end of the fifth wire (T5) is connected to the lower end of the second resistor (R2), the upper end of the sixth wire (R2) is connected to the upper end of a sixth wire (T4642), and the upper end of a gate bias voltage (Vgs (T3) are connected to the third wire (T6), the right end of the seventh wire segment (T7) is connected to the left end of the eighth wire segment (T8), the right end of the eighth wire segment (T8) is connected to the gate of the Field Effect Transistor (FET), the source of the Field Effect Transistor (FET) is grounded, the drain of the Field Effect Transistor (FET) is connected to the left end of the ninth wire segment (T9), the right end of the ninth wire segment (T9) is connected to the left end of the tenth wire segment (T10), the right end of the tenth wire segment (T10) is connected to the left end of the eleventh wire segment (T11) and the left end of the sixteenth wire segment (T16), the right end of the eleventh wire segment (T11) is connected to the upper end of the twelfth wire segment (T12) and the left end of the thirteenth wire segment (T13), the right end of the thirteenth wire segment (T13) is connected to the upper end of the fourteenth wire segment (T14) and the left end of the fifteenth wire segment (T15), the right end of the sixteenth wire segment (T16) is connected to the lower end of the seventeenth wire segment (T18), the right end of an eighteenth wire joint (T18) is simultaneously connected with the lower end of a nineteenth wire joint (T19) and the left end of a twentieth wire joint (T20), the right end of a fifteenth wire joint (T15) and the right end of a twentieth wire joint (T20) are simultaneously connected with the left end of a twentieth wire joint (T21), the right end of a twentieth wire joint (T21) is simultaneously connected with the lower end of a twentieth wire joint (T22) and the left end of a twentieth wire joint (T23), the upper end of a twentieth wire joint (T22) is simultaneously connected with a grounded fourth capacitor (C4) and a drain bias voltage (Vds), the right end of a twentieth wire joint (T23) is simultaneously connected with the lower end of a twentieth wire joint (T24) and the left end of a twentieth wire joint (T25), the right end of a twentieth wire joint (T2) is connected with the left end of a fifth capacitor (C8), the right end of a fifth capacitor (C5) is connected with the right end of a twentieth wire joint (T59692), and the right end of a twenty wire joint (Zload signal output is carried out by a twenty load signal load output.

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