CN113258889B - Broadband power amplifier - Google Patents
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- CN113258889B CN113258889B CN202110330159.XA CN202110330159A CN113258889B CN 113258889 B CN113258889 B CN 113258889B CN 202110330159 A CN202110330159 A CN 202110330159A CN 113258889 B CN113258889 B CN 113258889B
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- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 description 12
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
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Abstract
The invention provides a broadband power amplifier, which adopts a novel output matching network based on an annular structure, overcomes the problem that the output impedance of a transistor changes violently along with the frequency in a broadband working frequency band, and realizes effective matching of the output impedance of the transistor. The input impedance curve of the output matching network is in the working frequency band range, and can fall into a high-efficiency impedance space of the transistor obtained by multiple times of harmonic source load traction, and effective control of second harmonic of the output matching network is achieved. The test result of the embodiment shows that when the input power is 28dBm, the saturated output power is 39.1-41.8 dBm within the frequency band range of 0.3-2.0GHz, the Drain Efficiency (DE) is between 60.8% -66.4%, the gain is between 11-13.9 dB, and the relative bandwidth is as high as 147.8%.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a microstrip power amplifier with broadband performance.
Background
Power amplifiers are the main components in radio frequency transmission systems. The signal passes through a radio frequency power amplifier to obtain enough radio frequency output power, and then the signal can be fed to an antenna to be transmitted. In higher frequency bands such as radio frequency/microwave, the power amplifier realized based on lumped parameter elements is limited by the difficulty of realizing the device. The microstrip line has the advantages of small volume, light weight, wide use frequency band, high reliability, low manufacturing cost and the like, and is a high-frequency transmission line with wide application. The microstrip lines have distributed parameter effect, and the electrical characteristics thereof are closely related to the structure size. Therefore, microstrip power amplifiers are an important implementation form in higher frequency bands such as radio frequency/microwave. The main technical indicators of the microstrip power amplifier are bandwidth, efficiency, output power, and so on.
Disclosure of Invention
In order to overcome the defect of insufficient bandwidth of the traditional microstrip power amplifier. The invention provides a novel microstrip power amplifier which can realize broadband performance. Compared with the existing similar power amplifier, the broadband high-efficiency power amplifier has the advantages of broadband, high efficiency and the like. Hereinafter, simply referred to as a broadband power amplifier.
The topology structure of the broadband power amplifier is shown in fig. 1, and is characterized in that: a signal is Input from an Input port (Input), the Input port (Input) is connected to the left end of a first wire joint (T1), the right end of the first wire joint (T1) is connected with the left end of a first capacitor (C1), the right end of a first capacitor (C1) is connected to the left end of a second wire joint (T2), the right end of the second wire joint (T2) is connected with the lower end of a third wire joint (T3) and the left end of a fourth wire joint (T4) at the same time, the right end of a fourth wire joint (T4) is connected with the left end of a first resistor (R1) and the left end of a second capacitor (C23) in parallel, the right end of a first resistor (R1) and the right end of a second capacitor (C2) are connected with the lower end of a fifth wire joint (T5) and the left end of a seventh wire joint (T7) in parallel, the upper end of the fifth wire joint (T5) is connected with the lower end of the second resistor (R2), the upper end of the second resistor (R2) is connected with the upper end of the sixth wire joint (T4642) and the upper end of a sixth wire joint (T6) is connected with the upper end of a third wire joint (T6) and a third wire joint (T6) bias voltage, the right end of a seventh wire section (T7) is connected with the left end of an eighth wire section (T8), the right end of an eighth wire section (T8) is connected with the gate of a Field Effect Transistor (FET), the source of the Field Effect Transistor (FET) is grounded, the drain of the Field Effect Transistor (FET) is connected with the left end of a ninth wire section (T9), the right end of a ninth wire section (T9) is connected with the left end of a tenth wire section (T10), the right end of the tenth wire section (T10) is connected with the left end of an eleventh wire section (T11) and the left end of a sixteenth wire section (T16) at the same time, the right end of an eleventh wire section (T11) is connected with the upper end of a tenth wire section (T12) and the left end of a thirteenth wire section (T13) at the same time, the right end of a thirteenth wire section (T13) is connected with the upper end of a fourteenth wire section (T14) and the left end of a fifteenth wire section (T15) at the right end of a sixteenth wire section (T3626) at the same time, and the left end of a sixteenth wire section (T16) is connected with the left end of a seventeenth wire section (T18) and the left end of a seventeenth wire section (T18) at the left end of a seventeenth wire section (18) at the same time, the right end of an eighteenth wire joint (T18) is simultaneously connected with the lower end of a nineteenth wire joint (T19) and the left end of a twentieth wire joint (T20), the right end of a fifteenth wire joint (T15) and the right end of a twentieth wire joint (T20) are simultaneously connected with the left end of a twentieth wire joint (T21), the right end of a twentieth wire joint (T21) is simultaneously connected with the lower end of a twentieth wire joint (T22) and the left end of a twentieth wire joint (T23), the upper end of a twentieth wire joint (T22) is simultaneously connected with a grounded fourth capacitor (C4) and a drain bias voltage (Vds), the right end of a twentieth three wire joint (T23) is simultaneously connected with the lower end of a twentieth wire joint (T24) and the left end of a twentieth wire joint (T25), the right end of a twentieth wire joint (T25) is connected with the left end of a fifth capacitor (C5), the right end of a fifth capacitor (C5) is connected with the right end of a twenty-sixth wire joint (T26) for outputting a twenty load signal, and the right end of a twenty load (Zload is connected with the right end (Zload.
The output matching network of the broadband power amplifier is shown in fig. 2 and comprises a harmonic control network shown by a dashed box G, a twentieth wire joint (T22) connected in parallel and a fundamental wave matching network shown by a dashed box H. The harmonic control network is used for harmonic control, and the fundamental wave matching network is used for fundamental wave matching. Symbol Z A /θ A Represents the characteristic impedance/electrical length, Z, of the tenth (T11), fifteenth (T15), sixteenth (T16) and twentieth (T20) line segments B /θ B Representing the characteristic impedance/electrical length, Z, of the tenth (T12), fourteenth (T14), seventeenth (T17) and nineteenth (T19) wire segments C /θ C Represents the characteristic impedance/electrical length, Z, of the tenth (T13) and eighteenth (T18) nodes D /θ D Representing the characteristic impedance/electrical length, Z, of the tenth (T10) and twentieth (T21) line segments 1 /θ 1 Representing the characteristic impedance/electrical length, Z, of the twentieth wire node (T23) 2 /θ 2 Representing the characteristic impedance/electrical length, Z, of the twenty-fifth line segment (T25) 3 /θ 3 The characteristic impedance/electrical length of the twenty-fourth node (T24) is shown. Z' load 、Z″ load And Z in Respectively representing the input impedance seen in the corresponding direction. The electrical length of the twentieth wire segment (T22) is set to λ/4, where λ is the wideband power amplifier center frequency f M At the waveguide wavelength.
The input impedance Z of the output matching network shown in FIG. 2 is derived in . First, the twenty-second wire joint connected in parallel is analyzed(T22) and a fundamental matching network shown by the dashed box H, as shown in fig. 3. The input impedance Z "as shown is derived below load . The ABCD matrix of the fundamental matching network shown by the dashed box H is marked as [ ABCD] NH Is shown as
[ABCD] NH Element A of (A) 1 、B 1 、C 1 And D 1 Are respectively as
An input impedance Z 'as shown can be obtained' load Is composed of
Let the passband lower-side frequency of the wide-band power amplifier be f L The upper side frequency of the passband is f H Center frequency of f M =(f L +f H )/2. These three frequencies are called fundamental frequencies, and the corresponding second harmonic frequencies are 2f L 、2f M And 2f H . Let λ be fundamental central frequency f M At the waveguide wavelength, the electrical length of the twentieth wire segment (T22) is set to be λ/4,. Therefore, the temperature of the molten metal is controlled,at the fundamental center frequency f M Here, Z ″) load Can be regarded as Z' load Parallel to the short-circuit line of quarter wavelength. Note that the input impedance of the quarter-wave shorting line is infinite. Thus at the fundamental center frequency f M At the position of the air compressor, the air compressor is started,
the harmonic control network shown by the dashed box G is then analyzed. The harmonic control network is formed by connecting three parts of networks: the tenth node (T10) is connected to the left end of the network (abbreviated as network F) shown by the dashed box F, and the right end of the network F is connected to the twentieth node (T21). Further, the network F is formed by connecting a network indicated by a dashed box E (simply referred to as network E) and a network indicated by a dashed box E '(simply referred to as network E') in parallel. The network E is symmetrical to the network E', which is shown in fig. 4. The ABCD matrices of the eleventh line segment (T11), the tenth line segment (T12), and the thirteenth line segment (T13) are:
wherein, Z A =Z C 。
Thus, the ABCD matrix of network E is denoted as matrix [ ABCD ]] NE The expression is as follows:
wherein, [ ABCD] NE Wherein elements A, B, C and D are each
The network F is formed by connecting the network E and the network E 'in parallel, and the network E' are symmetrical. Obtaining the ABCD matrix [ ABCD ] of the network F] NF Comprises the following steps:
further, an ABCD matrix of the harmonic control network shown by a dotted line frame G is obtained and is marked as [ ABCD ]] NG The expression is as follows:
wherein, [ ABCD] NG The elements A ', B', C 'and D' are respectively
Input impedance Z looking into the left end of the harmonic control network as indicated by the dashed box G in Is shown as
The design steps of the broadband power amplifier are summarized as follows:
and Step 1, selecting a proper static working point, and determining a gate bias voltage Vgs and a drain bias voltage Vds.
And Step 2, after the bias voltage is determined, designing a proper bias network and a proper stabilizing circuit.
Step 3, determining the designed working frequency band f L And f H Calculating the center frequency of f M =(f L +f H ) And/2, finding the source end and the load end of the transistor at the fundamental frequency f by a method of multiple harmonic source load traction L 、f M And f H And second harmonic frequency 2f L 、 2f M And 2f H A high efficiency impedance space.
Step 4, determining parameter Z 1 、Z 2 、Z 3 、Z A 、Z B And Z D And theta 1 、θ 2 、θ 3 、θ A 、θ B 、θ C And theta D Z 'is calculated according to formulas (3) and (10)' load And Z in At the fundamental frequency f L 、f M And f H And second harmonic 2f L 、2f M And 2f H So that it is located in the high efficiency impedance space.
Step 5, combining the bias network, the stabilizing circuit and the matching network to perform overall schematic diagram simulation and optimization so as to enable the overall schematic diagram to meet design indexes; and finally, optimizing the layout, and then processing and testing the real object.
The broadband power amplifier has the beneficial effects that: on the premise of ensuring high efficiency, the broadband working characteristic is obtained; the design process is simple, and the debugging is easy.
Drawings
FIG. 1: the structure schematic diagram of the broadband power amplifier;
FIG. 2: outputting a structural schematic diagram of the matching network;
FIG. 3: a twenty-second wire joint (T22) is connected in parallel with a schematic diagram of a network formed by a fundamental wave matching network shown by a dashed box H;
FIG. 4: a network E schematic;
FIG. 5: the change curve diagram of the input impedance Zin of the output matching network in the frequency range of 0.3-2.0GHz is provided by the embodiment;
FIG. 6: the change curve diagram of the input impedance Zin of the output matching network in the frequency range of 2.1-4.0 GHz is provided by the embodiment;
FIG. 7 is a schematic view of: example simulation and test results plots.
Detailed Description
In order to embody the inventiveness and novelty of the present invention, the implementation and effect of the further technical solution are made below by means of the examples. In the analysis, the embodiments of the present invention will be described with reference to the drawings and specific examples, but the embodiments are not limited thereto.
Without loss of generality, the embodiment selects a common microstrip substrate with a relative dielectric constant of 3.66 and a substrate thickness of 0.508 mm.
The working frequency band of the embodiment is set to be 0.3-2.0 GHz. Thus, f L Is 0.3GHz, f H At 2.0GHz and a center frequency f M At 1.2GHz, these three frequencies are referred to as the fundamental frequencies.
At three fundamental frequencies, take θ A Are 2 °, 5 ° and 7 °, θ, respectively B Are respectively 1 DEG, 2 DEG and 3 DEG theta C Are respectively 1 DEG, 2 DEG and 3 DEG theta D Are respectively 1 DEG, 3 DEG and 4 DEG, Z A 、Z B And Z D The values of (d) are set to 44 Ω, 94 Ω, and 60 Ω, respectively. Can be calculated according to the formula (10) Z in At the fundamental frequency f L 、f M And f H And second harmonic 2f L 、2f M And 2f H The impedance values are as follows:
these impedance values all fall within the high efficiency impedance space range. Graphs of the fundamental and second harmonic impedances at the output of the transistor after final tuning and optimization are shown in fig. 5 and 6. FIG. 5 shows a variation curve of the input impedance Zin of the output matching network in the frequency range of 0.3 to 2.0 GHz. FIG. 6 shows a variation curve of the input impedance Zin of the output matching network in the frequency range of 2.1 to 4.0 GHz. It can be seen from the figure that the input impedance Zin is at the fundamental frequency f L =0.3GHz、f M 1.2GHz and f H All located in the high efficiency impedance space at 2.0 GHz. Furthermore, the input impedance Zin is approximately within the high efficiency impedance space at the second harmonic, enabling high efficiency power output over the entire design frequency band.
The gate bias voltage (Vgs) of the example was-2.8V, the drain bias voltage (Vds) was 28V, and the transistor was a CGH40010F field effect transistor. After the continuous wave signal is added through the input end to carry out the drive test, a comparison graph of the actual measurement result and the simulation result is given in fig. 7. It can be seen that, in the range of 0.3 to 2.0GHz, when the input signal power is 28dBm, the saturated output power Pout is 39.1 to 41.8dBm, the drain efficiency DE of 60.8 to 66.4 percent is obtained, and the gain is 11.0 to 13.9 dB. The relative bandwidth of the embodiment is as high as 147.8%, and the characteristic of broadband operation is realized while high efficiency is maintained.
The embodiments listed above fully demonstrate that the broadband power amplifier of the present invention achieves the advantage of broadband operation on the premise of ensuring efficiency, and has the advantages of simple design process, etc., thereby representing significant technical progress. It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto and changes may be made without departing from the scope of the invention in its aspects.
Claims (1)
1. A wideband power amplifier, characterized by: a signal is Input from an Input port (Input), the Input port (Input) is connected to the left end of a first wire (T1), the right end of the first wire (T1) is connected to the left end of a first capacitor (C1), the right end of a first capacitor (C1) is connected to the left end of a second wire (T2), the right end of the second wire (T2) is connected to the lower end of a third wire (T3) and the left end of a fourth wire (T4), the right end of a fourth wire (T4) is connected to the left end of a first resistor (R1) and the left end of a second capacitor (C2), the right end of the first resistor (R1) and the right end of a second capacitor (C2) are connected to the lower end of a fifth wire (T5) and the left end of a seventh wire (T7), the upper end of the fifth wire (T5) is connected to the lower end of the second resistor (R2), the upper end of the sixth wire (R2) is connected to the upper end of a sixth wire (T4642), and the upper end of a gate bias voltage (Vgs (T3) are connected to the third wire (T6), the right end of the seventh wire segment (T7) is connected to the left end of the eighth wire segment (T8), the right end of the eighth wire segment (T8) is connected to the gate of the Field Effect Transistor (FET), the source of the Field Effect Transistor (FET) is grounded, the drain of the Field Effect Transistor (FET) is connected to the left end of the ninth wire segment (T9), the right end of the ninth wire segment (T9) is connected to the left end of the tenth wire segment (T10), the right end of the tenth wire segment (T10) is connected to the left end of the eleventh wire segment (T11) and the left end of the sixteenth wire segment (T16), the right end of the eleventh wire segment (T11) is connected to the upper end of the twelfth wire segment (T12) and the left end of the thirteenth wire segment (T13), the right end of the thirteenth wire segment (T13) is connected to the upper end of the fourteenth wire segment (T14) and the left end of the fifteenth wire segment (T15), the right end of the sixteenth wire segment (T16) is connected to the lower end of the seventeenth wire segment (T18), the right end of an eighteenth wire joint (T18) is simultaneously connected with the lower end of a nineteenth wire joint (T19) and the left end of a twentieth wire joint (T20), the right end of a fifteenth wire joint (T15) and the right end of a twentieth wire joint (T20) are simultaneously connected with the left end of a twentieth wire joint (T21), the right end of a twentieth wire joint (T21) is simultaneously connected with the lower end of a twentieth wire joint (T22) and the left end of a twentieth wire joint (T23), the upper end of a twentieth wire joint (T22) is simultaneously connected with a grounded fourth capacitor (C4) and a drain bias voltage (Vds), the right end of a twentieth wire joint (T23) is simultaneously connected with the lower end of a twentieth wire joint (T24) and the left end of a twentieth wire joint (T25), the right end of a twentieth wire joint (T2) is connected with the left end of a fifth capacitor (C8), the right end of a fifth capacitor (C5) is connected with the right end of a twentieth wire joint (T59692), and the right end of a twenty wire joint (Zload signal output is carried out by a twenty load signal load output.
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