CN114978045A - Dual-frequency Doherty power amplifier and radio frequency discrete device - Google Patents
Dual-frequency Doherty power amplifier and radio frequency discrete device Download PDFInfo
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
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Abstract
The invention discloses a dual-frequency Doherty power amplifier and a radio frequency discrete device, wherein the amplifier comprises: the circuit comprises an input circuit, a first amplifying circuit, a second amplifying circuit and an output circuit; the first amplifying circuit and the second amplifying circuit have the same circuit structure and are symmetrical; the input circuit comprises a 50 ohm impedance line and a metal through hole ground; the 50 ohm impedance line is connected to the first amplifying circuit; the metal through hole is connected to the second amplifying circuit; the output end of the first amplifying circuit and the output end of the second amplifying circuit are both connected to the output circuit. According to the invention, on one hand, the stability and the gain balance circuit are subjected to compromise among gain, stability and linearity, so that the linearity of the circuit after being combined is improved, on the other hand, the impedance pre-adjusting circuit is utilized to adjust the double-frequency optimal impedance point to a close point, so that the difficulty of double-frequency matching of the output end circuit and the complexity of the circuit structure are reduced. The invention can be widely applied to the field of wireless communication.
Description
Technical Field
The invention relates to the field of wireless communication, in particular to a dual-frequency Doherty power amplifier and a radio frequency discrete device.
Background
A Power Amplifier (PA) is a key module in a transmitter of a wireless communication system, and is expensive, high in energy consumption, high in heat generation, and a strong nonlinear device, which not only directly determines the performance of the transmitter, but also affects the performance of the whole wireless communication system.
In order to enable a wireless communication system to be capable of smoothly transiting and upgrading, meet the requirements of high-capacity data transmission with high speed, accuracy and no distortion, and be compatible with existing equipment in second-generation to fourth-generation communication systems, the radio frequency front end is required to be capable of meeting multi-frequency or broadband work at the present stage. In order to meet the requirement of flexible configuration of communication frequency bands and avoid unnecessary waste of spectrum resources, the conventional single-frequency-band communication mode is obviously not suitable for the current 5G era, and therefore dual-frequency and even multi-frequency communication technologies and devices need to have excellent performance indexes. The Doherty power amplifier technology is the most widely applied power amplifier technology in the current wireless communication system, and mainly focuses on improving the backspacing efficiency, so that the Doherty power amplifier is required to meet the efficiency and the linearity and design multi-standard hardware through a multi-band solution scheme.
Therefore, the design of the power amplifier module with high performance, dual frequency bands, high back-off efficiency and high linearity has very important significance for realizing a high-performance and strong-applicability wireless transceiving system. In summary, how to improve the linearity and the back-off efficiency of the power amplifier and reduce the complexity of the circuit structure becomes a technical problem to be solved urgently.
Disclosure of Invention
To solve at least one of the technical problems in the prior art to a certain extent, an object of the present invention is to provide a dual-band Doherty power amplifier and a radio frequency discrete device.
The technical scheme adopted by the invention is as follows:
a dual-frequency Doherty power amplifier comprises an input circuit, a first amplifying circuit, a second amplifying circuit and an output circuit; the first amplifying circuit and the second amplifying circuit have the same circuit structure and are symmetrical;
the input circuit comprises a 50 ohm impedance line and a metal via ground;
one end of the 50 ohm impedance line is connected with a signal input end, and the other end of the 50 ohm impedance line is connected to the input end of the first amplifying circuit through a blocking capacitor;
the metal through hole ground is connected to the input end of the second amplifying circuit through a 50 ohm resistor;
the output end of the first amplifying circuit and the output end of the second amplifying circuit are both connected to the output circuit;
the first amplifying circuit comprises a dual-band 90-degree phase shift branch line coupler, a dual-band input matching circuit, a stabilizing and gain balancing circuit, a transistor, an impedance pre-adjusting circuit, a dual-band output matching circuit and a dual-band phase compensation line which are sequentially connected.
Further, the dual-band 90 ° phase-shifted branch line coupler includes two first transmission lines and one second transmission line;
the two first transmission lines are symmetrically arranged on two sides of the second transmission line; one end of the second transmission line is connected to the output end of the input circuit through one first transmission line, and the other end of the second transmission line is connected to the input end of the dual-frequency input matching circuit through the other first transmission line;
and a third transmission line is connected between the first transmission line on the first amplifying circuit and the corresponding first transmission line on the second amplifying circuit, and the two first transmission lines correspond to the two third transmission lines.
Furthermore, the first transmission line is rectangular, the long side of the first transmission line is connected with the second transmission line, and the short side of the first transmission line is connected with the third transmission line.
Further, the dual-frequency input matching circuit comprises a fourth transmission line, a fifth transmission line and a sixth transmission line which are sequentially connected in series;
one end of the fourth transmission line is connected with the output end of the dual-band 90-degree phase shift branch line coupler through a blocking capacitor, the other end of the fourth transmission line is connected with one end of the sixth transmission line through the fifth transmission line, and the other end of the sixth transmission line is connected to the output end of the stabilizing and gain balancing circuit;
wherein, in the dual-frequency input matching circuit, the width of the fifth transmission line is the smallest, and the width of the sixth transmission line is the largest.
Further, the stabilization and gain balancing circuit comprises an R-C parallel circuit and a seventh transmission line; the seventh transmission line is rectangular in shape;
one end of the R-C parallel circuit is connected with the output end of the double-frequency input matching circuit, the other end of the R-C parallel circuit is connected with one short edge of the seventh transmission line, and the other short edge of the seventh transmission line is connected to the grid of the transistor.
Further, the first amplifying circuit further comprises a dual-frequency gate bias circuit, and the dual-frequency gate bias circuit comprises a stabilizing resistor, a fifteenth transmission line, a sixteenth transmission line, a seventeenth transmission line, an eighteenth transmission line and a first bypass capacitor;
one end of the stabilizing resistor is connected with the long edge of the seventh transmission line, the other end of the stabilizing resistor is connected with one end of the sixteenth transmission line, the other end of the sixteenth transmission line is connected with one end of the eighteenth transmission line, and the other end of the eighteenth transmission line is connected to a grid voltage source VGS;
one end of the fifteenth transmission line is connected to one end of the sixteenth transmission line, one end of the seventeenth transmission line is connected to one end of the eighteenth transmission line, one end of the first bypass capacitor is connected to the eighteenth transmission line, and the other end of the first bypass capacitor is grounded.
Further, the dual-frequency output matching circuit comprises an eighth transmission line and a ninth transmission line which are connected in series;
one end of the eighth transmission line is connected with the output end of the impedance pre-adjusting circuit, the other end of the eighth transmission line is connected with one end of the ninth transmission line, and the other end of the ninth transmission line is connected with the input end of the dual-frequency output matching circuit;
the impedance pre-adjusting circuit is an impedance pre-adjusting transmission line, and the width of the impedance pre-adjusting transmission line is smaller than that of the eighth transmission line and larger than that of the ninth transmission line.
Further, the first amplifying circuit further comprises a dual-frequency drain biasing circuit, and the dual-frequency drain biasing circuit comprises a nineteenth transmission line, a twentieth transmission line, a twenty-first transmission line, a twenty-second transmission line and a second bypass capacitor;
one end of the twentieth transmission line is connected to the impedance pre-conditioning transmission line, the other end of the twentieth transmission line is connected to one end of the twenty-second transmission line, and the other end of the twenty-second transmission line is connected to a drain voltage source VDS;
one end of the nineteenth transmission line is connected to one end of the twentieth transmission line, one end of the twenty-first transmission line is connected to one end of the twenty-second transmission line, the second bypass capacitor is connected to the twenty-second transmission line, and the other end of the second bypass capacitor is grounded.
Further, the output circuit includes a dual-frequency impedance transformer including a tenth transmission line, an eleventh transmission line, a twelfth transmission line, a thirteenth transmission line, and a fourteenth transmission line; the tenth transmission line, the twelfth transmission line, the thirteenth transmission line and the fourteenth transmission line are all rectangular in shape;
one long side of the tenth transmission line is connected with the double-frequency phase compensation line on the first amplifying circuit, one short side of the tenth transmission line is connected with one end of the eleventh transmission line, and the other end of the eleventh transmission line is connected with the short plate of the twelfth transmission line;
one long side of the twelfth transmission line is connected with the double-frequency phase compensation line on the second amplification circuit, the other long side of the twelfth transmission line is connected with one short side of the thirteenth transmission line, and the other short side of the thirteenth transmission line is connected with the long side of the fourteenth transmission line.
The other technical scheme adopted by the invention is as follows:
a radio frequency discrete device comprising a dual-frequency Doherty power amplifier as described above.
The invention has the beneficial effects that: on one hand, the stability and gain balance circuit makes a compromise among gain, stability and linearity, so that the linearity of the circuit after combination is improved; on the other hand, the impedance pre-adjusting circuit is used for adjusting the double-frequency optimal impedance point to a close point, so that the difficulty of double-frequency matching of an output end circuit is reduced; and the single-frequency assembly is replaced by the double-frequency assembly, for the open-circuit short segment lines connected to the same node, the structure can be simplified by combining the parallel open-circuit short segment lines, the line length of the combined open-circuit short segment lines is unchanged, but the impedance is the square root of the product of the impedances of the two parallel open-circuit short segment lines, and the complexity of the circuit structure is greatly reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description is made on the drawings of the embodiments of the present invention or the related technical solutions in the prior art, and it should be understood that the drawings in the following description are only for convenience and clarity of describing some embodiments in the technical solutions of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a joint simulation diagram of a dual-frequency Doherty power amplifier in an embodiment of the present invention;
fig. 2 is a schematic diagram of dual-frequency gain balancing of a dual-frequency Doherty power amplifier in an embodiment of the present invention;
fig. 3 is a smith chart of a main power amplifier dual-frequency pre-conditioning output impedance (t) and load pulling impedance (●) of a dual-frequency Doherty power amplifier in an embodiment of the invention;
fig. 4 is a smith chart of the auxiliary power amplifier dual-frequency pre-conditioning output impedance (t) and load pulling impedance (●) of a dual-frequency Doherty power amplifier in an embodiment of the invention;
fig. 5 is a schematic diagram of a dual-band two-segment microstrip line output matching network of a dual-band Doherty power amplifier in an embodiment of the present invention;
fig. 6 is a simulation diagram of S parameters of a dual-frequency output matching network of a main power amplifier Cr and an auxiliary power amplifier Pk of a dual-frequency Doherty power amplifier in the embodiment of the invention;
fig. 7 is a simulation diagram of the S parameter of the dual-frequency Doherty power amplifier in the embodiment of the present invention;
fig. 8 is a stability simulation diagram of a dual-band Doherty power amplifier of the dual-band Doherty power amplifier in the embodiment of the present invention;
fig. 9 is a simulation graph of Power Added Efficiency (PAE) and Gain (Gain) of a dual-band Doherty pa according to an embodiment of the present invention as a function of output power (Pout);
fig. 10 is a simulation graph of the output power (Pout) as a function of the input power (Pin) for a dual-frequency Doherty power amplifier in an embodiment of the present invention;
fig. 11 is a smith chart of the change of the output impedance of the current source plane with the input power at the frequency of 1.8GHz of the dual-frequency Doherty power amplifier in the embodiment of the present invention;
fig. 12 is a smith chart of the output impedance of the current source plane as a function of the input power at a frequency of 5.8GHz for a dual-frequency Doherty power amplifier in accordance with an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. The step numbers in the following embodiments are provided only for convenience of illustration, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.
In the prior art, the following problems mainly exist: (1) the compromise between gain and stability at two frequency points in a dual-frequency DPA (power amplifier driver) is usually accompanied by a decrease in the frequency stability and a decrease in the gain at the other frequency point when the gain of one frequency point is increased for a wide frequency multiplication with a frequency ratio greater than 3, so that a performance tradeoff needs to be made between these two points. (2) The saturation gain of the dual-frequency DPA main circuit and the auxiliary circuit during independent operation influences the linearity of two frequency points after combination to a certain extent, and when the grid bias voltage of the two transistors changes, the power back-off point shifts along with the change, and proper bias voltage needs to be selected to enable the 6dB power back-off efficiency to reach the maximum as possible. (3) Research on a dual-frequency complex impedance matching network: the dual-frequency matching structure generally has several simple structures, including: t-shaped, Π -shaped structures, or multi-branch open or short circuit distribution, but their approach increases losses. Therefore, the invention is designed for the dual-frequency matching network to be simplified.
As shown in fig. 1, the present embodiment provides a dual-frequency Doherty power amplifier, including: the dual-band 90-degree phase-shift branch line coupler comprises a dual-band 90-degree phase-shift branch line coupler 1, a dual-band input matching circuit 2, a stabilizing and gain balancing circuit 3, a transistor 4, an impedance pre-adjusting circuit 5, a dual-band output matching circuit 6, a dual-band phase compensation line 7, a dual-band impedance converter 8, a dual-band gate bias circuit 9, a dual-band drain bias circuit 10, a 50-ohm impedance line 11, a bypass capacitor connecting metal through hole ground 12 and a coupler resistor connecting metal through hole ground 13.
The dual-band 90 ° phase shift branch line coupler 1 is a symmetrical structure, and includes: a first transmission line 14, a second transmission line 15, a third transmission line 16. The left upper port of the dual-band 90-degree phase shift branch line coupler 1 is connected with a 50-ohm impedance line 11 through blocking capacitors C1 and C2 to play a role of radio frequency input; the left lower port of the dual-band 90-degree phase shift branch line coupler 1 is connected with a 50-ohm resistor R1 connected with a metal through hole ground 13; the right upper port and the right lower port of the dual-band 90-degree phase shift branch line coupler 1 are respectively connected with the main circuit and the auxiliary circuit dual-frequency input matching circuit 2 of the power amplifier through the DC blocking capacitors C1 and C2.
The dual-frequency input matching circuit 2 includes: a fourth transmission line 17, a fifth transmission line 18, a sixth transmission line 19. As an alternative embodiment, the width of the fifth transmission line 18 is the smallest, and the width of the sixth transmission line 19 is the largest.
The stabilization and gain balancing circuit 3 comprises: the R-C parallel circuit 20, the seventh transmission line 21, and the 50 ohm stabilizing resistor R3; the R-C parallel circuit 20 is formed by connecting a resistor R2 and a capacitor C3 in parallel, one end of a stabilizing resistor R3 is connected with a first transmission line 21 of the double-frequency input matching network, the other end of the stabilizing resistor R3 is connected with the double-frequency gate bias circuit 9, and the right end of a seventh transmission line 21 is connected with the gate of the transistor 4.
The dual-frequency output matching circuit 6 includes: eighth and ninth transmission lines 22 and 23; the left end of the eighth transmission line 22 is connected to the impedance pre-adjusting transmission line 5.
The dual-frequency impedance transformer 8 includes: a tenth transmission line 24, an eleventh transmission line 25, a twelfth transmission line 26, a thirteenth transmission line 27, a fourteenth transmission line 28; the tenth transmission line 24 and the twelfth transmission line 26 are connected to the main and auxiliary phase compensation lines 7 at left ends thereof, respectively, and the fourteenth transmission line 28 is connected to the 50 ohm impedance line 11 at right ends thereof through dc blocking capacitors C1 and C2 to play a role of rf output.
The dual-frequency gate bias circuit 9 includes: a fifteenth transmission line 29, a sixteenth transmission line 30, a seventeenth transmission line 31, an eighteenth transmission line 32, and a bypass capacitance C4; wherein, one end of the bypass capacitor is connected with the eighteenth transmission line 32 and the grid voltage source V GS And the other ends of the bypass capacitors are all grounded.
The dual-frequency drain bias circuit 10 includes: a nineteenth transmission line 33, a twentieth transmission line 34, a twenty-first transmission line 35, a twenty-second transmission line 36, and a bypass capacitor C5; one end of the bypass capacitor is connected with the twenty-second transmission line 36 and the drain voltage source V DS And the other ends of the bypass capacitors are all grounded.
The power amplifier is further described in detail with reference to the figures and the specific embodiments.
Referring to fig. 1, the present embodiment provides a dual-frequency high-efficiency linear enhancement type Doherty power amplifier suitable for a 5G base station, where the designed operating frequency is two frequency points of 1.8GHz and 5.8GHz, and a transistor 4 is used as a 10W high power (GaN HEMT) device CG2H40010F, and the quiescent operating point of the transistor is set as: the main power amplifier is AB type, and the grid direct current voltage is Vgs-2.7V; the auxiliary power amplifier is C type, and the grid direct current voltage is Vgs-5.4V; the drain voltage is Vds-28V. The dielectric substrate selected in the embodiment is Rogers 5870, the highest limit frequency is 10GHz, the plate thickness of the dielectric substrate is 0.508mm, the relative dielectric constant is 2.33, and the metal thickness is 0.035 mm.
The dual-frequency high-efficiency linear enhancement type Doherty power amplifier suitable for the 5G base station in the embodiment comprises a dual-frequency band 90-degree phase shift branch line coupler, a dual-frequency input matching circuit, a stabilizing and gain balancing circuit, a transistor, an impedance pre-adjusting circuit, a dual-frequency output matching circuit, a dual-frequency phase compensation line, a dual-frequency impedance converter, a dual-frequency gate bias circuit and a dual-frequency drain bias circuit, as shown in fig. 1.
According to the simulation schematic diagram of the gain balancing circuit shown in fig. 2, the gain at the low frequency is reduced, so that the too serious compression of the gain after combination is effectively avoided, and the improvement of the linearity of the whole circuit is facilitated.
According to the smith charts of the dual-frequency pre-adjustment output impedance and the load traction impedance of the main power amplifier and the auxiliary power amplifier shown in fig. 3 and 4, it can be seen that the pre-adjustment output impedance at two working frequency points corresponds to the load traction impedance, and when the output impedance is pre-adjusted to the same impedance, the load traction optimal impedance is attracted to the same point.
The matching is then performed using a dual-frequency two-section microstrip line output matching network as shown in fig. 5, which shows the complex impedance Z 0 To real impedance Z L (50 Ω) matching process, first, the first transmission line will be Z in Conversion to Z L2 ，Z L2 At f 1 1.8GHz and f 2 Conjugated to each other at 5.8GHz, then Z L2 |f 1 ，f 2 Is converted into Z by a second transmission line L . The specific formula analysis is as follows:
equations (3), (4) are known conditions:
Z in ＝R 0 -jX 0 ＝Z 0 * (3)
Z L ＝R L +jX L ＝50Ω (4)
Z L2 can be expressed by both sides of equation (5):
then, the electrical length θ 1 And theta 2 At f 1 And f 2 The (2) is defined as (6), (7) to satisfy the dual-frequency condition:
θ 1 |f 1 ＝β 1 *l 1 ，θ 1 |f 2 ＝β 2 *l 1 (6)
θ 2 |f 1 ＝β 1 *l 2 ，θ 2 |f 2 ＝β2*l 2 (7)
substituting equations (6), (7) into equation (5) results in four equations containing four unknown variables. The characteristic impedance Z of the two microstrip lines is calculated by writing a script program in Matlab software 1 、Z 2 Electrical length theta 1 And theta 2 The value of (c). The simulation result of the S parameter of the dual-band output matching network of the main power amplifier (Carrier PA) and the auxiliary power amplifier (peak PA) is shown in fig. 6.
According to the small signal performance simulation diagrams of the dual-frequency high-efficiency linear enhancement type Doherty power amplifier suitable for the 5G base station shown in FIGS. 7 and 8, the power amplifier respectively has small signal gains of 12 dB and 11.5dB at 1.8GHz and 5.8GHz, the return loss S11 is less than-10 dB, and the stability K value is greater than 1.
Referring to fig. 9, a large signal performance simulation diagram of a dual-band high-efficiency linear-enhancement-mode Doherty power amplifier suitable for a 5G base station is shown in fig. 10, which includes the gain, output power and drain efficiency results of the power amplifier. Thus, the dual frequency DPA has saturated output powers of 43.1dBm and 43dBm at 1.8GHz and 5.8GHz, respectively, and peak Power Added Efficiencies (PAE) of 61.6% and 60% and power added efficiencies of 46.9% and 43.5% for a 6-dB power back-off at both operating frequencies.
Referring to fig. 11, the smith charts of the main and auxiliary power amplifiers shown in fig. 12 show that the output impedance of the current source plane changes with the input power at the dual frequency, respectively, and it can be seen that the output power is changed to about 50 ohm load at the saturation power output, thereby achieving the target.
In summary, compared with the prior art, the power amplifier of the embodiment has the following advantages and beneficial effects:
(1) and (3) enhancing the linearity: according to the invention, before the dual-frequency optimal input and output impedance obtained by the transistor through load-pull is matched to 50 omega, the gains of two frequencies are balanced by using the RC stabilizing circuit and the seventh transmission line 21 connected to the grid electrode of the transistor, as shown in fig. 2, the maximum gain of 1.8GHz is balanced to be close to the maximum gain of 5.8GHz through the seventh transmission line 21, so that the serious gain compression of the combined DPA at 1.8GHz is avoided, the compromise among gain, stability and linearity is made, and the circuit linearity after combination is improved.
(2) The matching difficulty is low: the dual-frequency output matching network disclosed by the invention is different from the traditional dual-frequency power amplifier, the matching method uses a section of microstrip transmission line connected to the drain electrode of a transistor for pre-adjusting the output impedance so as to simplify the dual-frequency output matching network, and in the existing dual-frequency PA, a complex structure is usually used for realizing the matching of two complex impedances of two frequencies to a load of 50 omega. These structures tend to increase the size and loss of the circuit and may present frequency ratio and bandwidth limitations in the calculations and analysis due to the excessive distance of the dual-frequency impedance. Whereas in the present invention, since the dual-band output impedance has been previously adjusted to almost the same impedance, the previously complicated matching process can be realized by a simple two-stage transmission line (eighth transmission line 22, ninth transmission line 23) that can match the same single impedance to 50 Ω at two frequencies at the same time.
(3) The structure is simple: the invention replaces the single-frequency component with the double-frequency component, and simplifies the structure of the open-circuit short segment wires connected to the same node by combining the parallel open-circuit short segment wires, wherein the electrical length of the combined open-circuit short segment wires is unchanged, but the impedance is the square root of the product of the impedances of the two parallel open-circuit short segment wires. And for the double-frequency phase line, the single-section microstrip line (7) is adopted to realize the equal proportion conversion of the frequency and the phase shift of the double frequency, so that the problem of bandwidth loss of the complex branch is greatly reduced.
The embodiment also provides a radio frequency discrete device, and the chip comprises a dual-frequency Doherty power amplifier as shown in fig. 1.
A radio frequency discrete device of the present embodiment has a corresponding relationship with the dual-frequency Doherty power amplifier described above, and therefore has corresponding functions and advantageous effects in the amplifier embodiment.
In the foregoing description of the specification, reference to the description of "one embodiment/example," "another embodiment/example," or "certain embodiments/examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A dual-frequency Doherty power amplifier is characterized by comprising an input circuit, a first amplifying circuit, a second amplifying circuit and an output circuit; the first amplifying circuit and the second amplifying circuit have the same circuit structure and are symmetrical;
the input circuit comprises a 50 ohm impedance line and a metal via ground;
one end of the 50 ohm impedance line is connected with a signal input end, and the other end of the 50 ohm impedance line is connected to the input end of the first amplifying circuit through a blocking capacitor;
the metal through hole ground is connected to the input end of the second amplifying circuit through a 50-ohm resistor;
the output end of the first amplifying circuit and the output end of the second amplifying circuit are both connected to the output circuit;
the first amplifying circuit comprises a dual-band 90-degree phase shift branch line coupler, a dual-band input matching circuit, a stabilizing and gain balancing circuit, a transistor, an impedance pre-adjusting circuit, a dual-band output matching circuit and a dual-band phase compensation line which are sequentially connected.
2. A dual-frequency Doherty power amplifier as claimed in claim 1, wherein said dual-band 90 ° phase-shifted branch line coupler comprises two first transmission lines and one second transmission line;
the two first transmission lines are symmetrically arranged on two sides of the second transmission line; one end of the second transmission line is connected to the output end of the input circuit through one first transmission line, and the other end of the second transmission line is connected to the input end of the double-frequency input matching circuit through the other first transmission line;
and a third transmission line is connected between the first transmission line on the first amplifying circuit and the corresponding first transmission line on the second amplifying circuit, and the two first transmission lines correspond to the two third transmission lines.
3. The dual-band Doherty power amplifier of claim 2, wherein the first transmission line has a rectangular shape, a long side of the first transmission line is connected to the second transmission line, and a short side of the first transmission line is connected to the third transmission line.
4. The dual-frequency Doherty power amplifier of claim 1, wherein the dual-frequency input matching circuit comprises a fourth transmission line, a fifth transmission line and a sixth transmission line connected in series in sequence;
one end of the fourth transmission line is connected with the output end of the dual-band 90-degree phase shift branch line coupler through a blocking capacitor, the other end of the fourth transmission line is connected with one end of the sixth transmission line through the fifth transmission line, and the other end of the sixth transmission line is connected to the output end of the stabilizing and gain balancing circuit;
wherein the fifth transmission line has a minimum width and the sixth transmission line has a maximum width.
5. The dual-frequency Doherty power amplifier of claim 1 wherein said stabilizing and gain-balancing circuit comprises an R-C parallel circuit and a seventh transmission line; the seventh transmission line is rectangular in shape;
one end of the R-C parallel circuit is connected with the output end of the double-frequency input matching circuit, the other end of the R-C parallel circuit is connected with one short edge of the seventh transmission line, and the other short edge of the seventh transmission line is connected to the grid of the transistor.
6. The dual-frequency Doherty power amplifier of claim 5, wherein the first amplifying circuit further comprises a dual-frequency gate bias circuit, the dual-frequency gate bias circuit comprising a stabilizing resistor, a fifteenth transmission line, a sixteenth transmission line, a seventeenth transmission line, an eighteenth transmission line and a first bypass capacitor;
one end of the stabilizing resistor is connected with the long edge of the seventh transmission line, the other end of the stabilizing resistor is connected with one end of the sixteenth transmission line, the other end of the sixteenth transmission line is connected with one end of the eighteenth transmission line, and the other end of the eighteenth transmission line is connected to a grid voltage source V GS ；
One end of the fifteenth transmission line is connected to one end of the sixteenth transmission line, one end of the seventeenth transmission line is connected to one end of the eighteenth transmission line, one end of the first bypass capacitor is connected to the eighteenth transmission line, and the other end of the first bypass capacitor is grounded.
7. The dual-frequency Doherty power amplifier according to claim 1, wherein said dual-frequency output matching circuit comprises an eighth transmission line and a ninth transmission line connected in series;
one end of the eighth transmission line is connected with the output end of the impedance pre-adjusting circuit, the other end of the eighth transmission line is connected with one end of the ninth transmission line, and the other end of the ninth transmission line is connected with the input end of the dual-frequency output matching circuit;
the impedance pre-adjusting circuit is an impedance pre-adjusting transmission line, and the width of the impedance pre-adjusting transmission line is smaller than that of the eighth transmission line and larger than that of the ninth transmission line.
8. The dual-frequency Doherty power amplifier of claim 7, wherein the first amplification circuit further comprises a dual-frequency drain bias circuit, the dual-frequency drain bias circuit comprising a nineteenth transmission line, a twentieth transmission line, a twenty-first transmission line, a twenty-second transmission line and a second bypass capacitor;
one end of the twentieth transmission line is connected to the impedance pre-conditioning transmission line, and the other end of the twentieth transmission line is connected to the impedance pre-conditioning transmission lineOne end of the twenty-second transmission line is connected, and the other end of the twenty-second transmission line is connected to a drain voltage source V DS ；
One end of the nineteenth transmission line is connected to one end of the twentieth transmission line, one end of the twenty-first transmission line is connected to one end of the twenty-second transmission line, the second bypass capacitor is connected to the twenty-second transmission line, and the other end of the second bypass capacitor is grounded.
9. The dual-frequency Doherty power amplifier of claim 1 wherein the output circuit comprises a dual-frequency impedance transformer, the dual-frequency impedance transformer comprising a tenth transmission line, an eleventh transmission line, a twelfth transmission line, a thirteenth transmission line and a fourteenth transmission line; the tenth transmission line, the twelfth transmission line, the thirteenth transmission line and the fourteenth transmission line are all rectangular in shape;
one long side of the tenth transmission line is connected with the double-frequency phase compensation line on the first amplifying circuit, one short side of the tenth transmission line is connected with one end of the eleventh transmission line, and the other end of the eleventh transmission line is connected with the short plate of the twelfth transmission line;
one long side of the twelfth transmission line is connected with the double-frequency phase compensation line on the second amplification circuit, the other long side of the twelfth transmission line is connected with one short side of the thirteenth transmission line, and the other short side of the thirteenth transmission line is connected with the long side of the fourteenth transmission line.
10. A radio frequency discrete device comprising a dual-frequency Doherty power amplifier as claimed in any one of claims 1 to 9.
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| CN202210539947.4A CN114978045A (en) | 2022-05-18 | 2022-05-18 | Dual-frequency Doherty power amplifier and radio frequency discrete device |
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| CN202210539947.4A CN114978045A (en) | 2022-05-18 | 2022-05-18 | Dual-frequency Doherty power amplifier and radio frequency discrete device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116707571A (en) * | 2023-08-08 | 2023-09-05 | 中国电信股份有限公司 | Signal equalization processing method and device for dual-frequency far-end radio frequency unit and related equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116707571A (en) * | 2023-08-08 | 2023-09-05 | 中国电信股份有限公司 | Signal equalization processing method and device for dual-frequency far-end radio frequency unit and related equipment |
| CN116707571B (en) * | 2023-08-08 | 2023-10-24 | 中国电信股份有限公司 | Signal equalization processing method and device for dual-frequency far-end radio frequency unit and related equipment |
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