CN113257691B - 一种降低热应力的功率模块引线互连方法 - Google Patents

一种降低热应力的功率模块引线互连方法 Download PDF

Info

Publication number
CN113257691B
CN113257691B CN202110439094.2A CN202110439094A CN113257691B CN 113257691 B CN113257691 B CN 113257691B CN 202110439094 A CN202110439094 A CN 202110439094A CN 113257691 B CN113257691 B CN 113257691B
Authority
CN
China
Prior art keywords
chip
power module
composite metal
metal block
thermal stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110439094.2A
Other languages
English (en)
Other versions
CN113257691A (zh
Inventor
梅云辉
李潇迪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianjin Polytechnic University
Original Assignee
Tianjin Polytechnic University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianjin Polytechnic University filed Critical Tianjin Polytechnic University
Priority to CN202110439094.2A priority Critical patent/CN113257691B/zh
Publication of CN113257691A publication Critical patent/CN113257691A/zh
Application granted granted Critical
Publication of CN113257691B publication Critical patent/CN113257691B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/43Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Abstract

一种降低热应力的功率模块引线互连方法,属于功率模块封装领域。随着功率模块技术的不断发展,包括碳化硅在内的新一代半导体芯片的损耗发热严重,明显降低封装使用寿命。其中,当芯片表面温度很高时,芯片与金属键合丝进行连接的位置热应力显著,连接点极易失效。本发明开发了一种提高功率模块铝丝键合寿命的方法;主要的特征是引入Cu‑Al复合金属垫片,芯片两端通过纳米银焊膏烧结分别与基板和复合金属垫片互连,增加热量导出的路径,降低芯片与键合处的温度;铝丝与铝片键合互连,避免了芯片与铝线热膨胀系数失配;最终显著降低铝丝键合处的热应力,提高可靠性和寿命。这种结构适用于各种采用铝线键合互连工艺的功率模块的生产。

Description

一种降低热应力的功率模块引线互连方法
技术领域
本发明涉及一种降低热应力的功率模块引线互连方法,属于功率模块封装结构和工艺以及电子封装领域。
背景技术
功率模块是将功率电力电子元器件通过电气互连形成具有一定功能的集成电路然后再灌封而成的模块。其结构如图1所示,主要包括:基板、芯片、互连材料以及底板;基板101 与芯片103通过连接层102连接,连接层的材料可以是焊锡或者纳米银焊膏;芯片103与基板101通过铝线104连接,铝线两端的连接通过引线键合技术实现。功率模块自诞生以来就在电力电子以及交通运输等领域获得了广泛的应用。功率模块工作时,其功能的主要依靠半导体芯片实现,在半导体芯片运行既定功能的同时,必不可少的会产生大量的热损耗,这些热量使得芯片以及芯片周围的材料处于较高温度状态。同时,由于不同材料的热膨胀系数不同,在较高的温度状态将会使不同器件之间互连界面产生热应力。随着功率模块工作时不断开启和关闭,功率模块会受到长期循环性的热应力的作用,不断产生并积累损伤,最终导致失效。根据热应力产生机理以及功率模块损伤机制,可以清楚的了解到,功率模块中芯片温度越高,温度波动范围越大,功率模块内部结构的损伤积累就越快,功率模块的使用寿命就越短。近年来,功率半导体技术不断发展,功率模块的集成度不断上升,其功率密度也不断上升,尤其是在包括碳化硅(SiC)在内的新一代半导体材料的不断应用的当下,由于SiC的禁带宽度比Si材料更宽,其可以承受的电压更大,为充分利用SiC材料的性能,SiC功率模块设计时,功率密度明显增加,这意味着SiC器件工作温度更高,采用当前的封装工艺,其寿命将严重降低。
功率模块的失效主要表现为芯片节温过高失效以及互连界面失效。目前,大部分功率模块中芯片的热量往往只能向下传递到基板然后再传递到底板进行散热,其散热效率有限。并且,功率器件之间的电气互连大多采用的是引线键合互连技术,即通过导电金属丝线互连。其中,最常用的导电金属丝线就是铝线。引线与芯片通过键合技术,以面积很小的键合点相连接。由此可见,键合点处往往是热应力集中的位置,尤其是在SiC等第三代宽紧带半导体器件应用后,其承受的热应力将更大。这意味着键合点处是功率模块内比较危险的位置,其使用寿命往往是制约功率模块寿命的关键所在。因此,要提高功率模块的可靠性,延长功率模块的使用寿命,就必须解决芯片温度过高以及键合点处的热应力大的问题。
发明内容
本发明研究开发了一种降低热应力的功率模块引线互连方法,具体过程如图2所示:铜铝复合金属块206可以通过电阻焊或其他方式实现复合;DBC基板101与芯片103通过纳米银焊膏烧结层102连接;芯片103与复合金属块206中的铜块206-1通过纳米银焊膏烧结层 205实现互连;铝线104一端与复合金属块206中的铝块206-2连接,另一端与DBC基板101连接,连接均采用超声波-压力键合技术。
对比可见,本方法最主要的特征是引入Cu-Al复合金属块,使得芯片两端通过纳米银焊膏烧结分别与DBC基板和复合金属块互连,可以有效的将芯片产热导出,降低芯片的温度。同时,铝线与铝块键合互连,避免了铝线与芯片热膨胀系数不匹配的问题,并且复合金属块的存在,对热量有缓冲作用,可以降低键合点处的温度。这两点特征共同作用,可以明显降低键合点处的热应力,提高功率模块的可靠性,延长功率模块的使用寿命。
本发明的技术方案如下:
一种降低热应力的功率模块引线互连方法;在芯片与引线之间增加Cu-Al复合金属块作为缓冲层;芯片两侧分别与DBC基板以及复合金属块中的铜块相连接;复合金属块中的铝块通过铝线与DBC基板相连接。
所述芯片与DBC基板以及芯片与复合金属块的连接,均通过一种纳米银焊膏的低温烧结实现连接,升温速率为4-6℃/min,烧结温度为270℃-290℃,保温时间为30-35min。
所述Cu-Al复合金属块,采用电阻焊或其他方法将Cu块和Al块进行复合连接;Cu块一侧与芯片上表面进行连接;Al块一侧与Al线进行引线键合,形成键合点。
所述Al线,一端与Cu-Al复合金属块的Al块表面相连接,另一端与基板表面连接。此 2处连接均通过压力-超声键合技术实现,键合压力为30-60gf,超声功率为1.3-1.8W。
本发明中,芯片与DBC基板的连接以及Cu-Al复合金属块中的Cu块与芯片上表面的连接,都是通过纳米银焊膏的烧结实现,增加了芯片散热的路径,并且可以获得较高的热量传输速度,能够有效降低芯片工作时的温度;引入Cu-Al复合金属块,使得芯片向上传递更多的热量,降低芯片工作温度的同时,复合金属块的温度也比现有结构中芯片的温度要低,从而降低连接点工作温度;并且将连接点从芯片-Al线连接改为Al-Al连接,以避免热膨胀系数不匹配程度。综合上述特征与优势,本方法可以有效降低芯片温度,减轻连接点处的热应力,有利于延长连接点的工作寿命,提高功率模块的使用寿命。本发明涉及的方法,包括基板、 IGBT芯片、Cu-Al复合金属块以及Al线四个部分。芯片与DBC基板的连接以及Cu-Al复合金属块中的Cu块与芯片上表面的连接,都是通过纳米银焊膏的烧结实现;纳米银烧结连接以及复合金属块的存在,可以降低芯片以及连接点的工作温度;同时,Al块与Al线连接,属于同种金属连接,没有热膨胀系数不匹配问题,从而可以降低连接点处的热应力,提高连接点的使用寿命,进而提高功率模块的可靠性,延长其使用寿命。本发明中的方法适用于各种采用铝线键合互连工艺的Si基或者SiC等材料的功率模块的生产。
附图说明
为便于理解,对比现有引线键合结构和本发明所采用的引线键合结构,其中:
图1为现有的引线键合结构的示意图;图2为本发明的实施例中的引线键合结构的示意图。
说明书附图标记如下:
图1中的标注包括:101、DBC基板;102、基板与芯片的焊膏连接层;103、芯片;104、铝线;
图2中的标注包括:101、DBC基板;102、基板与芯片的焊膏连接层;103、芯片;104、铝线;205、芯片与Cu-Al复合金属块的焊膏连接层;206-1、Cu块;206-2、Al块。
具体实施方式
(1)将DBC基板经过清洗后通过钢网印刷焊膏,并将芯片贴至焊膏上。
(2)将基板和芯片在空气中以5℃·min-1的加热速率加热到100℃,将气氛转换为4%H2+96%N2气氛,之后继续以5℃·min-1的速率加热至250℃,保温10min,期间进行气氛转换,过程为4%H2+96%N2气氛-空气-4%H2+96%N2气氛,其中空气氛围保持时间为60s-80s,然后继续加热至280℃,保温30min后随炉冷却至室温,实现芯片与基板的连接。
(3)将准备好的铜块和铝块通过电阻焊进行焊接,焊接参数包括:焊接电流为20kA;焊接时间为800ms;焊接压力为0.1MPa。
(4)将焊接后的Cu-Al复合金属块,通过与(2)中相同的工艺与芯片表面进行连接。
(5)通过超声波-压力键合工艺将铝线两端分别连接在Al块表面和基板表面,键合压力为35 gf,超声功率为1.5W。

Claims (1)

1.一种降低热应力的功率模块引线互连方法,其特征在于:在芯片与引线之间增加Cu-Al复合金属块作为缓冲层,使芯片向Cu-Al复合金属块传递热量,降低芯片工作温度,同时利用Cu-Al复合金属块温度比芯片温度低的特点,降低键合点温度;
所述Cu-Al复合金属块的Al层与铝线相连,避免热膨胀系数不匹配,Cu-Al复合金属块中的Cu层通过纳米银焊膏烧结连接技术与芯片相连;
芯片两侧分别与DBC基板以及复合金属块中的铜块通过纳米银焊膏烧结相连接;
烧结工艺为:在空气中以5℃·min-1的加热速率加热到100℃,将气氛转换为4%H2+96%N2气氛,之后继续以5℃·min-1的速率加热至250℃,保温10min,期间进行气氛转换,过程为4%H2+96%N2气氛-空气-4%H2+96%N2气氛,其中空气氛围保持时间为60s-80s,然后继续加热至280℃,保温30min后随炉冷却至室温;
所述Al线,一端与Cu-Al复合金属块的Al一侧相连,另一端与DBC基板连接。
CN202110439094.2A 2021-04-23 2021-04-23 一种降低热应力的功率模块引线互连方法 Active CN113257691B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110439094.2A CN113257691B (zh) 2021-04-23 2021-04-23 一种降低热应力的功率模块引线互连方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110439094.2A CN113257691B (zh) 2021-04-23 2021-04-23 一种降低热应力的功率模块引线互连方法

Publications (2)

Publication Number Publication Date
CN113257691A CN113257691A (zh) 2021-08-13
CN113257691B true CN113257691B (zh) 2024-01-02

Family

ID=77221506

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110439094.2A Active CN113257691B (zh) 2021-04-23 2021-04-23 一种降低热应力的功率模块引线互连方法

Country Status (1)

Country Link
CN (1) CN113257691B (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103295918A (zh) * 2013-05-30 2013-09-11 江西联创特种微电子有限公司 一种大功率场效应晶体管铝-金键合过渡片的制备方法
CN203367260U (zh) * 2013-06-27 2013-12-25 北京新雷能科技股份有限公司 一种功率陶瓷外壳和功率芯片封装结构
CN110718470A (zh) * 2019-09-03 2020-01-21 浙江固驰电子有限公司 一种高可靠性低结构应力的铝基板铝线键合工艺
CN112151400A (zh) * 2020-09-23 2020-12-29 锦州七七七微电子有限责任公司 一种解决smd管壳键合点金铝系统的方法
CN112201628A (zh) * 2020-08-24 2021-01-08 株洲中车时代半导体有限公司 一种功率模块封装结构及其制备方法
CN112599504A (zh) * 2020-12-15 2021-04-02 华芯威半导体科技(北京)有限责任公司 一种大功率模块粗铜线键合结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103295918A (zh) * 2013-05-30 2013-09-11 江西联创特种微电子有限公司 一种大功率场效应晶体管铝-金键合过渡片的制备方法
CN203367260U (zh) * 2013-06-27 2013-12-25 北京新雷能科技股份有限公司 一种功率陶瓷外壳和功率芯片封装结构
CN110718470A (zh) * 2019-09-03 2020-01-21 浙江固驰电子有限公司 一种高可靠性低结构应力的铝基板铝线键合工艺
CN112201628A (zh) * 2020-08-24 2021-01-08 株洲中车时代半导体有限公司 一种功率模块封装结构及其制备方法
CN112151400A (zh) * 2020-09-23 2020-12-29 锦州七七七微电子有限责任公司 一种解决smd管壳键合点金铝系统的方法
CN112599504A (zh) * 2020-12-15 2021-04-02 华芯威半导体科技(北京)有限责任公司 一种大功率模块粗铜线键合结构

Also Published As

Publication number Publication date
CN113257691A (zh) 2021-08-13

Similar Documents

Publication Publication Date Title
US11139278B2 (en) Low parasitic inductance power module and double-faced heat-dissipation low parasitic inductance power module
US10559538B2 (en) Power module
US6611056B2 (en) Composite material, and manufacturing method and uses of same
US10510640B2 (en) Semiconductor device and method for manufacturing semiconductor device
EP2018667A2 (en) Power semiconductor module
WO2019071743A1 (zh) 采用低温烧结纳米银的双面互连硅基igbt模块的方法
CN102593081A (zh) 包括散热器的半导体器件
JP2017034152A (ja) 電力用半導体装置
CN113257691B (zh) 一种降低热应力的功率模块引线互连方法
CN112864140A (zh) 一种新型耐高温SiC MOSFET半桥多层封装结构
CN113838821A (zh) 一种用于SiC平面封装结构的散热件及其制备方法
Grummel et al. Design consideration of high temperature SiC power modules
CN110571204A (zh) 具有双面散热能力的双向开关功率器件及制作方法
WO2022213013A1 (en) Double-side cooled power modules with sintered-silver interposers
CN207602834U (zh) 一种大功率ipm模块端子连接结构
CN218996706U (zh) 一种铜带键合的环氧塑封车用功率模块封装结构
JP3736251B2 (ja) 複合材料とその製造方法
CN219917162U (zh) 功率模块
Li et al. Research on Thermal-Mechanical Properties of GaN Power Module Based on QFN Package by Using Nano Copper/Silver Sinter Paste
Shen et al. High temperature high power module design for wide bandgap semiconductors: Packaging architecture and materials considerations
JP4277582B2 (ja) 半導体装置
CN116072640A (zh) 一种低电感功率模块及其制作方法
CN117690887A (zh) 一种双面散热的氧化镓芯片倒装封装结构及其制备方法
CN117558704A (zh) 一种半导体功率模块
CN117199045A (zh) 用于功率半导体封装的衬底以及包含该衬底的封装

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant