CN113255263B - Particle band dividing method, device, computer equipment and storage medium - Google Patents

Particle band dividing method, device, computer equipment and storage medium Download PDF

Info

Publication number
CN113255263B
CN113255263B CN202110628383.7A CN202110628383A CN113255263B CN 113255263 B CN113255263 B CN 113255263B CN 202110628383 A CN202110628383 A CN 202110628383A CN 113255263 B CN113255263 B CN 113255263B
Authority
CN
China
Prior art keywords
node
nodes
segmentation
particle band
resource
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110628383.7A
Other languages
Chinese (zh)
Other versions
CN113255263A (en
Inventor
邵中尉
张吉锋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Sierxin Technology Co.,Ltd.
Original Assignee
Shanghai Guowei Silcore Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Guowei Silcore Technology Co Ltd filed Critical Shanghai Guowei Silcore Technology Co Ltd
Priority to CN202110628383.7A priority Critical patent/CN113255263B/en
Publication of CN113255263A publication Critical patent/CN113255263A/en
Application granted granted Critical
Publication of CN113255263B publication Critical patent/CN113255263B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking
    • G06F30/3308Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/327Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

The invention provides a particle band segmentation method, a particle band segmentation device, computer equipment and a storage medium, which belong to the field of integrated circuit chip design, and specifically comprise the steps of analyzing a design file carrying preset nodes, extracting a connection relation and generating a syntax tree diagram corresponding to the circuit nodes; obtaining the current resource value and the level information of each circuit node in the grammar tree graph through a resource evaluation module; acquiring a resource theoretical upper limit value list of each circuit node from a threshold calculation module; marking all nodes with current resource values larger than the theoretical upper limit value of the resources, and determining an initial particle band according to the marked nodes; and adjusting and optimizing the initial particle band according to the preset node to obtain a segmentation particle band. Through the processing scheme of the application, effective segmentation is rapidly realized, the search segmentation time is short, and the distribution efficiency is improved.

Description

Particle band dividing method, device, computer equipment and storage medium
Technical Field
The invention relates to the field of integrated circuit chip design, in particular to a particle band segmentation method and device for limiting resource distribution, computer equipment and a storage medium.
Background
Before the chip is put into a factory to be manufactured formally, the correctness and the performance index of a net-shaped data structure or a net list logic in a chip design file must be verified. In chip design, programmable logic arrays are often used for design logic verification. A single logic array has limited computational capacity and often requires multiple logic arrays to work together to verify the design logic in the entire design document. Therefore, a design file or a netlist written by an RTL (real time language) language needs to be divided into a plurality of parts according to a certain strategy and distributed to corresponding logic arrays, each part is connected through interconnection signals and respectively operated on different FPGAs, and the logic functions of user design before and after division need to be kept consistent.
During segmentation, the design file can be abstracted into a syntax tree graph with resource weights, and then the syntax tree graph is segmented into particles carrying a plurality of nodes, wherein each particle is allocated to one FPGA. After the segmentation is completed, the particles in the graph can be restored to be in an RTL language or netlist format, original code content and a hierarchical structure are kept, the particles are placed in the corresponding FPGA, meanwhile, port signals in a TOP layer module in the FPGA are added, correct interconnection communication connection among the FPGAs is guaranteed, and finally, the TOP layer in each FPGA is combined into a TOP module to complete the whole process.
However, the traditional method does not consider the distribution conditions of resources and levels of the design module for selecting the segmentation particle band, in actual engineering, the obtained segmentation particle resources often exceed the resources of even one whole FPGA, so that the segmentation result is invalid, a user needs to repeatedly test and adjust the segmentation particle band to finally obtain an effective segmentation result, and a large amount of time is wasted; meanwhile, even if an effective segmentation result meeting the upper limit of FPGA resources can be obtained, for a segmentation algorithm, the segmentation particles are often difficult to achieve the optimal segmentation effect of minimum interconnection due to overlarge weight, and the segmentation effect is not ideal, so that the FPGA operation efficiency is not high. Moreover, the design scale of the current user is often huge, the difficulty of knowing the resource distribution condition of the segmentation particles and selecting the segmentation particles through a manual or semi-automatic tool is very large, time and labor are wasted, and errors are easy to occur; under the condition of simultaneously considering resource limitation of the segmentation particle band and meeting the requirement of a node of a segmentation position specified by a user, the final segmentation particle band is not easy to obtain quickly.
Disclosure of Invention
Accordingly, to overcome the above-mentioned disadvantages of the prior art, the present invention provides a particle band segmentation method, apparatus, computer device and storage medium defining a resource distribution.
In order to achieve the above object, the present invention provides a particle band dividing method for defining resource distribution, comprising: analyzing a design file carrying preset nodes, wherein the design file is used for describing the structure of each circuit node of a circuit system and the connection relation among the circuit nodes, and extracting the connection relation to generate a syntax tree diagram corresponding to the circuit nodes; obtaining the current resource value and the level information of each circuit node in the grammar tree graph through a resource evaluation module; acquiring a resource theoretical upper limit value list of each circuit node from a threshold calculation module; marking all nodes with current resource values larger than the theoretical upper limit value of the resource, and determining an initial particle band according to the marked nodes, wherein the segmentation particles in the initial particle band comprise a plurality of circuit nodes in a syntax tree with resource weight; and adjusting and optimizing the initial particle band according to the preset node to obtain a segmentation particle band.
In one embodiment, the adjusting and optimizing the initial particle band according to the preset node to obtain a segmented particle band includes: judging whether the preset node is positioned below the initial particle band in the syntax tree diagram; when the judgment result is yes, deleting all father nodes corresponding to the preset nodes from the initial particle band according to the syntax tree graph; and determining an optimized particle band by adopting a minimum envelope method formed by the preset nodes to the upper layer of the grammar tree graph, and combining the optimized particle band with the initial particle bands of all the father nodes corresponding to the preset nodes, so as to obtain a segmentation particle band.
In one embodiment, the adjusting and optimizing the initial particle band according to the preset node to obtain a segmented particle band includes: judging whether the preset node is positioned below the initial particle band in the syntax tree diagram; when the judgment result is negative, judging whether the preset node is positioned above the initial particle band in the syntax tree diagram; and generating error reporting information according to the judgment result of the preset node above the initial particle band.
In one embodiment, the determining the initial particle band according to the marking nodes includes: acquiring a segmentation empty set; adding all leaf nodes at the tail end of the syntax tree diagram into a segmentation empty set to obtain a segmentation to-be-checked set; when the leaf nodes are judged not to exist the mark nodes, judging whether father nodes of each leaf node in the segmentation to-be-verified set are the mark nodes or not; when the father node is judged to be the mark node, the leaf node is reserved in the segmentation to-be-checked set; when the father node is judged not to be the mark node, adding the father node into the segmentation to-be-verified set, and deleting all child nodes of the father node from the segmentation to-be-verified set; and setting each node in the segmentation to-be-checked set and nodes in a syntax tree below the node as segmentation particles according to the syntax tree graph until the father node of each node in the segmentation to-be-checked set is a mark node or a top node, and constructing an initial particle band.
The invention also provides a particle band segmentation apparatus for defining a resource distribution, the apparatus comprising: the file analysis module is used for analyzing a design file carrying preset nodes, wherein the design file is used for describing the structure of each circuit node of the circuit system and the connection relation among the circuit nodes, and extracting the connection relation to generate a syntax tree diagram corresponding to the circuit nodes; the resource value acquisition module is used for acquiring the current resource value and the level information of each circuit node in the syntax tree diagram through the resource evaluation module; a theoretical threshold value obtaining module, configured to obtain a resource theoretical upper limit value list of each circuit node from the threshold value calculating module; the marking module is used for marking all nodes with current resource values larger than the theoretical upper limit value of the resource, and determining an initial particle band according to the marked nodes, wherein the segmentation particles in the initial particle band comprise a plurality of circuit nodes in a syntax tree with resource weight; and the particle band segmentation module is used for adjusting and optimizing the initial particle band according to the preset node to obtain a segmented particle band.
The invention also provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method when executing the computer program.
The invention also provides a computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method as described above.
Compared with the prior art, the invention has the advantages that: the particle band is determined by the distribution condition of the module resources along with the hierarchy, so that particles with proper resource size can be obtained, the overall segmentation efficiency is improved, the rapid and effective segmentation is realized, the search segmentation time is short, and the distribution efficiency is improved; and the whole scheme only relates to local modification of the syntax tree graph, does not need to carry out resource recalculation on the whole tree, only needs to update the resources of partial nodes from bottom to top, and simultaneously ensures the minimization of the number of the nodes in the segmentation particle band and the execution efficiency of the segmentation algorithm.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a diagram illustrating an application scenario of a particle band segmentation method according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a particle band segmentation method according to an embodiment of the present invention;
FIG. 3 is a diagram of a syntax tree diagram in an embodiment of the present invention;
FIG. 4 is a labeled diagram of a syntax tree diagram in an embodiment of the present invention;
FIG. 5 is a schematic diagram of an initial grain band of a syntax tree diagram in an embodiment of the present invention;
FIG. 6 is a schematic diagram of a segmented granular band of a syntax tree diagram in an embodiment of the present invention;
FIG. 7 is a block diagram of an object allocation apparatus according to an embodiment of the present invention;
fig. 8 is an internal structural diagram of a computer device in an embodiment of the present invention.
Detailed Description
The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number and aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
The object allocation method provided by the application can be applied to the application environment shown in fig. 1. It should be noted that, the method in the embodiment of the present disclosure may be executed by a terminal and/or a server, and several steps in the method may also be executed by the terminal and/or the server, which is not limited herein. Wherein the terminal 102 communicates with the server 104 via a network. The terminal 102 may send the design file to the server 104; the server 104 analyzes a design file carrying preset nodes, wherein the design file is used for describing the structure of each circuit node of the circuit system and the connection relation among the circuit nodes, and extracts the connection relation to generate a syntax tree diagram corresponding to the circuit nodes; the server 104 obtains the current resource value and the level information of each circuit node in the syntax tree diagram through the resource evaluation module; the server 104 acquires a resource theoretical upper limit value list of each circuit node from the threshold calculation module; the server 104 marks all nodes of which the current resource values are larger than the theoretical upper limit value of the resources, and determines an initial particle band according to the marked nodes, wherein the segmentation particles in the initial particle band comprise a plurality of circuit nodes in a syntax tree with resource weight; the server 104 adjusts and optimizes the initial particle band according to the preset node to obtain a segmentation particle band. The terminal 102 may be, but not limited to, various personal computers, notebook computers, smart phones, tablet computers, and portable smart devices, and the server 104 may be implemented by an independent server or a server cluster formed by a plurality of servers.
As shown in fig. 2, an embodiment of the present application is based on a server, and provides a method for segmenting a particle band defining resource distribution, including the following steps:
step 201, analyzing a design file carrying preset nodes, where the design file is used to describe structures of circuit nodes of a circuit system and connection relations among the circuit nodes, and extracting the connection relations to generate a syntax tree diagram corresponding to the circuit nodes.
The design file is used for describing the structure of each circuit node of the circuit system and the connection relation between the circuit nodes. The design file comprises a plurality of logic program blocks (modules), nesting or parallel relation exists among the logic program blocks, and each logic program block corresponds to each circuit node of the circuit system. A circuit node may be one or more electronic components. The design file can be a format file such as Verilog, vhdl, systemVerilog and the like; the netlist is a mesh data structure formed by RTL after RTL logic synthesis, the design logic of a user is also described, and the RTL or netlist design forms a syntax tree diagram in a memory through a syntax parser. The preset node refers to a node which cannot be divided in the design file, in the syntax tree diagram, the node and all nodes below the node are taken as a whole to form a particle, and the FPGA directly operates an example represented by the part as a black box. And the server analyzes the design file carrying the preset nodes and extracts the connection relation to generate a syntax tree diagram corresponding to the circuit nodes.
Step 202, obtaining the current resource value and level information of each circuit node in the syntax tree diagram through the resource evaluation module.
The resources refer to the general names of various resources of the FPGA, such as PIO resources, LUT resources, BUF resources, and the like, which will be consumed by the segmentation particles. As shown in fig. 3, the syntax tree itself has hierarchical information, that is, the resource hierarchical distribution of each node is obtained. The hierarchy of the syntax tree diagram represents the call relationship between modules, the top level nodes of the syntax tree diagram are top designs (i.e., main functions) in RTL, the stem nodes of the syntax tree diagram represent modules instantiated in the middle, and the leaf nodes of the syntax tree diagram represent terminal modules or black boxes (black boxes) that no longer contain other modules. The resource evaluation module is a module for evaluating resource consumption of nodes of the syntax tree, and the principle of the resource evaluation module is that logical synthesis is carried out on the nodes of the syntax tree, FPGA hardware resources consumed by the nodes are counted and used as an evaluation result, and the resource types comprise PIO resources, LUT resources, BUF resources and the like. And the server obtains the current resource value and the level information of each circuit node in the syntax tree diagram through the resource evaluation module.
Step 203, a resource theoretical upper limit value list of each circuit node from the threshold calculation module is obtained.
The threshold calculation module is a module for scientifically defining the size of the segmentation particles, namely the amount of resources consumed by the particles, and the proper particle size is beneficial to obtaining a reasonable and efficient segmentation result and fast convergence of a segmentation algorithm. The input of the threshold value calculation module is the number of the used FPGAs, the type and the total amount of single FPGA resources, performance requirement parameters of a graph partitioning algorithm to be called and the resource distribution condition of user design logic; the output is the values of the non-leaf node resource upper limit list R _ stem and the leaf node resource upper limit list R _ leaf. The values of the R _ stem and R _ leaf lists may also come from direct parameter input by the terminal 102. And the server acquires a resource theoretical upper limit value list of each circuit node from the threshold calculation module.
And 204, marking all nodes of which the current resource values are larger than the theoretical upper limit value of the resources, and determining an initial particle band according to the marked nodes, wherein the segmentation particles in the initial particle band comprise a plurality of circuit nodes in a syntax tree with resource weight.
And the server marks all nodes with current resource values larger than the theoretical upper limit value of the resource, and determines an initial particle band according to the marked nodes, wherein the segmentation particles in the initial particle band comprise a plurality of circuit nodes in a syntax tree with resource weight. As shown in fig. 4, the server may perform a coloring operation on each node of the syntax tree. The server may dye red for non-leaf nodes whose resources exceed the value of R _ stem and green for non-leaf nodes less than or equal to the value of R _ stem; and coloring red for those leaf nodes whose resources exceed the R _ leaf value and green for those leaf nodes whose resources are less than or equal to the R _ leaf value. The server determines an initial particle band, which is a particular segmented particle band of all possible segmented particle bands, which is the one closest to the upper layer under the resource constraints computed by the resource assessment module and the threshold computation module. The initial grain band, which is the highest and only one of the divided grain bands in the syntax tree diagram, is shown in fig. 5 below.
And step 205, adjusting and optimizing the initial particle band according to a preset node to obtain a segmentation particle band.
And the server adjusts and optimizes the initial particle band according to the preset node to obtain a segmentation particle band.
According to the particle band segmentation method for limiting resource distribution, the particle band is determined and segmented according to the distribution condition of the resources of the module along with the hierarchy, so that particles with proper resource size can be obtained, the overall segmentation efficiency is improved, quick and effective segmentation is realized, the search segmentation time is short, and the distribution efficiency is improved; and the whole scheme only relates to local modification of the syntax tree graph, does not need to carry out resource recalculation on the whole tree, only needs to update the resources of partial nodes from bottom to top, and simultaneously ensures the minimization of the number of the nodes in the segmentation particle band and the execution efficiency of the segmentation algorithm.
In one embodiment, the adjusting and optimizing the initial particle band according to the preset node to obtain the segmented particle band includes: judging whether a preset node is positioned below the initial particle band in the syntax tree diagram; if so, deleting all father nodes corresponding to the preset nodes from the initial particle band according to the syntax tree graph; and determining an optimized particle band by adopting a minimum envelope method formed by the preset nodes to the upper layer of the grammar tree graph, and combining the optimized particle band with the initial particle bands of all the father nodes corresponding to the preset nodes, so as to obtain a segmentation particle band.
The server judges whether the preset node is positioned below the initial particle band in the grammar tree diagram. The meaning of the predetermined node (fix node) is that a user hopes that the node participates in the division in an integral mode, and the node is fixedly stored on a certain FPGA after the division.
When the determination is yes, the initial grain band corresponding to the resource restriction band is necessarily required to be shifted down to include the fix node. And the server deletes all father nodes corresponding to the preset nodes from the initial particle band according to the syntax tree graph. A parent node corresponding to the preset node or a parent node of the parent node may exist in the initial granular zone, and the server may delete the associated node of the fix node in the resource definition zone from the node set of the initial granular zone.
The server determines an optimized particle band by adopting a minimum envelope method formed by the preset nodes to the upper layer of the grammar tree graph, and combines the optimized particle band with the initial particle bands of all the father nodes corresponding to the preset nodes, so as to obtain the segmentation particle band shown in fig. 6. The server can independently extract the ancestor node and the descendant node from the whole syntax tree to form a subtree, determine an optimized particle band by a method of forming a minimum envelope from a fix point to the upper layer of the syntax tree, and merge the optimized particle band with the initial particle bands of all the father nodes corresponding to the deleted preset nodes to obtain the segmented particle bands.
In the above syntax tree diagram, all directly related nodes of the fix node, such as father nodes, grandfather nodes, etc., need to be marked as cut particle band forbidden points; then, a divided particle band which contains a fix node and cannot contain a divided particle band forbidden point and is positioned at the top is found. The position is the most upper position so as to ensure the minimum number of nodes in the segmentation particle band and further ensure the execution efficiency of the segmentation algorithm.
In one embodiment, the adjusting and optimizing the initial particle band according to the preset node to obtain the segmented particle band includes: judging whether a preset node is positioned below the initial particle band in the syntax tree diagram; if not, judging whether the preset node is positioned above the initial particle band in the syntax tree diagram; and generating error reporting information according to the judgment result of the preset node above the initial particle band.
The server judges whether the preset node is positioned below the initial particle band in the grammar tree diagram. And when the judgment result is no, the server judges whether the preset node is positioned above the initial particle band in the syntax tree diagram. And the server generates error reporting information according to the judgment result of the preset node above the initial particle band. When the fix node is in the initial particle band, the requirement of the user for specifying the position can be met without any operation; when the fix node is above the initial particle band, the resource of the fix node must exceed the upper limit of the predetermined value, the fix node is illegal, and the server generates error report information according to the judgment result of the predetermined node above the initial particle band.
In one embodiment, determining the initial particle band from the marker nodes comprises: acquiring a segmentation empty set; adding all leaf nodes at the tail end of the syntax tree diagram into a segmentation empty set to obtain a segmentation to-be-checked set; when judging that no mark node exists in the leaf nodes, judging whether a father node for segmenting each leaf node in the set to be verified is a mark node; when the father node is judged to be the mark node, the leaf node is reserved in the segmentation to-be-verified set; when the father node is judged not to be the mark node, adding the father node into the segmentation to-be-verified set, and deleting all child nodes of the father node from the segmentation to-be-verified set; and setting each node in the segmentation to-be-checked set and the node in the syntax tree below the node in the segmentation to-be-checked set as segmentation particles according to the syntax tree graph until the father node of each node in the segmentation to-be-checked set is a marked node or a top node, and constructing an initial particle band.
The server obtains the segmentation empty set. And the server adds all leaf nodes at the tail end in the syntax tree graph into the segmentation empty set to obtain a segmentation to-be-checked set. And when the leaf nodes are judged not to exist the marked nodes, the server judges whether the father node dividing each leaf node in the set to be checked is the marked node. And when the father node is judged to be the mark node, the server keeps the leaf node in the split to-be-verified set. When the father node is judged not to be the mark node, the server adds the father node into the segmentation to-be-verified set, and simultaneously deletes all child nodes of the father node from the segmentation to-be-verified set; until the father node of each node in the segmentation to-be-verified set is a marked node or a top node, setting each node in the segmentation to-be-verified set and the node in the syntax tree below the node as segmentation particles according to the syntax tree diagram, and constructing an initial particle band as shown in fig. 5.
In one embodiment, as shown in fig. 7, there is provided an object assigning apparatus including: a file parsing module 701, a resource value obtaining module 702, a theoretical threshold obtaining module 703, a marking module 704 and a particle band dividing module 705, wherein:
the file parsing module 701 is configured to parse a design file carrying preset nodes, where the design file is used to describe structures of circuit nodes of the circuit system and connection relationships between the circuit nodes, and extract the connection relationships to generate a syntax tree diagram corresponding to the circuit nodes.
A resource value obtaining module 702, configured to obtain, through the resource evaluating module, a current resource value and hierarchy information of each circuit node in the syntax tree diagram.
A theoretical threshold obtaining module 703, configured to obtain a resource theoretical upper limit list of each circuit node from the threshold calculating module.
And a marking module 704, configured to mark all nodes whose current resource values are greater than the resource theoretical upper limit value, and determine an initial grain band according to the marked nodes, where a segmented grain in the initial grain band includes a plurality of circuit nodes in a syntax tree with resource weights.
And a particle band dividing module 705, configured to adjust and optimize the initial particle band according to a preset node, so as to obtain a divided particle band.
In one embodiment, the particle band segmentation module 705 comprises:
and the judging unit is used for judging whether the preset node is positioned below the initial particle band in the syntax tree diagram.
And the node deleting unit is used for deleting all father nodes corresponding to the preset nodes from the initial particle band according to the syntax tree graph when the judgment result is yes.
And the optimization unit is used for determining an optimized particle band by adopting a minimum envelope method formed by the preset nodes to the upper layer of the grammar tree graph, and combining the optimized particle band with the initial particle bands of all the father nodes corresponding to the preset nodes to obtain the segmentation particle band.
In one embodiment, the particle band segmentation module 705 comprises:
the judging unit is used for judging whether the preset node is positioned below the initial particle band in the syntax tree diagram; and when the judgment result is no, judging whether the preset node is positioned above the initial particle band in the syntax tree diagram.
And the error reporting unit is used for generating error reporting information according to the judgment result of the preset node above the initial particle band.
In one embodiment, the tagging module 704 includes:
and the empty set generating unit is used for acquiring the segmentation empty sets.
And the segmentation to-be-verified set generation unit is used for adding all leaf nodes at the tail end in the grammar tree graph into the segmentation empty set to obtain the segmentation to-be-verified set.
And the marked node judging unit is used for judging whether a father node for dividing each leaf node in the set to be verified is a marked node or not when judging that the marked node does not exist in the leaf nodes.
A father node judging unit, which is used for dividing the set to be verified and reserving the leaf node when judging that the father node is the mark node; and when the father node is judged not to be the mark node, adding the father node into the segmentation to-be-verified set, and deleting all child nodes of the father node from the segmentation to-be-verified set.
And the particle band generating unit is used for setting each node in the segmentation to-be-checked set and the node in the syntax tree below the node as the segmentation particles according to the syntax tree graph until the father node of each node in the segmentation to-be-checked set is the mark node or the top node, and constructing the initial particle band.
For the specific definition of the object allocation device, reference may be made to the above definition of the object allocation method, which is not described herein again. The various modules in the object distribution apparatus described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as shown in fig. 8. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is for storing object allocation data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement an object allocation method.
Those skilled in the art will appreciate that the architecture shown in fig. 8 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, there is provided a computer device comprising a memory storing a computer program and a processor implementing the following steps when the processor executes the computer program: analyzing a design file carrying preset nodes, wherein the design file is used for describing the structure of each circuit node of the circuit system and the connection relation among the circuit nodes, and extracting the connection relation to generate a syntax tree diagram corresponding to the circuit nodes; obtaining the current resource value and level information of each circuit node in the syntax tree diagram through a resource evaluation module; acquiring a resource theoretical upper limit value list of each circuit node from a threshold calculation module; marking all nodes with current resource values larger than the theoretical upper limit value of the resource, and determining an initial particle band according to the marked nodes, wherein the segmentation particles in the initial particle band comprise a plurality of circuit nodes in a syntax tree with resource weight; and adjusting and optimizing the initial particle band according to a preset node to obtain a segmentation particle band.
In one embodiment, the adjusting and optimizing the initial particle band according to the preset node when the processor executes the computer program to obtain the segmented particle band includes: judging whether a preset node is positioned below the initial particle band in the syntax tree diagram; if so, deleting all father nodes corresponding to the preset nodes from the initial particle band according to the syntax tree graph; and determining an optimized particle band by adopting a minimum envelope method formed by the preset nodes to the upper layer of the grammar tree graph, and combining the optimized particle band with the initial particle bands of all the father nodes corresponding to the preset nodes, so as to obtain a segmentation particle band.
In one embodiment, the adjusting and optimizing the initial particle band according to the preset node when the processor executes the computer program to obtain the segmented particle band includes: judging whether a preset node is positioned below the initial particle band in the syntax tree diagram; if not, judging whether the preset node is positioned above the initial particle band in the syntax tree diagram; and generating error reporting information according to the judgment result of the preset node above the initial particle band.
In one embodiment, the determining an initial grain band from the marker nodes implemented when the processor executes the computer program comprises: acquiring a segmentation empty set; adding all leaf nodes at the tail end of the syntax tree diagram into a segmentation empty set to obtain a segmentation to-be-checked set; when judging that no mark node exists in the leaf nodes, judging whether a father node for segmenting each leaf node in the set to be verified is a mark node; when the father node is judged to be the mark node, the leaf node is reserved in the segmentation to-be-verified set; when the father node is judged not to be the mark node, adding the father node into the segmentation to-be-verified set, and deleting all child nodes of the father node from the segmentation to-be-verified set; and setting each node in the segmentation to-be-checked set and the node in the syntax tree below the node in the segmentation to-be-checked set as segmentation particles according to the syntax tree graph until the father node of each node in the segmentation to-be-checked set is a marked node or a top node, and constructing an initial particle band.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of: analyzing a design file carrying preset nodes, wherein the design file is used for describing the structure of each circuit node of the circuit system and the connection relation among the circuit nodes, and extracting the connection relation to generate a syntax tree diagram corresponding to the circuit nodes; obtaining the current resource value and level information of each circuit node in the syntax tree diagram through a resource evaluation module; acquiring a resource theoretical upper limit value list of each circuit node from a threshold calculation module; marking all nodes with current resource values larger than the theoretical upper limit value of the resource, and determining an initial particle band according to the marked nodes, wherein the segmentation particles in the initial particle band comprise a plurality of circuit nodes in a syntax tree with resource weight; and adjusting and optimizing the initial particle band according to a preset node to obtain a segmentation particle band.
In one embodiment, the computer program when executed by the processor performs tuning optimization on the initial particle band according to a preset node to obtain a segmented particle band, the tuning optimization comprising: judging whether a preset node is positioned below the initial particle band in the syntax tree diagram; if so, deleting all father nodes corresponding to the preset nodes from the initial particle band according to the syntax tree graph; and determining an optimized particle band by adopting a minimum envelope method formed by the preset nodes to the upper layer of the grammar tree graph, and combining the optimized particle band with the initial particle bands of all the father nodes corresponding to the preset nodes, so as to obtain a segmentation particle band.
In one embodiment, the computer program when executed by the processor performs tuning optimization on the initial particle band according to a preset node to obtain a segmented particle band, the tuning optimization comprising: judging whether a preset node is positioned below the initial particle band in the syntax tree diagram; if not, judging whether the preset node is positioned above the initial particle band in the syntax tree diagram; and generating error reporting information according to the judgment result of the preset node above the initial particle band.
In one embodiment, the computer program when executed by a processor implements determining an initial grain band from a marker node, comprising: acquiring a segmentation empty set; adding all leaf nodes at the tail end of the syntax tree diagram into a segmentation empty set to obtain a segmentation to-be-checked set; when judging that no mark node exists in the leaf nodes, judging whether a father node for segmenting each leaf node in the set to be verified is a mark node; when the father node is judged to be the mark node, the leaf node is reserved in the segmentation to-be-verified set; when the father node is judged not to be the mark node, adding the father node into the segmentation to-be-verified set, and deleting all child nodes of the father node from the segmentation to-be-verified set; and setting each node in the segmentation to-be-checked set and the node in the syntax tree below the node in the segmentation to-be-checked set as segmentation particles according to the syntax tree graph until the father node of each node in the segmentation to-be-checked set is a marked node or a top node, and constructing an initial particle band.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (6)

1. A method of segmenting a particle band defining a resource distribution, comprising:
analyzing a design file carrying preset nodes, wherein the design file is used for describing the structure of each circuit node of a circuit system and the connection relation among the circuit nodes, and extracting the connection relation to generate a syntax tree diagram corresponding to the circuit nodes;
obtaining the current resource value and the level information of each circuit node in the grammar tree graph through a resource evaluation module;
acquiring a resource theoretical upper limit value list of each circuit node from a threshold calculation module;
marking all nodes with current resource values larger than the theoretical upper limit value of the resource, and determining an initial particle band according to the marked nodes, wherein the segmentation particles in the initial particle band comprise a plurality of circuit nodes in a syntax tree with resource weight;
adjusting and optimizing the initial particle band according to the preset node to obtain a segmentation particle band,
wherein the determining an initial particle band from the marker nodes comprises:
acquiring a segmentation empty set;
adding all leaf nodes at the tail end of the syntax tree diagram into a segmentation empty set to obtain a segmentation to-be-checked set;
when the leaf nodes are judged not to exist the mark nodes, judging whether father nodes of each leaf node in the segmentation to-be-verified set are the mark nodes or not;
when the father node is judged to be the mark node, the leaf node is reserved in the segmentation to-be-checked set; when the father node is judged not to be the mark node, adding the father node into the segmentation to-be-verified set, and deleting all child nodes of the father node from the segmentation to-be-verified set;
and setting each node in the segmentation to-be-checked set and nodes in a syntax tree below the node as segmentation particles according to the syntax tree graph until the father node of each node in the segmentation to-be-checked set is a mark node or a top node, and constructing an initial particle band.
2. The particle band segmentation method according to claim 1, wherein the adjusting and optimizing the initial particle band according to the preset node to obtain a segmented particle band comprises:
judging whether the preset node is positioned below the initial particle band in the syntax tree diagram;
when the judgment result is yes, deleting all father nodes corresponding to the preset nodes from the initial particle band according to the syntax tree graph;
and determining an optimized particle band by adopting a minimum envelope method formed by the preset nodes to the upper layer of the grammar tree graph, and combining the optimized particle band with the initial particle bands of all the father nodes corresponding to the preset nodes, so as to obtain a segmentation particle band.
3. The particle band segmentation method according to claim 1, wherein the adjusting and optimizing the initial particle band according to the preset node to obtain a segmented particle band comprises:
judging whether the preset node is positioned below the initial particle band in the syntax tree diagram;
when the judgment result is negative, judging whether the preset node is positioned above the initial particle band in the syntax tree diagram;
and generating error reporting information according to the judgment result of the preset node above the initial particle band.
4. A particle band splitting apparatus defining a resource distribution, the apparatus comprising:
the file analysis module is used for analyzing a design file carrying preset nodes, wherein the design file is used for describing the structure of each circuit node of the circuit system and the connection relation among the circuit nodes, and extracting the connection relation to generate a syntax tree diagram corresponding to the circuit nodes;
the resource value acquisition module is used for acquiring the current resource value and the level information of each circuit node in the syntax tree diagram through the resource evaluation module;
a theoretical threshold value obtaining module, configured to obtain a resource theoretical upper limit value list of each circuit node from the threshold value calculating module;
a marking module, configured to mark all nodes whose current resource values are greater than a resource theoretical upper limit value, and determine an initial grain band according to the marked nodes, where a partition grain in the initial grain band includes circuit nodes in a plurality of syntax trees with resource weights, and the determining the initial grain band according to the marked nodes includes: acquiring a segmentation empty set; adding all leaf nodes at the tail end of the syntax tree diagram into a segmentation empty set to obtain a segmentation to-be-checked set; when the leaf nodes are judged not to exist the mark nodes, judging whether father nodes of each leaf node in the segmentation to-be-verified set are the mark nodes or not; when the father node is judged to be the mark node, the leaf node is reserved in the segmentation to-be-checked set; when the father node is judged not to be the mark node, adding the father node into the segmentation to-be-verified set, and deleting all child nodes of the father node from the segmentation to-be-verified set; setting each node in the segmentation to-be-checked set and nodes in a syntax tree below the node as segmentation particles according to the syntax tree graph until father nodes of each node in the segmentation to-be-checked set are all marked nodes or top-level nodes, and constructing an initial particle band;
and the particle band segmentation module is used for adjusting and optimizing the initial particle band according to the preset node to obtain a segmented particle band.
5. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor realizes the steps of the method of any one of claims 1 to 3 when executing the computer program.
6. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 3.
CN202110628383.7A 2021-06-07 2021-06-07 Particle band dividing method, device, computer equipment and storage medium Active CN113255263B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110628383.7A CN113255263B (en) 2021-06-07 2021-06-07 Particle band dividing method, device, computer equipment and storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110628383.7A CN113255263B (en) 2021-06-07 2021-06-07 Particle band dividing method, device, computer equipment and storage medium

Publications (2)

Publication Number Publication Date
CN113255263A CN113255263A (en) 2021-08-13
CN113255263B true CN113255263B (en) 2021-10-01

Family

ID=77186594

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110628383.7A Active CN113255263B (en) 2021-06-07 2021-06-07 Particle band dividing method, device, computer equipment and storage medium

Country Status (1)

Country Link
CN (1) CN113255263B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114330173B (en) * 2022-03-08 2023-03-28 上海思尔芯技术股份有限公司 Boundary node connection relation obtaining method, device, equipment and storage medium
CN114781295B (en) * 2022-06-21 2022-09-09 上海国微思尔芯技术股份有限公司 Logic circuit scale reduction method and device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109445834A (en) * 2018-10-30 2019-03-08 北京计算机技术及应用研究所 The quick comparative approach of program code similitude based on abstract syntax tree

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69327389T2 (en) * 1992-10-29 2000-06-15 Altera Corp Procedure for testing designs for programmable logic circuits
JP3920308B2 (en) * 2003-10-31 2007-05-30 富士通株式会社 Verification support device, verification support method, verification support program, and recording medium
ATE470909T1 (en) * 2006-04-24 2010-06-15 Ericsson Telefon Ab L M CHECKING THE AUTHORITY OF INSTALLING A SOFTWARE VERSION
CN102231133B (en) * 2011-07-05 2013-07-03 上海交通大学 Concurrent real-time program verification optimized processing system and method based on rewrite logic
CN103310011A (en) * 2013-07-02 2013-09-18 曙光信息产业(北京)有限公司 Analytical method for data query under cluster database system environment
WO2018078451A1 (en) * 2016-10-25 2018-05-03 Reconfigure.Io Limited Synthesis path for transforming concurrent programs into hardware deployable on fpga-based cloud infrastructures
CN110268330B (en) * 2016-12-23 2022-01-28 Asml荷兰有限公司 Method and system for manufacturing electronic device using maskless photoetching exposure system
CN107748716A (en) * 2017-09-15 2018-03-02 深圳英飞拓科技股份有限公司 The lookup method and terminal device of a kind of bug
CN110716724B (en) * 2019-09-25 2021-01-08 支付宝(杭州)信息技术有限公司 Method and device for realizing privacy block chain based on FPGA
CN110941934A (en) * 2019-12-06 2020-03-31 思尔芯(上海)信息科技有限公司 FPGA prototype verification development board segmentation simulation system, method, medium and terminal
CN111475437A (en) * 2020-04-14 2020-07-31 深圳忆联信息系统有限公司 DDR (double data Rate) verification device and method for SOC (System on chip) chip FPGA prototype of solid state disk, computer equipment and storage medium
CN111898331A (en) * 2020-06-08 2020-11-06 北京智芯仿真科技有限公司 Random dynamic allocation method for frequency domain simulation calculation tasks of very large scale integrated circuit
CN112818585B (en) * 2021-04-20 2021-07-13 北京智芯仿真科技有限公司 Method and device for dividing iterative computation parallel particles of integrated circuit interlayer coupling

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109445834A (en) * 2018-10-30 2019-03-08 北京计算机技术及应用研究所 The quick comparative approach of program code similitude based on abstract syntax tree

Also Published As

Publication number Publication date
CN113255263A (en) 2021-08-13

Similar Documents

Publication Publication Date Title
CN113255263B (en) Particle band dividing method, device, computer equipment and storage medium
CN106919769B (en) Hierarchical FPGA (field programmable Gate array) layout and wiring method based on multi-level method and empowerment hypergraph
Hagen et al. A new approach to effective circuit clustering
CN113255264B (en) Incremental segmentation processing method and device, computer equipment and storage medium
CN109062565B (en) Artificial intelligence writing method for telemetry source code of digital satellite AOS protocol
US20120233575A1 (en) Layout method for integrated circuit including vias
US11055463B1 (en) Systems and methods for gate array with partial common inputs
CN113094355A (en) Model instantiation method, device, equipment and medium based on domestic communication protocol
CN114330173B (en) Boundary node connection relation obtaining method, device, equipment and storage medium
CN116501503B (en) Architecture mapping method and device for load task, computer equipment and medium
CN116911227A (en) Logic mapping method, device, equipment and storage medium based on hardware
CN107315863B (en) Layout optimization method and device, terminal and storage medium
US11790139B1 (en) Predicting a performance metric based on features of a circuit design and explaining marginal contributions of the features to the prediction
CN107704685B (en) Mesh division method and device
CN114036769B (en) Avionics system physical architecture-oriented function deployment scheme generation method and device
Cuoccio et al. A generation flow for self-reconfiguration controllers customization
Hong et al. CASH: A novel quadratic placement algorithm for very large standard cell layout design based on clustering
CN111274750A (en) FPGA simulation verification system and method based on visual modeling
CN113255262B (en) Object allocation method and device, computer equipment and storage medium
CN113568598B (en) Yosys-based FPGA logic synthesis method and device for realizing summation operation
CN108459968A (en) A kind of apparent energy consumption evaluation method of object-oriented code
CN117197165A (en) Automatic boundary selection segmentation iterative processing method, system, equipment and medium
CN115544626B (en) Sub-model extraction method, device, computer equipment and medium
CN113312865B (en) Method and device for screening divided clocks, computer equipment and storage medium
US20230098098A1 (en) Scalable scribe regions for implementing user circuit designs in an integrated circuit using dynamic function exchange

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Room 27, 6th floor, No. 29 and 30, Lane 1775, Qiushan Road, Lingang New District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 201306

Patentee after: Shanghai Sierxin Technology Co.,Ltd.

Address before: Room 27, 6th floor, No. 29 and 30, Lane 1775, Qiushan Road, Lingang New District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 201306

Patentee before: Shanghai Guowei silcore Technology Co.,Ltd.