CN113312865B - Method and device for screening divided clocks, computer equipment and storage medium - Google Patents
Method and device for screening divided clocks, computer equipment and storage medium Download PDFInfo
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- CN113312865B CN113312865B CN202110867351.2A CN202110867351A CN113312865B CN 113312865 B CN113312865 B CN 113312865B CN 202110867351 A CN202110867351 A CN 202110867351A CN 113312865 B CN113312865 B CN 113312865B
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
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- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Abstract
The invention provides a method and a device for screening a partition clock, computer equipment and a storage medium, belonging to the field of chip design, and particularly comprising the steps of analyzing a design file of a programmable logic verification array to obtain a grammar node and grammar node information; acquiring the minimum number of the divided clocks and a preset clock cutting list; determining a first segmentation clock according to the syntax node information; clustering and merging all grammar nodes; screening a second division clock from a preset clock division list according to the occurrence frequency of each node clock in the combined grammar node information; distributing the syntax tree structure to the programmable logic array according to the minimum number of the division clocks and the connection line weight value to obtain a third division clock corresponding to the programmable logic array; a split clock list is generated from the first split clock, the second split clock, and the third split clock. By the processing scheme, the difficulty of time sequence analysis and TDM insertion is reduced, and the performance and accuracy of system operation can be improved.
Description
Technical Field
The invention relates to the field of chip design, in particular to a method and a device for screening a division clock, computer equipment and a storage medium.
Background
Design files require multiple pieces of programmable logic array interconnections to be able to accommodate and verify. The programmable logic array may be an FPGA. In general, an FPGA verification system is adopted to segment and verify a large design file, but in the FPGA verification system, the time delay of cross-FPGA signal transmission is much longer than that of FPGA internal signal transmission. When a clock signal needs to be transmitted across FPGAs, the delay of the transmission of the signal across FPGAs may cause clock phase offset, and generally, the FPGA verification system adopts methods of copying the clock across FPGAs on each FPGA, reducing the clock frequency of a user, and the like, so as to avoid the problems caused by the clock phase offset, but this increases the difficulty of timing analysis and TDM insertion, and greatly reduces the performance of system operation. The specific reasons are as follows:
1. time sequence analysis: each FPGA is provided with a time sequence analyzer, and the time sequence analyzer is used for analyzing by combining engineering on the FPGA and input and output clock signals, so that the establishment time and the holding time can be ensured to be met, and the designed function and performance can be ensured. As more clock signals need to be passed across the FPGA, the more variables the timing analyzer needs to incorporate into the analysis, the greater the difficulty.
2. TDM insertion: clock signals required to be transmitted across the FPGAs on each FPGA correspond to one TDM packet. As more clock signals need to be passed across the FPGA, the more packets the TDM needs to insert.
Therefore, a clock screening method capable of screening clocks with low cutting times and less fan-out is urgently needed.
Disclosure of Invention
Therefore, in order to overcome the above-mentioned shortcomings in the prior art, the present invention provides a method, an apparatus, a computer device and a storage medium for partitioning a specified number of clocks, which not only reduces the difficulty of timing analysis and TDM insertion, but also improves the performance and accuracy of system operation.
In order to achieve the above object, the present invention provides a method for screening split clocks, including: analyzing a design file of the programmable logic verification array to obtain grammar nodes of a grammar tree structure and grammar node information, wherein the grammar node information at least comprises a connecting line weight value between the grammar nodes and associated nodes and a node clock corresponding to the grammar nodes; acquiring the minimum number of the divided clocks and a preset clock cutting list; determining a first segmentation clock according to the grammar node information, deleting the first segmentation clock in the grammar node information, and resetting a connection line weight value between the grammar node and an associated node; according to the updated grammar node information, clustering and merging all grammar nodes; screening a second division clock from the preset clock division list according to the occurrence frequency of each node clock in the combined grammar node information, deleting the second division clock in the grammar node information, and setting a connection line weight value between the grammar node and an associated node again; distributing the syntax tree structure to a programmable logic array according to the minimum number of the partition clocks and the connection line weight value to obtain a third partition clock corresponding to the programmable logic array; generating a split clock list according to the first split clock, the second split clock, and the third split clock.
In one embodiment, the screening the second partition clock from the preset clock partition list according to the number of occurrences of each node clock in the combined syntax node information includes: sorting the node clocks in the preset clock cutting list according to the occurrence frequency of each node clock in the combined grammar node information to obtain a current clock sorting list; and screening out the node clock with the highest current time number from the current clock ordered list as a second division clock.
In one embodiment, the allocating the syntax tree structure to a programmable logic array according to the minimum number of split clocks and the link weight value to obtain a third split clock corresponding to the programmable logic array includes: distributing the syntax tree structure to a programmable logic array according to the connection weight value to the syntax tree structure to obtain a clock to be divided corresponding to the programmable logic array; when the clock to be divided is judged not to be overlapped with the first divided clock and the second divided clock, setting the clock to be divided as a third divided clock; deleting the third partition clock in the grammar node information, and setting the weight value of the connecting line between the grammar node and the associated node again until the number of the first partition clock, the second partition clock and the third partition clock reaches the minimum number of the partition clocks.
In one embodiment, when it is determined that the clock to be divided overlaps the first divided clock and the second divided clock, the method further includes: restoring the grammar nodes of the clustering combination; judging whether the number of cutting connecting lines is reduced and a node clock for cutting is not added when the restored grammar node is moved to another programmable logic array; when the judgment result is positive, setting the node clock corresponding to the French node as a fourth segmentation clock; and generating a division clock list according to the first division clock, the second division clock, the third division clock and the fourth division clock.
In one embodiment, the resetting the link weight value between the grammar node and the associated node includes: judging whether the node clock of the associated node has the preset clock cutting list or not; when the node clock of the associated node is judged to have no preset clock cutting list, increasing the weight value of a connecting line between the grammar node and the associated node; and when the node clock of the associated node is judged to have the preset clock cutting list, maintaining the connection weight value between the grammar node and the associated node.
The invention provides a device for screening split clocks, which comprises: the file analysis module is used for analyzing the design file of the programmable logic verification array to obtain grammar nodes of a grammar tree structure and grammar node information, wherein the grammar node information at least comprises a connecting line weight value between the grammar nodes and a node clock corresponding to the grammar nodes; the preset information acquisition module is used for acquiring the minimum number of the divided clocks and a preset clock cutting list; the first clock screening module is used for determining a first segmentation clock according to the grammar node information, deleting the first segmentation clock in the grammar node information and resetting a connection line weight value between the grammar node and an associated node; the node clustering module is used for clustering and merging all grammar nodes according to the updated grammar node information; a second clock screening module, configured to screen a second partition clock from the preset clock partition list according to the number of times that each node clock appears in the merged syntax node information, delete the second partition clock in the syntax node information, and set a connection weight value between the syntax node and an associated node again; the third clock screening module is used for distributing the syntax tree structure to the programmable logic array according to the minimum number of the divided clocks and the connecting line weight value to obtain a third divided clock corresponding to the programmable logic array; a list generating module, configured to generate a split clock list according to the first split clock, the second split clock, and the third split clock.
In one embodiment, the second clock filtering module comprises: the sorting unit is used for sorting the node clocks in the preset clock cutting list according to the occurrence frequency of each node clock in the combined grammar node information to obtain a current clock sorting list; and the second clock screening unit is used for screening out the node clock with the highest current time number from the current clock sorting list as a second division clock.
In one embodiment, the third clock filtering module comprises: the distribution unit is used for distributing the grammar tree structure to a programmable logic array according to the connection line weight value to the grammar tree structure so as to obtain a clock to be divided corresponding to the programmable logic array; a third clock screening unit configured to set the clock to be divided as a third divided clock when it is determined that the clock to be divided is not overlapped with the first divided clock and the second divided clock; and the repeating unit is used for deleting the third division clock in the grammar node information, and setting the connection line weight value between the grammar node and the associated node again until the number of the first division clock, the second division clock and the third division clock reaches the minimum division clock number.
A computer device comprising a memory storing a computer program and a processor implementing the steps of the above method when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method.
Compared with the prior art, the invention has the advantages that: the design can be divided by the clock with low frequency and less fan-out according to the number of the divided clocks set by the user and the clock list which is divided preferentially, the actual requirements of the user are met, the difficulties of time sequence analysis, logic verification and TDM insertion are reduced, and the performance and the accuracy of system operation are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a split clock screening method in one embodiment of the invention;
FIG. 2 is a schematic diagram of the split clock filtering step in one embodiment of the present invention;
FIG. 3 is a block diagram of a split clock filter apparatus according to an embodiment of the present invention;
fig. 4 is an internal structural diagram of a computer device in an embodiment of the present invention.
Detailed Description
The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number and aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that aspects may be practiced without these specific details.
As shown in fig. 1, an embodiment of the present application provides a method for screening split clocks, which may be applied to a terminal or a server, where the terminal may be but is not limited to various personal computers, notebook computers, smart phones, tablet computers, and portable smart devices, and the server may be implemented by an independent server or a server cluster formed by multiple servers, and the method includes the following steps:
The design file is used for describing the structure of each circuit node of the circuit system and the connection relation between the circuit nodes. The design file contains a plurality of logic program blocks (modules), nesting or parallel relation exists among the logic program blocks, and each logic program block corresponds to each circuit node of the circuit system. A circuit node may be one or more electronic components. A programmable logic verification array is an array of elements made up of a plurality of programmable logic devices. In one embodiment, the programmable logic device may be an FPGA. The design file may include a module name setting file, a module division file, and a syntax node information file. The module name setting file contains original design module name information corresponding to each grammar node, and the original design module name information corresponding to each grammar node can be known through the module name setting file. The module division file contains division standard information designated in advance. The syntax node information file contains syntax node information.
The grammar node information at least comprises a connecting line weight value between the grammar node information and the associated node and a node clock corresponding to the grammar node. The syntax node information may include the number of resources occupied by each syntax node, a node clock name directly connected to a clock input pin of the syntax node, net connection information between nodes, and the like. The resource number is the total number of node resources which need to be carried by each grammar node in each FPGA operation, and can not exceed the total number of the resources of the FPGA. The node clock name is the clock domain to which the node belongs, and can be represented by clk, and one clock domain can correspond to the node clocks of a plurality of syntax nodes and provide a uniform clock signal for the syntax nodes. The net connection information is the connection relationship between nodes, and may include a connection weight value. The division standard information is information that a user fixes some nodes to a certain FPGA board in advance. And the server analyzes the design file applied to the programmable logic verification array to obtain the grammar nodes and grammar node information of the grammar tree structure.
The server obtains the minimum number N of the divided clocks and a preset clock cutting list clk _ list. N represents the minimum value of the number of divisible clocks (when N =0, it represents no limitation to the number of divisible clocks). The minimum number of split clocks N may be user set. The preset clock cutting list may be a user-specified clock list.
And 103, determining a first segmentation clock according to the grammar node information, deleting the first segmentation clock in the grammar node information, and resetting a connection line weight value between the grammar node and the associated node.
The associated node is a drive node (driver node) connected with the grammar node through a connecting line, and can input data to the grammar node or receive data output by the grammar node. And the server determines the first segmentation clock according to the grammar node information, deletes the first segmentation clock in the grammar node information, and resets the weight value of the connecting line between the grammar node and the associated node. And the server determines a clock which is to be cut according to the grammar node information, wherein the clock is the first cutting clock. Let m first split clocks, the first split clock list is cut _ clk _ list. The server retrieves node clocks carried by all the grammar nodes, and deletes the clock of the grammar node when judging that the clock of the node exists in cut _ clk _ list; and searching all related nodes connected with the net of the grammar node, and if the related nodes have clocks which are not in the clk _ list, giving higher weight values to the net.
And step 104, clustering and merging all grammar nodes according to the updated grammar node information.
And the server performs clustering combination on all the grammar nodes according to the updated grammar node information. The clustering merging algorithm can be a conventional common clustering algorithm, and only needs to merge grammar node parts according to updated grammar node information and reduce the magnitude order of segmentation.
And 105, screening a second division clock from the preset clock division list according to the occurrence frequency of each node clock in the combined grammar node information, deleting the second division clock in the grammar node information, and setting the weight value of the connecting line between the grammar node and the associated node again.
And the server screens a second division clock from the preset clock division list according to the occurrence frequency of each node clock in the combined grammar node information, deletes the second division clock in the grammar node information, and sets the weight value of the connecting line between the grammar node and the associated node again. Setting the connection weight values in the steps 103 and 105 according to a preset rule, wherein the preset rule is that when the deleted clock does not have a preset clock cutting list, the connection weight value between the grammar node and the associated node is increased; and when the deleted clock does not have the preset clock cutting list, maintaining the current connection line weight value. However, in the two steps, the increasing ranges of the weight values may be different.
And 106, distributing the syntax tree structure to the programmable logic array according to the minimum number of the partition clocks and the connection line weight value to obtain a third partition clock corresponding to the programmable logic array.
And the server distributes the syntax tree structure to the programmable logic array according to the minimum number of the divided clocks and the connection line weight value to obtain a third divided clock corresponding to the programmable logic array.
The server generates a split clock list according to the first split clock, the second split clock and the third split clock.
The method for screening the divided clocks can divide the clocks with low frequency and less fan-out according to the number of the divided clocks set by the user and the clock list which is preferentially cut, meets the actual requirements of the user, simultaneously lightens the difficulties of time sequence analysis, logic verification and TDM insertion, and improves the performance and accuracy of system operation.
In one embodiment, the step of filtering the second partition clock from the preset clock partition list according to the occurrence frequency of each node clock in the merged syntax node information comprises the following steps: according to the occurrence frequency of each node clock in the combined grammar node information, sorting the node clocks in a preset clock cutting list to obtain a current clock sorting list; and screening out the node clock with the highest current time number from the current clock ordered list as a second division clock.
And the server sorts the node clocks in the preset clock cutting list according to the occurrence frequency of each node clock in the combined grammar node information to obtain a current clock sorting list. After the server retrieves and deletes the first segmentation clock, the times of all node clocks in all grammar nodes are appeared, and the clocks in the clk _ list are sorted from high to low according to the appearing times. And the server screens out the node clock with the highest current time number from the current clock ordered list as a second division clock.
As shown in fig. 2, in an embodiment, the step of distributing the syntax tree structure to the programmable logic array according to the minimum number of the split clocks and the link weight value to obtain a third split clock corresponding to the programmable logic array includes the following steps:
During the process of analyzing (Parse) the design file by the server, the module can be instantiated into a logic Instance (Instance) and forms a syntax tree structure with a hierarchical relationship, and the Instance is a Node (Node) in an Instance tree diagram. The instances contain logic functions, and the instances have a connection relationship. Each Instance uniquely corresponds to a Module, the nesting relationship among the modules forms the connection relationship among the nodes in the syntax tree structure, and the logic relationship among the nodes also comprises the link weight value between the nodes and the associated nodes. The server can adopt various existing segmentation algorithms to segment all grammar nodes, determine the programmable logic array corresponding to the grammar nodes, and further determine the clock to be segmented corresponding to the programmable logic array.
And when the clock to be divided is judged not to be overlapped with the first divided clock and the second divided clock, the server sets the clock to be divided as a third divided clock.
And step 203, deleting the third partition clock in the grammar node information, and setting the connection weight value between the grammar node and the associated node again until the number of the first partition clock, the second partition clock and the third partition clock reaches the minimum number of the partition clocks.
And the server deletes the third partition clock in the grammar node information, and sets the connection weighted value between the grammar node and the associated node again until the number of the first partition clock, the second partition clock and the third partition clock reaches the minimum number of the partition clocks. The number of server cycles is N-m.
In one embodiment, when it is determined that the clock to be divided overlaps the first divided clock and the second divided clock, the method further includes the steps of: restoring the grammar nodes of the clustering combination; judging whether the number of cutting connecting lines is reduced and a node clock for cutting is not added when the restored grammar node is moved to another programmable logic array; when the judgment result is positive, setting the node clock corresponding to the French node as a fourth segmentation clock; a split clock list is generated from the first split clock, the second split clock, the third split clock, and the fourth split clock.
When the clock to be divided is judged to be overlapped with the first division clock and the second division clock, the server judges that the order of magnitude of the division is too fine, and the server restores the grammar nodes which are clustered and merged in the step 104. The server attempts to move to another FPGA one by aggregating the syntax nodes together to realize the restoration of the nodes. The server judges whether the number of the cutting connecting lines is reduced and a node clock for cutting is not added when the restored grammar node is moved to another programmable logic array. And when the judgment result is positive, setting the node clock corresponding to the French node as a fourth segmentation clock. The server generates a split clock list according to the first split clock, the second split clock, the third split clock and the fourth split clock.
In one embodiment, after deleting the first partition clock, the second partition clock, or the third partition clock, resetting the connection weight value between the syntax node and the associated node may include the following steps: judging whether a node clock of the associated node has a preset clock cutting list or not; when judging that the node clock of the associated node does not have the preset clock cutting list, increasing the weight value of a connecting line between the grammar node and the associated node; and when the node clock of the associated node is judged to have the preset clock cutting list, maintaining the connection line weight value between the grammar node and the associated node.
And the server judges whether the node clock of the associated node has a preset clock cutting list or not. When the server judges that the node clock of the associated node does not have the preset clock cutting list, the connection line weight value between the grammar node and the associated node is increased; and when the server judges that the node clock of the associated node has the preset clock cutting list, maintaining the connection weight value between the grammar node and the associated node.
In one embodiment, as shown in fig. 3, a device for screening split clocks is provided, and the device includes a file parsing module 301, a preset information obtaining module 302, a first clock screening module 303, a node clustering module 304, a second clock screening module 305, a third clock screening module 306, and a list generating module 307:
the file analysis module 301 is configured to analyze the design file of the programmable logic verification array to obtain a syntax node and syntax node information of a syntax tree structure, where the syntax node information at least includes a connection weight value between the relevant node and a node clock corresponding to the syntax node.
The preset information obtaining module 302 is configured to obtain a minimum number of divided clocks and a preset clock cutting list.
The first clock screening module 303 is configured to determine a first partition clock according to the syntax node information, delete the first partition clock in the syntax node information, and reset a connection weight value between the syntax node and the associated node.
And the node clustering module 304 is configured to perform clustering and merging on all syntax nodes according to the updated syntax node information.
The second clock filtering module 305 is configured to filter a second partition clock from the preset clock partition list according to the occurrence frequency of each node clock in the merged syntax node information, delete the second partition clock in the syntax node information, and set a connection weight value between the syntax node and the associated node again.
And a third clock filtering module 306, configured to distribute the syntax tree structure to the programmable logic array according to the minimum number of the split clocks and the connection weight value, so as to obtain a third split clock corresponding to the programmable logic array.
A list generating module 307 configured to generate a split clock list according to the first split clock, the second split clock, and the third split clock.
In one embodiment, the second clock filter module comprises:
and the sequencing unit is used for sequencing the node clocks in the preset clock cutting list according to the occurrence frequency of each node clock in the combined grammar node information to obtain a current clock sequencing list.
And the second clock screening unit is used for screening the node clock with the highest current time number from the current clock sorted list to serve as a second division clock.
In one embodiment, the third clock filtering module comprises:
and the distribution unit is used for distributing the syntax tree structure to the programmable logic array according to the connection weight value and the syntax tree structure to obtain the clock to be divided corresponding to the programmable logic array.
And the third clock screening unit is used for setting the clock to be divided into a third divided clock when the clock to be divided is judged not to be overlapped with the first divided clock and the second divided clock.
And the repeating unit is used for deleting the third division clock in the grammar node information, and setting the connection weighted value between the grammar node and the associated node again until the number of the first division clock, the second division clock and the third division clock reaches the minimum division clock number.
In one embodiment, the apparatus further comprises:
and the restoring module is used for restoring the grammar nodes combined by the clusters.
And the clock modification module is used for judging whether the number of the cutting connecting lines is reduced and the node clock of the cutting is not newly added when the restored grammar node is moved to another programmable logic array.
And the fourth clock setting module is used for setting the node clock corresponding to the French node as the fourth division clock when the judgment result is positive.
And the list generating module is used for generating a division clock list according to the first division clock, the second division clock, the third division clock and the fourth division clock.
In one embodiment, the first clock filtering module, the second clock filtering module, and the third clock filtering module each include:
and the clock judging unit is used for judging whether the node clock of the associated node has a preset clock cutting list or not.
The weight value setting unit is used for increasing the weight value of a connecting line between the grammar node and the associated node when judging that the node clock of the associated node does not have a preset clock cutting list; and when the node clock of the associated node is judged to have the preset clock cutting list, maintaining the connection line weight value between the grammar node and the associated node.
For specific limitations of the divided clock filtering apparatus, reference may be made to the above limitations of the divided clock filtering method, which are not described herein again. The respective modules in the divided clock filtering apparatus described above may be implemented in whole or in part by software, hardware, and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a server, the internal structure of which may be as shown in fig. 4. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is for storing split clock screening data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a split clock screening method.
In one embodiment, there is provided a computer device comprising a memory storing a computer program and a processor implementing the following steps when the processor executes the computer program: analyzing a design file of the programmable logic verification array to obtain grammar nodes of a grammar tree structure and grammar node information, wherein the grammar node information at least comprises a connecting line weight value between the grammar nodes and a node clock corresponding to the grammar nodes; acquiring the minimum number of the divided clocks and a preset clock cutting list; determining a first segmentation clock according to the grammar node information, deleting the first segmentation clock in the grammar node information, and resetting a connection line weight value between the grammar node and the associated node; according to the updated grammar node information, clustering and merging all grammar nodes; screening a second division clock from a preset clock division list according to the occurrence frequency of each node clock in the combined grammar node information, deleting the second division clock in the grammar node information, and setting the weight value of a connecting line between the grammar node and the associated node again; distributing the syntax tree structure to the programmable logic array according to the minimum number of the division clocks and the connection line weight value to obtain a third division clock corresponding to the programmable logic array; a split clock list is generated from the first split clock, the second split clock, and the third split clock.
In one embodiment, the filtering of the second split clock from the preset clock split list based on the number of occurrences of each node clock in the merged syntax node information by the processor when executing the computer program comprises: according to the occurrence frequency of each node clock in the combined grammar node information, sorting the node clocks in a preset clock cutting list to obtain a current clock sorting list; and screening out the node clock with the highest current time number from the current clock ordered list as a second division clock.
In one embodiment, the allocating, by the processor when executing the computer program, the syntax tree structure to the programmable logic array according to the minimum number of split clocks and the link weight value to obtain a third split clock corresponding to the programmable logic array includes: distributing the syntax tree structure to the programmable logic array according to the connection weight value to the syntax tree structure to obtain a clock to be divided corresponding to the programmable logic array; when the clock to be divided is judged not to be overlapped with the first divided clock and the second divided clock, setting the clock to be divided as a third divided clock; and deleting the third partition clock in the grammar node information, and setting the connection weighted value between the grammar node and the associated node again until the number of the first partition clock, the second partition clock and the third partition clock reaches the minimum number of the partition clocks.
In one embodiment, when determining that the clock to be divided overlaps the first division clock and the second division clock, the method implemented when the processor executes the computer program further includes: restoring the grammar nodes of the clustering combination; judging whether the number of cutting connecting lines is reduced and a node clock for cutting is not added when the restored grammar node is moved to another programmable logic array; when the judgment result is positive, setting the node clock corresponding to the French node as a fourth segmentation clock; a split clock list is generated from the first split clock, the second split clock, the third split clock, and the fourth split clock.
In one embodiment, the resetting of the link weight value between the grammar node and the associated node, which is performed by the processor when executing the computer program, includes: judging whether a node clock of the associated node has a preset clock cutting list or not; when judging that the node clock of the associated node does not have the preset clock cutting list, increasing the weight value of a connecting line between the grammar node and the associated node; and when the node clock of the associated node is judged to have the preset clock cutting list, maintaining the connection line weight value between the grammar node and the associated node.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of: analyzing a design file of the programmable logic verification array to obtain grammar nodes of a grammar tree structure and grammar node information, wherein the grammar node information at least comprises a connecting line weight value between the grammar nodes and a node clock corresponding to the grammar nodes; acquiring the minimum number of the divided clocks and a preset clock cutting list; determining a first segmentation clock according to the grammar node information, deleting the first segmentation clock in the grammar node information, and resetting a connection line weight value between the grammar node and the associated node; according to the updated grammar node information, clustering and merging all grammar nodes; screening a second division clock from a preset clock division list according to the occurrence frequency of each node clock in the combined grammar node information, deleting the second division clock in the grammar node information, and setting the weight value of a connecting line between the grammar node and the associated node again; distributing the syntax tree structure to the programmable logic array according to the minimum number of the division clocks and the connection line weight value to obtain a third division clock corresponding to the programmable logic array; a split clock list is generated from the first split clock, the second split clock, and the third split clock.
In one embodiment, the computer program when executed by the processor for implementing the method for filtering the second split clock from the preset clock split list according to the number of occurrences of each node clock in the merged syntax node information comprises: according to the occurrence frequency of each node clock in the combined grammar node information, sorting the node clocks in a preset clock cutting list to obtain a current clock sorting list; and screening out the node clock with the highest current time number from the current clock ordered list as a second division clock.
In one embodiment, a method for distributing a syntax tree structure to a programmable logic array according to a minimum number of split clocks and link weight values when a computer program is executed by a processor to obtain a third split clock corresponding to the programmable logic array includes: distributing the syntax tree structure to the programmable logic array according to the connection weight value to the syntax tree structure to obtain a clock to be divided corresponding to the programmable logic array; when the clock to be divided is judged not to be overlapped with the first divided clock and the second divided clock, setting the clock to be divided as a third divided clock; and deleting the third partition clock in the grammar node information, and setting the connection weighted value between the grammar node and the associated node again until the number of the first partition clock, the second partition clock and the third partition clock reaches the minimum number of the partition clocks.
In one embodiment, the computer program when executed by the processor implements when determining that the clock to be divided overlaps the first division clock and the second division clock, the method further comprising: restoring the grammar nodes of the clustering combination; judging whether the number of cutting connecting lines is reduced and a node clock for cutting is not added when the restored grammar node is moved to another programmable logic array; when the judgment result is positive, setting the node clock corresponding to the French node as a fourth segmentation clock; a split clock list is generated from the first split clock, the second split clock, the third split clock, and the fourth split clock.
In one embodiment, the computer program when executed by the processor implements resetting the link weight values between the grammar node and the associated nodes, including: judging whether a node clock of the associated node has a preset clock cutting list or not; when judging that the node clock of the associated node does not have the preset clock cutting list, increasing the weight value of a connecting line between the grammar node and the associated node; and when the node clock of the associated node is judged to have the preset clock cutting list, maintaining the connection line weight value between the grammar node and the associated node.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method of split clock screening, comprising:
analyzing a design file of the programmable logic verification array to obtain grammar nodes of a grammar tree structure and grammar node information, wherein the grammar node information at least comprises a connecting line weight value between the grammar nodes and associated nodes and a node clock corresponding to the grammar nodes;
acquiring the minimum number of the divided clocks and a preset clock cutting list;
determining a first segmentation clock according to the grammar node information, deleting the first segmentation clock in the grammar node information, and resetting a connection line weight value between the grammar node and an associated node;
according to the updated grammar node information, clustering and merging all grammar nodes;
screening a second division clock from the preset clock cutting list according to the occurrence frequency of each node clock in the combined grammar node information, deleting the second division clock in the grammar node information, and resetting a connection line weight value between the grammar node and an associated node again, wherein the connection line weight value is set according to a preset rule, and the preset rule is that when the deleted clock does not have the preset clock cutting list, the connection line weight value between the grammar node and the associated node is increased; when the deleted clock has no preset clock cutting list, maintaining the current connection line weight value;
distributing the syntax tree structure to a programmable logic array according to the minimum number of the partition clocks and the connection line weight value to obtain a third partition clock corresponding to the programmable logic array;
generating a split clock list according to the first split clock, the second split clock, and the third split clock.
2. The method as claimed in claim 1, wherein the screening the second split clock from the preset clock splitting list according to the number of occurrences of each node clock in the combined syntax node information comprises:
sorting the node clocks in the preset clock cutting list according to the occurrence frequency of each node clock in the combined grammar node information to obtain a current clock sorting list;
and screening out the node clock with the highest current time number from the current clock ordered list as a second division clock.
3. The method of claim 1, wherein the distributing the syntax tree structure to a programmable logic array according to the minimum number of split clocks and the link weight value to obtain a third split clock corresponding to the programmable logic array comprises:
distributing the syntax tree structure to a programmable logic array according to the connection weight value to the syntax tree structure to obtain a clock to be divided corresponding to the programmable logic array;
when the clock to be divided is judged not to be overlapped with the first divided clock and the second divided clock, setting the clock to be divided as a third divided clock;
deleting the third partition clock in the grammar node information, and setting the weight value of the connecting line between the grammar node and the associated node again until the number of the first partition clock, the second partition clock and the third partition clock reaches the minimum number of the partition clocks.
4. The split clock screening method according to claim 3, wherein when it is determined that the clock to be split overlaps with the first split clock and the second split clock, the method further comprises:
restoring the grammar nodes of the clustering combination;
judging whether the number of cutting connecting lines is reduced and a node clock for cutting is not added when the restored grammar node is moved to another programmable logic array;
when the judgment result is positive, setting the node clock corresponding to the French node as a fourth segmentation clock;
and generating a division clock list according to the first division clock, the second division clock, the third division clock and the fourth division clock.
5. The method of claim 1, wherein the resetting the link weight value between the grammar node and the associated node comprises:
judging whether the node clock of the associated node has the preset clock cutting list or not;
when the node clock of the associated node is judged to have no preset clock cutting list, increasing the weight value of a connecting line between the grammar node and the associated node; and when the node clock of the associated node is judged to have the preset clock cutting list, maintaining the connection weight value between the grammar node and the associated node.
6. A split clock screening apparatus, the apparatus comprising:
the file analysis module is used for analyzing the design file of the programmable logic verification array to obtain grammar nodes of a grammar tree structure and grammar node information, wherein the grammar node information at least comprises a connecting line weight value between the grammar nodes and a node clock corresponding to the grammar nodes;
the preset information acquisition module is used for acquiring the minimum number of the divided clocks and a preset clock cutting list;
the first clock screening module is used for determining a first segmentation clock according to the grammar node information, deleting the first segmentation clock in the grammar node information and resetting a connection line weight value between the grammar node and an associated node;
the node clustering module is used for clustering and merging all grammar nodes according to the updated grammar node information;
a second clock screening module, configured to screen a second division clock from the preset clock division list according to the number of times that each node clock appears in the merged syntax node information, delete the second division clock in the syntax node information, and reset a connection weight value between the syntax node and an associated node again, where the connection weight value is set according to a predetermined rule, and the predetermined rule is that when the deleted clock does not have the preset clock division list, the connection weight value between the syntax node and the associated node is increased; when the deleted clock has no preset clock cutting list, maintaining the current connection line weight value;
the third clock screening module is used for distributing the syntax tree structure to the programmable logic array according to the minimum number of the divided clocks and the connecting line weight value to obtain a third divided clock corresponding to the programmable logic array;
a list generating module, configured to generate a split clock list according to the first split clock, the second split clock, and the third split clock.
7. The split clock screening apparatus of claim 6, wherein the second clock screening module comprises:
the sorting unit is used for sorting the node clocks in the preset clock cutting list according to the occurrence frequency of each node clock in the combined grammar node information to obtain a current clock sorting list;
and the second clock screening unit is used for screening out the node clock with the highest current time number from the current clock sorting list as a second division clock.
8. The split clock screening apparatus of claim 6, wherein the third clock screening module comprises:
the distribution unit is used for distributing the grammar tree structure to a programmable logic array according to the connection line weight value to the grammar tree structure so as to obtain a clock to be divided corresponding to the programmable logic array;
a third clock screening unit configured to set the clock to be divided as a third divided clock when it is determined that the clock to be divided is not overlapped with the first divided clock and the second divided clock;
and the repeating unit is used for deleting the third division clock in the grammar node information, and setting the connection line weight value between the grammar node and the associated node again until the number of the first division clock, the second division clock and the third division clock reaches the minimum division clock number.
9. A computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor implements the steps of the method of any one of claims 1 to 5 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 5.
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