CN113223953A - Manufacturing method and manufacturing equipment of fast recovery chip and fast recovery chip - Google Patents
Manufacturing method and manufacturing equipment of fast recovery chip and fast recovery chip Download PDFInfo
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- CN113223953A CN113223953A CN202110348517.XA CN202110348517A CN113223953A CN 113223953 A CN113223953 A CN 113223953A CN 202110348517 A CN202110348517 A CN 202110348517A CN 113223953 A CN113223953 A CN 113223953A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
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- 238000009792 diffusion process Methods 0.000 claims abstract description 228
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 142
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 127
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 127
- 239000010703 silicon Substances 0.000 claims abstract description 127
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 102
- 229910052796 boron Inorganic materials 0.000 claims abstract description 102
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- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 93
- 239000011574 phosphorus Substances 0.000 claims abstract description 93
- 238000005498 polishing Methods 0.000 claims abstract description 78
- 239000007788 liquid Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 16
- 238000005488 sandblasting Methods 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3046—Mechanical treatment, e.g. grinding, polishing, cutting using blasting, e.g. sand-blasting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
Abstract
The application discloses a manufacturing method, manufacturing equipment and a fast recovery chip of a fast recovery chip, wherein the manufacturing method comprises the following steps: carrying out phosphorus diffusion on the silicon wafer by using a phosphorus source to form a phosphorus diffusion structural layer on at least one surface of the silicon wafer; removing the phosphorus diffusion structure layer on one surface of the silicon wafer; carrying out boron diffusion on the silicon wafer by using a boron source so as to form a boron diffusion structural layer on one surface of the silicon wafer, which is removed from the phosphorus diffusion structural layer; polishing the surface of the boron diffusion structure layer to form a first polished surface; performing platinum diffusion on the first polishing surface by using a platinum source to form a platinum diffusion structure layer on the first polishing surface; preparing a fast recovery chip by adopting the silicon chip subjected to platinum diffusion; the polishing surface is formed before platinum diffusion, so that platinum diffusion is more uniform, the original structure of the silicon wafer is prevented from being damaged due to nonuniform platinum distribution, and the recovery characteristic of the chip is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor electronic component manufacturing, in particular to a manufacturing method and manufacturing equipment of a fast recovery chip and the fast recovery chip.
Background
The main circuit in modern power electronic circuit, whether it adopts a thyristor switched off by current conversion or a novel power electronic device with self-turn-off capability, needs a power fast recovery diode connected in parallel with it to reduce the charging time of the main switch device capacitor by the reactive current in the load, and at the same time, it restrains the high voltage induced by the parasitic inductance when the load current is instantaneously reversed. In recent years, with the continuous progress of the manufacturing technology of power semiconductor devices, the design and manufacture of novel power semiconductor devices such as vertical double-diffused metal-oxide semiconductor field effect transistors (DMOSFETs) and Insulated Gate Bipolar Transistors (IGBTs) of main switch devices in power electronic circuits have made great progress, and the frequency performance is continuously improved, which puts higher requirements on fast power recovery diodes used in cooperation with the fast power recovery diodes. Therefore, the diode must have a short reverse recovery time and excellent overall performance. Fast recovery diodes with P-i-N structures are the first choice devices for high voltage applications with high withstand voltage and high switching speed.
The production process of the semiconductor chip needs to carry out platinum expansion treatment after boron expansion and before GPP production, stirring and uniformly coating a configured platinum source, then loading the chip into a boat, feeding the chip into a furnace, discharging the chip out of the furnace and cooling the chip, and the recovery characteristic of the product is influenced because the phenomenon of uneven diffusion often occurs when the platinum is diffused in the chip in the prior art.
Disclosure of Invention
The application aims to provide a manufacturing method and manufacturing equipment of a fast recovery chip and the fast recovery chip, which can improve the dispersion uniformity of platinum in a silicon wafer so as to improve the recovery characteristic of the chip.
The application discloses a manufacturing method of a fast recovery chip, which comprises the following steps:
carrying out phosphorus diffusion on the silicon wafer by using a phosphorus source to form a phosphorus diffusion structural layer on at least one surface of the silicon wafer;
removing the phosphorus diffusion structure layer on one surface of the silicon wafer;
carrying out boron diffusion on the silicon wafer by using a boron source so as to form a boron diffusion structural layer on one surface of the silicon wafer, which is removed from the phosphorus diffusion structural layer;
polishing the surface of the boron diffusion structure layer to form a first polished surface;
performing platinum diffusion on the first polishing surface using a platinum source;
and preparing the fast recovery chip by adopting the silicon chip subjected to platinum diffusion.
Optionally, in the step of polishing the surface of the boron diffusion structure layer to form a first polished surface, the thickness of the polished silicon wafer is 3 to 5 micrometers smaller than the thickness of the silicon wafer before polishing.
Optionally, in the step of performing platinum diffusion on the first polishing surface by using a platinum source, the platinum source is a liquid platinum source, and the liquid platinum source is uniformly coated on the first polishing surface to perform platinum diffusion.
Optionally, in the step of performing platinum diffusion on the first polishing surface by using a platinum source, the temperature of the platinum diffusion is 800-950 ℃.
Optionally, in the step of removing the phosphorus diffusion structure layer on one side of the silicon wafer, the phosphorus diffusion structure layer on one side of the silicon wafer is removed by sand blasting.
Optionally, before the step of performing boron diffusion on the silicon wafer by using a boron source to form a boron diffusion structure layer on the side of the silicon wafer from which the phosphorus diffusion structure layer is removed, the method further includes:
polishing the surface of the silicon wafer, from which the phosphorus diffusion structure layer is removed, to form a second polished surface;
in the step of performing boron diffusion on the silicon wafer by using the boron source, a liquid boron source is coated on the second polishing surface to perform boron diffusion on the silicon wafer.
Optionally, during the step of diffusing platinum on the first polishing surface using a platinum source, nitrogen gas is introduced at a rate of 5-7 liters per minute.
Optionally, in the step of polishing the surface of the boron diffusion structure layer to form a first polished surface, the polished silicon wafer is cleaned.
The application also discloses a fast recovery chip, which comprises a phosphorus region, a base region and a boron region, wherein the phosphorus region is the cathode of the fast recovery chip; the base region is arranged on the phosphorus region; the boron region is arranged on the base region and is an anode of the fast recovery chip; and a polishing surface is formed on one surface of the boron region, which is far away from the base region, the fast recovery chip comprises platinum atoms, and the platinum atoms are uniformly distributed in the phosphorus region, the base region and the boron region.
The application also discloses a manufacturing device of the fast recovery chip, which comprises a plurality of different diffusion devices and polishing devices; the different diffusion devices respectively realize phosphorus diffusion, boron diffusion and platinum diffusion of the silicon wafer; the polishing device is used for polishing the silicon wafer subjected to boron diffusion; the manufacturing equipment of the fast recovery chip uses any one of the manufacturing methods of the fast recovery chip to manufacture the fast recovery chip.
This application is because the polishing surface is smooth to the silicon chip that has carried out phosphorus diffusion and boron diffusion earlier before platinum diffusion, when carrying out platinum diffusion, platinum can diffuse to the silicon chip uniformly in, prevents that platinum diffusion is inhomogeneous and destroys other structures in the silicon chip, and platinum has splendid turn-on speed simultaneously, thereby has improved the recovery characteristic of fast recovery chip.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic flowchart illustrating a method for manufacturing a fast recovery chip according to an embodiment of the present disclosure;
FIG. 2 is a cross-sectional view of a fast recovery chip according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a manufacturing apparatus for a fast recovery chip according to an embodiment of the present disclosure.
Wherein, 100, fast recovery chip; 110. a first polishing surface; 120. a boron region; 130. a base region; 140. a phosphorus region; 200. a manufacturing device; 210. a diffusion device; 211. a phosphorus diffusion device; 212. a boron diffusion device; 213. a platinum diffusion device; 220. provided is a polishing device.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application will now be described in detail with reference to the drawings and alternative embodiments, it being understood that any combination of the various embodiments or technical features described below may form new embodiments without conflict.
As shown in fig. 1, as an embodiment of the present application, a method for manufacturing a fast recovery chip is disclosed, which includes the steps of:
s1: carrying out phosphorus diffusion on the silicon wafer by using a phosphorus source to form a phosphorus diffusion structural layer on at least one surface of the silicon wafer;
s2: removing the phosphorus diffusion structure layer on one surface of the silicon wafer;
s3: carrying out boron diffusion on the silicon wafer by using a boron source so as to form a boron diffusion structural layer on one surface of the silicon wafer, which is removed from the phosphorus diffusion structural layer;
s4: polishing the surface of the boron diffusion structure layer to form a first polished surface;
s5: performing platinum diffusion on the first polishing surface using a platinum source;
s6: and preparing the fast recovery chip by adopting the silicon chip subjected to platinum diffusion.
Before platinum diffusion, it is right the surface of boron diffusion structural layer polishes the processing, make the one side of waiting to carry out platinum diffusion more smooth, so when platinum diffusion, because the first polishing surface that forms after the polishing is smooth to make can be even when platinum diffuses, thereby make platinum atom evenly distributed to resume the chip soon in, prevent that the maldistribution from causing the destruction of other structures in the chip that resumes soon, simultaneously because platinum has good electric conductive property, platinum evenly distributed makes the chip that resumes soon have better recovery characteristic.
Taking a 200V SF50mil product as an example, the recovery characteristics of unpolished and polished products are measured, wherein TRR is the reverse recovery time of the diode, the current can reversely flow through the diode in the process of forward conduction to reverse blocking, the time required by internal carrier recombination is TRR, the TRR value is generally referenced to a standard of 30-35, and the more concentrated the TRR value in the standard range is, the better the recovery characteristics are, namely the discreteness small recovery characteristic is high, and after polishing is carried out, the TRR value is obviously better than the TRR value of unpolished, and the following table refers specifically:
| take 200V SF50mil product as an example | TRR |
| Normal abrasive sheet (unpolished) | 29-35 |
| Experimental polishing pad (polishing) | 30-32 |
Watch 1
Specifically, in step S1, the phosphorus source refers to a phosphorus material used as a diffusion source, and phosphorus diffusion is performed on the silicon wafer by using the phosphorus source, which may specifically be: and (3) putting the phosphorus source and the silicon wafer into a diffusion furnace for diffusion reaction. Usually, a phosphorus paper source is selected as a phosphorus material, a piece of phosphorus paper source is added between two silicon wafers, phosphorus in the phosphorus paper source is diffused to the upper and lower silicon wafers, and after the phosphorus diffusion is carried out on the silicon wafers, a phosphorus diffusion structure layer is formed on one surface, which is in contact with the phosphorus paper source, in each silicon wafer. The phosphorus diffusion structure layer is a layer of structure with a phosphorus diffusion junction, the thickness of the silicon wafer before and after phosphorus diffusion is kept the original silicon wafer thickness, and the original silicon wafer thickness range is 245-255 um.
In some embodiments, prior to step S1, the method may further include: and (4) performing decontamination treatment on the surface of the silicon wafer. The decontamination treatment may be, for example: and (3) pickling and cleaning the silicon wafer to remove dirt, an oxide layer and the like on the surface of the silicon wafer.
In step S2, the step of removing the phosphorus diffusion structure layer on one side of the silicon wafer may specifically be: and removing the phosphorus diffusion structure layer on one surface of the silicon wafer in a sand blasting way, and controlling the thickness of the silicon wafer to be 235-245 microns, wherein the thickness of the silicon wafer before sand blasting is 245-255, the thickness of the silicon wafer can be reduced by about 10 microns by sand blasting, the effect of subsequent platinum ion diffusion is prevented from being influenced by too thick thickness of the silicon wafer, and in addition, the next step is carried out after removing the phosphorus diffusion junction and the phosphorus diffusion source in the phosphorus diffusion structure layer by sand blasting, the influence of the phosphorus diffusion junction on polishing is prevented, and the junction depth and the thickness change of the boron junction caused by the residual phosphorus diffusion source are prevented.
In step S3, the boron source refers to a boron material used as a diffusion source, and the boron source may be a liquid boron source. The method for carrying out boron diffusion on the silicon wafer by using the boron source specifically comprises the following steps: and coating a liquid boron source on one surface of the silicon wafer with the phosphorus removal diffusion structure layer, and putting the silicon wafer into a diffusion furnace for diffusion reaction. And after boron diffusion is carried out on the silicon wafer, a boron diffusion structural layer is formed on one surface of the silicon wafer, which is removed from the phosphorus diffusion structural layer. The boron diffusion structure layer is a layer of structure formed by diffusing boron diffusion junctions on the silicon wafer and is adjacent to the phosphorus diffusion layer structure.
In some embodiments, before step S3, the method may further include: and polishing the surface of the silicon wafer, from which the phosphorus diffusion structure layer is removed, so as to form a second polished surface. Namely, polishing the surface of the silicon wafer with the phosphorus diffusion structure layer removed before boron diffusion. Step S3 may specifically be: and coating a liquid boron source on the second polishing surface, and performing boron diffusion on the silicon wafer to form a boron diffusion structural layer on the second polishing surface. By forming the second polishing surface, the distribution of the boron source on the silicon wafer is more uniform, the boron diffusion is more uniform, and the yield of the product is improved. Of course, in some other embodiments, the silicon wafer may also be polished before step S1, and the polishing is performed on the premise that the silicon wafer is not damaged, so that the surface of the silicon wafer contacting with the phosphorus is smoother, and the phosphorus diffusion is more uniform.
In step S4, a surface of the boron diffusion structure layer is subjected to a polishing process to form a first polished surface. In addition, in this embodiment, the thickness of the polished silicon wafer is reduced by 3 to 5 micrometers relative to the thickness of the silicon wafer before polishing, and if the thickness of the polished silicon wafer is reduced by less than 3 micrometers or more than 5 micrometers, the thickness cannot reach the standard; for example, if the thinning thickness is too large, platinum ions can directly diffuse through the silicon wafer, so that the whole silicon wafer is completely scrapped. The polishing thickness is denoted by X, and controlling the polishing thickness can further improve the recovery characteristics, specifically referring to table two below:
watch two
In step S5, the platinum source is a liquid platinum source, and platinum diffusion is performed on the first polishing surface by using the platinum source, which specifically includes: the liquid platinum source is uniformly coated on the first polishing surface to perform platinum diffusion, so that the liquid platinum source can be more uniformly coated on the polishing surface, and the platinum diffusion can be more uniform after the liquid platinum source is uniformly coated. The diffusion temperature of platinum diffusion is controlled to be 800-950 ℃, if the temperature is too high, a boron junction is deeper, the whole structure of the silicon wafer is influenced, and if the temperature is too low, the surface concentration is changed, the change of a TRR value is influenced, and the recovery characteristic is influenced.
In step S5, the method may further include: and introducing nitrogen at the rate of 5-7L/min during platinum diffusion, wherein the nitrogen is pure nitrogen to prevent other gases from entering and influencing the diffusion uniformity.
In step S6, a fast recovery chip is prepared by using a silicon wafer after platinum diffusion, which may specifically be: and etching, sintering, coating and the like are carried out on the silicon wafer subjected to platinum diffusion to prepare the fast recovery chip. The fast recovery chip prepared by the silicon wafer after platinum diffusion can be a fast recovery diode and the like.
In the embodiment, the surface for platinum diffusion is polished and then coated with the liquid platinum source, so that the liquid platinum source can be more uniformly distributed on the surface for platinum diffusion, and the diffusion can be more uniform. However, because the polishing cost is too high and the platinum is not used excessively, researches show that the internal structure of the silicon wafer is greatly influenced by the non-uniform platinum diffusion, and the internal structure is damaged when the platinum is not uniform, the polishing treatment is carried out before the platinum is diffused so as to prevent the internal structure of the silicon wafer from being damaged by the non-uniform platinum diffusion, and meanwhile, the rapid recovery diode has an outstanding effect on the recovery characteristic of the rapid recovery diode after the platinum is uniformly diffused.
In some other embodiments, in step S5, the platinum source may also be platinum ions, and the platinum diffusion on the first polishing surface using the platinum source may further include: platinum ions are implanted onto the first polished face to perform platinum diffusion. Platinum ion implantation is performed at the first polished surface so that platinum can be more uniformly diffused into the silicon wafer when platinum diffusion is performed. The platinum diffusion can be carried out within a preset temperature range, platinum ions are uniformly diffused to each region of the silicon wafer, other structures in the silicon wafer are prevented from being damaged due to the fact that the platinum ions are not uniformly diffused, meanwhile, the platinum has extremely high conduction speed, the original structure of the silicon wafer is prevented from being damaged due to the fact that the platinum is not uniformly distributed, and meanwhile, the recovery characteristic of the chip can be improved.
Typically, the implantation dose of the platinum ions is 2e15cm2To 4e15cm2The implantation energy of the platinum ions is 50KeV to 70KeV, the implantation depth of the platinum ions is 2-4 micrometers, the depth is strictly controlled, the platinum ions are prevented from being expanded through a silicon wafer due to over-deep implantation, and specific ion implantation is carried outThe recovery characteristics of the depth-of-penetration versus fast recovery chip are referred to the following table three, where H is the platinum ion implantation depth:
watch III
In this embodiment, by polishing the surface for platinum diffusion and then performing platinum ion implantation, platinum ions can be more uniformly implanted into the surface for platinum diffusion, and thus, the surface for platinum diffusion can be more uniform when being diffused.
As another embodiment of the present application, a method of manufacturing a fast recovery chip is disclosed, including the steps of:
(1) treating the surface of a primary silicon wafer, and immersing the primary silicon wafer into hydrofluoric acid for acid cleaning;
(2) stacking the processed silicon wafer and the phosphorus paper source together, and placing the silicon wafer and the phosphorus paper source together in a diffusion furnace for phosphorus diffusion after arrangement;
(3) putting the silicon wafer from which phosphorus is diffused into hydrofluoric acid for slicing treatment and cleaning treatment;
(4) carrying out sand blasting treatment on the silicon wafer after the phosphorus fragmentation to remove phosphorus diffusion junctions and controlling the thickness of the silicon wafer to be 235-245 um;
(5) cleaning the material subjected to sand blasting, then performing boron diffusion, coating a liquid boron source on a sand blasting removal surface, and performing diffusion to form a boron junction;
(6) and (3) polishing the surface of the boron zone surface of the boron-expanded material to be about 3-5um, and cleaning after polishing.
(7) Coating a liquid platinum source on the polished silicon wafer, uniformly coating the platinum source on the polished surface, and performing platinum diffusion after coating, wherein the temperature is controlled at 800-950 ℃.
(8) After platinum diffusion, the silicon wafer is cleaned, coated with photoresist, exposed and developed, and then etched by mixed acid at the temperature of-5-1 ℃ to form a groove.
(9) After the trench was opened, the chip was subjected to RCA cleaning, and then LPCVD was performed to form a SIPOS film (semi-insulating polysilicon film) on the surface.
(10) And (4) coating photoresist glass after SIPOS, and carrying out glass sintering after exposure and development.
(11) LTO (low temperature oxidation) is performed after glass sintering, and a silicon dioxide film is grown.
(12) And (4) removing the oxidation layer on the table top of the chip after the step (11) through gluing, exposing and developing.
(13) And (4) carrying out primary nickel plating on the chip in the step (12), sintering, carrying out secondary nickel plating and then carrying out gold plating treatment.
(14) And cutting the gold-plated chip into single crystal grains by using a laser cutting machine.
(15) The grains are cleaned and then packaged.
Wherein, in the step (1), the surface smut, oxide layer and the like of the original silicon wafer are mainly removed, in the step (2), when phosphorus is diffused, the temperature range is 1150-; during boron diffusion, namely in the step (5), introducing oxygen 12LPM and nitrogen 3LPM at the temperature of 1200-1300 ℃ according to the ratio of 4: 1; the surface polishing treatment is added after the boron is expanded, so that the surface is smoother, a platinum source can be more uniformly tiled to polish the surface in the platinum coating process, the TRR value of the whole silicon wafer is more uniform finally, and the discreteness is small.
In the step (7), the platinum material is a liquid platinum source, the liquid platinum source is uniformly coated on the polishing surface to diffuse platinum, the liquid platinum source is required to diffuse, the liquid platinum source can be more uniformly coated on the polishing surface, and the platinum can be more uniformly diffused after the liquid platinum source is uniformly coated on the polishing surface; and the diffusion temperature in the step (7) is controlled at 800-950 ℃, the requirement on the temperature during platinum diffusion is higher, if the temperature is too high, a boron junction is deeper, the whole structure of the silicon wafer is influenced, and if the temperature is too low, the surface concentration is changed, the change of a TRR value is influenced, and the recovery characteristic is influenced.
In the step (8), the mixed acid comprises the following components in a ratio of 9: 9: 12: 7 nitric acid, hydrofluoric acid, acetic acid and sulfuric acid.
As another embodiment of the present application, a method of manufacturing a fast recovery chip is disclosed, including the steps of:
(1) treating the surface of a primary silicon wafer, and immersing the primary silicon wafer into hydrofluoric acid for acid cleaning;
(2) stacking the processed silicon wafer and the phosphorus paper source together, and placing the silicon wafer and the phosphorus paper source together in a diffusion furnace for phosphorus diffusion after arrangement;
(3) putting the silicon wafer from which phosphorus is diffused into hydrofluoric acid for slicing treatment and cleaning treatment;
(4) carrying out sand blasting treatment on the silicon wafer after the phosphorus fragmentation to remove phosphorus diffusion junctions and controlling the thickness of the silicon wafer to be 235-245 um;
(5) cleaning the material after sand blasting, adding a gallium material, and performing gallium diffusion;
(6) adding boron material, then carrying out boron diffusion, coating a liquid boron source on the sand blasting removal surface, and diffusing to form boron junctions;
(7) and (3) polishing the surface of the boron zone surface of the boron-expanded material to be about 3-5um, and cleaning after polishing.
(8) And (3) performing platinum ion implantation on the polished silicon wafer, wherein the depth of the implanted platinum ions is 2-4 microns, performing platinum deep diffusion after the platinum ions are implanted, and controlling the temperature at 800-950 ℃.
(9) After platinum diffusion, the silicon wafer is cleaned, coated with photoresist, exposed and developed, and then etched by mixed acid at the temperature of-5-1 ℃ to form a groove.
(10) After the trench was opened, the chip was subjected to RCA cleaning, and then LPCVD was performed to form a SIPOS film (semi-insulating polysilicon film) on the surface.
(11) And (4) coating photoresist glass after SIPOS, and carrying out glass sintering after exposure and development.
(12) LTO (low temperature oxidation) is performed after glass sintering, and a silicon dioxide film is grown.
(13) And (4) removing the oxidation layer on the table top of the chip after the step (11) through gluing, exposing and developing.
(14) And (4) carrying out primary nickel plating on the chip in the step (12), sintering, carrying out secondary nickel plating and then carrying out gold plating treatment.
(15) And cutting the gold-plated chip into single crystal grains by using a laser cutting machine.
(16) The grains are cleaned and then packaged.
Wherein, before the gallium diffusion or the boron diffusion, the polishing treatment can be carried out so as to lead the diffusion to be more uniform; the platinum deep diffusion means that platinum ions can be diffused to deeper positions of the silicon wafer after ion implantation, so that platinum atoms can be uniformly distributed in each region of the silicon wafer.
In all the embodiments, the gallium diffusion and the boron diffusion can be performed simultaneously, and the gallium material and the boron material are added into the same diffusion furnace at the same time, so that the time of the manufacturing method can be saved, the production efficiency can be improved, and the PN junction can be formed more smoothly by performing the diffusion at the same time.
As shown in fig. 2, as another embodiment of the present application, a fast recovery chip 100 is disclosed, which includes an SF chip including a phosphorus region 140, a base region 130, and a boron region 120, where the phosphorus region 140 is a cathode of the fast recovery chip; the base region 130 is disposed on the phosphor region; the boron region 120 is arranged on the base region and is an anode of the fast recovery chip; a first polishing surface 110 is formed on one surface of the boron region far away from the base region, the fast recovery chip comprises platinum atoms, and the platinum atoms are uniformly distributed in the phosphorus region, the base region and the boron region after being diffused from the polishing surface.
The first polishing surface is formed before platinum diffusion, so that the platinum can be more uniformly diffused into the silicon wafer during the platinum diffusion, the TRR value is more uniform, and a fast recovery chip with good recovery characteristics is obtained.
And a platinum ion injection area is also formed on the first polishing surface, the depth of the injected platinum ions is 2-4 microns, and the platinum diffusion is carried out after the platinum ions are injected, so that the platinum diffusion uniformity is further improved.
As shown in fig. 3, as another embodiment of the present application, there is disclosed a manufacturing apparatus 200 of a fast recovery chip, including a plurality of different diffusion devices 210 and polishing devices 220; the plurality of different diffusion devices 210 respectively realize phosphorus diffusion, boron diffusion and platinum diffusion of the silicon wafer; the polishing device is used for polishing the silicon wafer subjected to boron diffusion; wherein, the manufacturing equipment of the fast recovery chip uses the manufacturing method in any one of the above embodiments to manufacture the fast recovery chip.
The phosphorus diffusion, the boron diffusion and the platinum diffusion are carried out in different diffusion furnaces, each diffusion is carried out in an independent diffusion furnace to prevent mutual pollution, particularly, products with a boron source coming out of the diffusion furnace are wasted during phosphorus diffusion, so that diffusion cannot be carried out in the same diffusion furnace, the diffusion devices 210 are a phosphorus diffusion device 211 for phosphorus diffusion, a boron diffusion device 212 for boron diffusion and a platinum diffusion device 213 for platinum diffusion, and the diffusion devices are independent to prevent cross pollution caused by the fact that one diffusion device is shared, and the production yield of the products is influenced.
The manufacturing equipment further comprises an ion implanter, and after boron diffusion, platinum ion implantation is carried out on the silicon wafer with the surface being a boron junction by the ion implanter, and platinum diffusion is carried out.
Furthermore, the manufacturing equipment of the fast recovery chip also comprises a diffusion device for realizing gallium diffusion, the phosphorus diffusion, the gallium diffusion, the boron diffusion and the platinum diffusion are carried out in different diffusion furnaces, each diffusion is carried out in a separate diffusion furnace to prevent mutual pollution, and particularly, products with boron sources coming out from the inside are wasted during the phosphorus diffusion, so the diffusion cannot be carried out in the same diffusion furnace.
The gallium diffusion device for gallium diffusion is independent from each diffusion device, so that cross contamination caused by one diffusion device is prevented from being shared, the production yield of products is prevented from being influenced, generally, gallium diffusion is carried out before boron diffusion, the junction depth formed by the gallium diffusion device is far more gentle than that formed by direct boron diffusion, the voltage discreteness and surge capacity of the existing fast recovery diode product are improved, and the voltage drop characteristic of the fast recovery diode is improved.
Of course, the gallium diffusion and the boron diffusion can be carried out in a single diffusion furnace without cross-contamination with each other.
It should be noted that, the limitations of each step in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present application.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. A method for manufacturing a fast recovery chip, comprising the steps of:
carrying out phosphorus diffusion on the silicon wafer by using a phosphorus source to form a phosphorus diffusion structural layer on at least one surface of the silicon wafer;
removing the phosphorus diffusion structure layer on one surface of the silicon wafer;
carrying out boron diffusion on the silicon wafer by using a boron source so as to form a boron diffusion structural layer on one surface of the silicon wafer, which is removed from the phosphorus diffusion structural layer;
polishing the surface of the boron diffusion structure layer to form a first polished surface;
performing platinum diffusion on the first polishing surface using a platinum source;
and preparing the fast recovery chip by adopting the silicon chip subjected to platinum diffusion.
2. The method for manufacturing a fast recovery chip as claimed in claim 1, wherein in the step of polishing the surface of the boron diffusion structure layer to form the first polished surface, the thickness of the silicon wafer after polishing is 3 to 5 μm smaller than the thickness of the silicon wafer before polishing.
3. The method of claim 2, wherein in the step of diffusing platinum on the first polishing surface using a platinum source, the platinum source is a liquid platinum source that is uniformly applied to the first polishing surface for platinum diffusion.
4. The method as claimed in claim 3, wherein the platinum diffusion temperature is about 800-950 ℃ in the step of performing platinum diffusion on the first polishing surface by using a platinum source.
5. The method for manufacturing a fast recovery chip as claimed in claim 1, wherein in the step of removing the phosphorus diffusion structure layer on one side of the silicon wafer, the phosphorus diffusion structure layer on one side of the silicon wafer is removed by sand blasting.
6. The method of manufacturing a fast recovery chip as claimed in claim 1,
before the step of performing boron diffusion on the silicon wafer by using a boron source to form a boron diffusion structural layer on one side of the silicon wafer, on which the phosphorus diffusion structural layer is removed, the method further comprises the following steps:
polishing the surface of the silicon wafer, from which the phosphorus diffusion structure layer is removed, to form a second polished surface;
in the step of performing boron diffusion on the silicon wafer by using the boron source, a liquid boron source is coated on the second polishing surface to perform boron diffusion on the silicon wafer.
7. The method of claim 1, wherein during the step of diffusing platinum on the first polishing surface using a platinum source, nitrogen gas is introduced at a rate of 5-7 liters per minute.
8. The method for manufacturing a fast recovery chip as claimed in any one of claims 1 to 7, wherein in the step of polishing the surface of the boron diffusion structure layer to form the first polished surface, the silicon wafer after polishing is cleaned.
9. A fast recovery chip, comprising:
the phosphorus region is the cathode of the fast recovery chip;
a base region disposed on the phosphorus region;
the boron region is arranged on the base region and is an anode of the fast recovery chip;
and a polishing surface is formed on one surface of the boron region, which is far away from the base region, the fast recovery chip comprises platinum atoms, and the platinum atoms are uniformly distributed in the phosphorus region, the base region and the boron region.
10. An apparatus for manufacturing a fast recovery chip, comprising:
the different diffusion devices are used for respectively realizing phosphorus diffusion, boron diffusion and platinum diffusion of the silicon wafer;
the polishing device is used for polishing the silicon wafer subjected to boron diffusion;
wherein the manufacturing equipment of the fast recovery chip uses the manufacturing method of the fast recovery chip of any one of claims 1 to 8 to manufacture the fast recovery chip.
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