CN105355552A - Preparation method of fast recovery diode - Google Patents
Preparation method of fast recovery diode Download PDFInfo
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- CN105355552A CN105355552A CN201510737934.8A CN201510737934A CN105355552A CN 105355552 A CN105355552 A CN 105355552A CN 201510737934 A CN201510737934 A CN 201510737934A CN 105355552 A CN105355552 A CN 105355552A
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- 238000011084 recovery Methods 0.000 title claims abstract description 31
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 141
- 239000010703 silicon Substances 0.000 claims abstract description 141
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 141
- 238000000034 method Methods 0.000 claims abstract description 63
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 53
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 53
- 239000012535 impurity Substances 0.000 claims abstract description 34
- 238000009792 diffusion process Methods 0.000 claims abstract description 26
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 23
- 239000011574 phosphorus Substances 0.000 claims abstract description 23
- 229910052796 boron Inorganic materials 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 17
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000005516 engineering process Methods 0.000 claims abstract description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 13
- 230000003647 oxidation Effects 0.000 claims abstract description 13
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 13
- 238000001704 evaporation Methods 0.000 claims abstract description 12
- 230000008021 deposition Effects 0.000 claims abstract description 11
- 238000005275 alloying Methods 0.000 claims abstract description 10
- 238000000227 grinding Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 238000000465 moulding Methods 0.000 claims abstract description 9
- 238000005498 polishing Methods 0.000 claims abstract description 8
- 238000000605 extraction Methods 0.000 claims abstract description 6
- 239000004411 aluminium Substances 0.000 claims description 50
- 239000010410 layer Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- YBJHBAHKTGYVGT-ZKWXMUAHSA-N (+)-Biotin Chemical compound N1C(=O)N[C@@H]2[C@H](CCCCC(=O)O)SC[C@@H]21 YBJHBAHKTGYVGT-ZKWXMUAHSA-N 0.000 claims description 15
- FEPMHVLSLDOMQC-UHFFFAOYSA-N virginiamycin-S1 Natural products CC1OC(=O)C(C=2C=CC=CC=2)NC(=O)C2CC(=O)CCN2C(=O)C(CC=2C=CC=CC=2)N(C)C(=O)C2CCCN2C(=O)C(CC)NC(=O)C1NC(=O)C1=NC=CC=C1O FEPMHVLSLDOMQC-UHFFFAOYSA-N 0.000 claims description 15
- 238000003475 lamination Methods 0.000 claims description 14
- 229910052709 silver Inorganic materials 0.000 claims description 12
- 230000008020 evaporation Effects 0.000 claims description 11
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 238000012360 testing method Methods 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 239000007795 chemical reaction product Substances 0.000 claims description 7
- 239000002775 capsule Substances 0.000 claims description 6
- 238000013461 design Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims description 4
- 239000011265 semifinished product Substances 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000002788 crimping Methods 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 abstract 1
- 239000011733 molybdenum Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 15
- 230000000052 comparative effect Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 238000013021 overheating Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 206010017577 Gait disturbance Diseases 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000009514 concussion Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
Abstract
The invention relates to a preparation method of a fast recovery diode matched with an integrated gate commutated thyristor in use. The preparation method comprises the steps of: 1) polishing an arbitrary surface of an N type silicon wafer; 2) carrying out aluminum pre-deposition, performing boron ion implantation on the polished surface of the silicon wafer, and carrying out oxidation propelling technology, so that a P+PNP type longitudinal structure is formed in the silicon wafer; 3) grinding the unpolished surface of the silicon wafer, so that a P+PN type longitudinal structure is formed in the silicon wafer; 4) conducting phosphorus impurity doping diffusion on an N type side of the silicon wafer, so that a P+PNN+ type longitudinal structure is formed in the silicon wafer; 5) evaporating an aluminum layer on the surface of the silicon wafer to form an extraction electrode, and carrying out an alloying process to form ohmic contact between aluminum and silicon; 6) carrying out proton irradiation on a chip anode surface; 7) bonding the chip anode surface with a molybdenum plate; 8) performing molding and protection processing; 9) and carrying out electron irradiation.
Description
Technical field
The present invention relates to a kind of preparation method of industrial component, particularly relate to a kind of preparation method of diode.
Background technology
In practical application, IGCT (IntegratedGateCommutatedThyristor, integrated gate commutated thyristor) supporting FRD (FastRecoveryDiode, fast recovery diode) needs to bear higher forward current rate of descent-di
f/ dt (generally can reach-500 ~-5000A/ μ s), possess quick turn-off capacity, trr reverse recovery time short (being generally 2 ~ 10 μ s) and softer reverse recovery characteristic (softness factor S>=0.8).Although market exists the supporting FRD of a variety of IGBT, its rated voltage and rated current are all less than normal, cannot meet the application demand of IGCT; And although the rated voltage of the supporting FRD of high speed thyristor, rated current can meet the application demand of IGCT, its forward current rate of descent-di
f/ dt ability to bear is low and the softness factor is too small, very easily damages when supporting the use with IGCT, and the inefficacy of FRD can cause the IGCT in circuit to damage, and therefore, can not meet the application demand of IGCT.The matched FRD overwhelming majority of IGCT is total head direct type FRD, but along with applied power grade more and more higher, operating mode is harsher, the reliability of total head direct type FRD sharply reduces, very easily lost efficacy, and seriously reduced the reliability of current transformer, fail safe, add maintenance cost.
The chip of fast recovery diode (FRD) generally adopts PIN type structure.Because base is thin, QRR is few, not only substantially reduces trr value, reduces forward voltage drop V
fM, and higher reverse voltage V can be born
rRM.FRD also has some other structure, as PINN
+, be PIN and derived structure thereof substantially.
The supporting fast recovery diode of IGCT on market, the overwhelming majority all adopts total head direct type structure, there is following shortcoming in total head direct type fast recovery diode (FRD): due to structural limitations, the heat-sinking capability of device is limited, in reversely restoring process, easily cause chip local overheating, cause chip failure, when the power of application circuit constantly increases, the failure rate of total head direct type FRD sharply increases; Total head direct type FRD generally imposes the electron irradiation of larger dose to reduce the reverse recovery loss of device, but the softness factor S of FRD can be caused to reduce, as forward current rate of descent-di
fwhen/dt is larger, in reversely restoring process, easily there is concussion and then lost efficacy in device; When improving the softness factor S of device, the reverse recovery loss of device can be caused to increase, above-mentioned parameter is considered in compromise, softness factor S cannot be brought up to greater value, thus cause the Reverse recovery crest voltage V of device
rMexcessive, easily cause device breakdown.
Summary of the invention
In order to solve above-mentioned problems of the prior art, the invention provides the manufacture method of the supporting low-temperature bonding fast recovery diode of a kind of brand-new IGCT, this FRD (low-temperature bonding type FRD) adopts anode linkage technique, compared with total head direct type FRD, FRD involved in the present invention has stronger heat-sinking capability, local overheating can not be there is damage, thus improve the working junction temperature of device, can be applied in more high-power circuit; The enhancing of heat-sinking capability, enables device bear larger reverse recovery loss, therefore, in order to try the softness factor S of device can be brought up to greater value, identical forward current rate of descent-di
funder/dt effect, the Reverse recovery crest voltage V of this device
rMless, enable to bear larger forward current rate of descent-di
f/ dt.Under same application condition, FRD involved in the present invention has higher reliability, and can be applied in the more harsh application of condition and not lose efficacy, its heat-sinking capability unit area current density that is stronger, that can bear is larger, working junction temperature is higher, forward current rate of descent-di
f/ dt ability to bear is stronger, reverse recovery characteristic is softer, can meet the supporting application demand of IGTC in more than 10MW current transformer, and in application, its reliability is far above total head direct type FRD.
One object of the present invention is, provides the preparation method of the supporting fast recovery diode of a kind of integrated gate commutated thyristor, comprises the steps:
1) carry out polishing to any one side of N-type silicon wafer, the burnishing surface of described N-type silicon wafer is chip anode face;
2) carry out aluminium pre-deposition, before or after carrying out aluminium pre-deposition, carry out boron ion implantation at the burnishing surface of described silicon wafer, and carry out oxidation propelling technique, make to form P in silicon wafer
+positive-negative-positive vertical structure;
3) grind the non-burnishing surface of described silicon wafer, described silicon wafer is thinned to default thickness, make silicon wafer inside form P
+pN type vertical structure;
4) carry out phosphorus impurities doping diffusion in the N-type side of described silicon wafer, make silicon wafer inside form P
+pNN
+type vertical structure;
5) at described silicon wafer surface evaporation aluminium lamination, form extraction electrode, after described silicon wafer surface evaporation aluminium lamination, carry out alloying technology, make to form ohmic contact between aluminium, silicon;
6) proton irradiation is carried out in chip anode face, to regulate the softness factor S of minority carrier life time and/or chip;
7) under uniform temperature, pressure, together with being bonded to molybdenum sheet in chip anode face, chip semi-finished product are obtained;
8) to step 7) obtained chip semi-finished product carry out moulding, preferably carry out the moulding of knot terminal, more preferably carry out table top moulding, and carry out conservation treatment, form complete chip;
9) to step 8) obtained complete chip carries out electron irradiation, obtains chip end-product.
On the one hand, present invention employs the proton irradiation technique of anode-side.
IGCT requires it is not only fast but also soft to the reverse recovery characteristic of supporting FRD, " soon " refers to that reverse recovery time trr is short, the length of trr is directly connected to switching loss and the operating frequency of device, and " soft " softness factor S when referring to Reverse recovery is greater than 0.8, otherwise in FRD reversely restoring process, the high dv/dt of easy generation and peak voltage, cause FRD and IGCT component failure.
Proton irradiation is the technology of shooting at the target after hydrogen atom ionization being accelerated, and can control the local minority carrier life-span of silicon wafer.Electron irradiation, for silicon wafer is placed in irradiation field, is bombarded by electronics, makes silicon wafer inside form complex centre, reaches the object controlling minority carrier life time.General FRD many employings electron irradiation, heavy metal doping process, the softness factor S of FRD after heavy metal doping or electron irradiation is generally less than 0.8.The present invention adopts proton irradiation technique, and the softness factor of the FRD after proton irradiation generally can be greater than 1.
The defect peak depth of proton irradiation changes with the change of irradiation energy, and the local minority carrier life time being easy to realize FRD device controls.By proton irradiation, chip minority carrier life time in a longitudinal direction can be made to be certain gradient distribution, instead of to be uniformly distributed, thus softness factor S when increasing device Reverse recovery.
When the region of proton irradiation is positioned at chip anode side, the most remarkable to the regulating action of FRD device softness, and required irradiation energy is less, reduces manufacturing cost while enabling device reach design parameter.Therefore, before chip anode low-temperature bonding technique, proton irradiation is carried out to chip, regulate the minority carrier life time of chip regional area, with the softness factor S of increased device.
On the other hand, present invention employs low-temperature bonding technique.
The supporting FRD of IGCT can produce high power loss in application process, and total head direct type FRD is by its structural limitations, and heat-sinking capability is limited, in application process, very easily causes device performance to decline because regional area is overheated, then loses efficacy.In order to reduce reverse recovery loss, total head direct type FRD needs the electron irradiation of larger dose usually, and its consequence the softness factor S of device cannot be adjusted to larger value, causes device easily to vibrate in reversely restoring process.The enhancing of low-temperature bonding type FRD heat-sinking capability, enables device bear larger reverse recovery loss, in order to try the softness factor S of device can be brought up to greater value, reaches the forward current rate of descent-di improving device
fthe object of/dt ability to bear.
Low-temperature bonding technique: under uniform temperature, pressure, together with being crimped onto chip anode face with the bonding face of molybdenum sheet.The voidage of this FRD bonded layer is zero, and the combination of anode molybdenum sheet and chip is more tight, has extremely strong heat-sinking capability, and chip does not exist local overheating phenomenon, and power loss is no longer the stumbling-block that its parameter is optimized further.In chip manufacturing, electron irradiation dosage can be reduced, with the softness factor S of further increased device, reduce the Reverse recovery crest voltage V of device
rM, and reduce the probability that vibration occurs device in reversely restoring process, thus improve the application reliability of device.
The flow process of a specific embodiment of the present invention as shown in Figure 1.
Of the present invention one preferred embodiment in, step 1) in the difference such as resistivity, thickness, diameter of selected N-type silicon wafer monocrystalline selected by the device of different voltage, current class.Of the present invention one preferred embodiment in, step 1) in selected N-type silicon wafer be the suitable N-type silicon wafer selected according to the device of different voltage, current class.Described N-type silicon wafer before polishing is preferably N-type silicon single crystal disk.
Of the present invention one preferred embodiment in, step 1) polishing is being carried out to any one side of N-type silicon wafer, the burnishing surface of described N-type silicon wafer is that chip anode face can for first to choose suitable N-type silicon wafer, and by any one side polishing of silicon wafer, burnishing surface is chip anode face, also can for directly to choose the N-type silicon wafer doing single-sided polishing process, burnishing surface is chip anode face.
Of the present invention one preferred embodiment in, step 2) described in aluminium pre-deposition for silicon wafer is loaded in source capsule, then source capsule is put into aluminium pre-deposition diffusion furnace, the doping of aluminium impurity is carried out to silicon wafer, until the aluminium impurity concentration on silicon wafer burnishing surface top layer reaches design load, and
Step 2) described in oxidation advance technique carry out in diffusion furnace.
Of the present invention one preferred embodiment in, step 2) described in boron ion implantation comprise the steps:
A) described silicon wafer is put into diffusion furnace and carry out oxidation technology, make described silicon wafer surface form SiO
2protective layer is to protect boron ion implantation face;
B) boron ion is injected at the burnishing surface of described silicon wafer.
In a concrete execution mode of the present invention, steps A) for silicon wafer is loaded in the source capsule of aluminium pre-deposition technique, then source capsule is put into aluminium pre-deposition diffusion furnace, the doping of aluminium impurity is carried out to silicon wafer, after technique terminates, detect the aluminium impurity concentration on silicon wafer burnishing surface top layer, if do not reach preset value, aforesaid operations must be repeated, until the aluminium impurity concentration on silicon wafer burnishing surface top layer reaches preset value, if the aluminium impurity concentration on silicon wafer burnishing surface top layer reaches preset value, then subsequent technique can be carried out.The preset value of described aluminium impurity concentration can be such as 10
15to 10
18cm
-3.
In a concrete execution mode of the present invention, described step B) comprise B1) preparation, B2) boron ion implantation and B3) boron aluminium impurity ties these steps of diffusion deeply.Step B1) be form thin SiO on silicon wafer surface
2protective layer is to protect boron ion implantation face (i.e. the burnishing surface of silicon wafer).Concrete, step B1) carry out oxidation technology for silicon wafer is put into diffusion furnace, make silicon wafer surface form SiO
2protective layer.Step B2) can be and inject boron ion at the burnishing surface of silicon wafer, inject deflection angle and dosage foundation design load and process conditions and determine.Step B3) can be and silicon wafer put into diffusion furnace and carry out oxidation and advance technique, make the boron in silicon wafer, aluminium impurity ties diffusion deeply, boron, aluminium junction depth are determined according to device voltage grade.
Of the present invention one preferred embodiment in, step 3) adopt one side grinding process to grind the non-burnishing surface of described silicon wafer, remove the aluminium impurity layer of the non-burnishing surface (cathode plane) of described silicon wafer, and described silicon wafer is thinned to default thickness, make silicon wafer inside form P
+pN type vertical structure.Described default thickness is required to determine by the electric pressure of device and forward voltage drop.
Of the present invention one preferred embodiment in, step 4) described in carry out in the N-type side of described silicon wafer phosphorus impurities doping diffusion comprise the steps:
I) described silicon wafer is put into diffusion furnace and carry out phosphorus pre-deposition technique, make the non-burnishing surface of described silicon wafer form the N-type impurity layer of high concentration, then remove the phosphorosilicate glass on described silicon wafer surface;
Ii) described silicon wafer being put into phosphorus advances diffusion furnace to carry out phosphorus impurities and deeply tie diffusion, makes phosphorus impurities diffuse to the default degree of depth, then removes the SiO on silicon wafer surface
2layer.Now, silicon wafer inside forms P
+pNN
+type vertical structure.
The N-type impurity layer of described high concentration is phosphorus impurities layer.
The described default degree of depth is such as 20-60 μm.
Of the present invention one preferred embodiment in, step 3) described grinding adopts one side grinding process to carry out, and step 5) described in evaporation aluminium lamination carry out in a vacuum.In a concrete execution mode of the present invention, step 5) carry out aluminium lamination evaporation for the silicon wafer after cleaning up is put into vacuum evaporator, form cathode and anode extraction electrode, then the silicon wafer having steamed aluminium is put into alloying furnace and carry out alloying, make to form ohmic contact between silicon, aluminium.
Of the present invention one preferred embodiment in, step 7) described under uniform temperature, pressure, specifically comprise the steps: together with chip anode face is bonded to molybdenum sheet
A) at chip anode face sputtering bonding metal layer;
B) at the bonding face sputtering bonding metal layer of molybdenum sheet, or single or double is directly selected to sputter the molybdenum sheet having bonding metal layer;
C) at molybdenum sheet bonding face crimping Ag films, under being crimped on the temperature of 100-200 DEG C preferably, carry out under the pressure of 0.3-2MPa;
D), together with chip anode face is crimped onto with the bonding face of molybdenum sheet, under being crimped on the temperature of 150-300 DEG C preferably, carry out under the pressure of 3-8MPa.
Step c) can see Fig. 2.Steps d) can see Fig. 3.
Of the present invention one preferred embodiment in, step a) described in bonding metal layer be any one in the following: Ag metal level, Ti, Ag metal level, Ni, Ag metal level, and Ti, Ni, Ag metal level;
Step b) described in bonding metal layer be any one in the following: Ag metal level, Ti, Ag metal level, Ni, Ag metal level, and Ti, Ni, Ag metal level.
Of the present invention one preferred embodiment in, in step 9) in electron irradiation is carried out to chip after also carry out chip testing, whether reach preset value with detection chip minority carrier life time and chip pressure drop; If do not reach preset value, then proceed electron irradiation until chip minority carrier life time and chip pressure drop reach preset value.Of the present invention one preferred embodiment in, the preset value of chip minority carrier life time can be such as 2-80 μ s, and the preset value of chip voltage can be such as 2-6V.Said chip pressure drop preset value is determined by chip voltage, current class.
Of the present invention one preferred embodiment in, described method also comprises the steps:
10) test of chip end-product is carried out to chip end-product, encapsulate and dispatch from the factory test in any one or multiple.
Of the present invention one preferred embodiment in, in step 5) at described silicon wafer surface evaporation aluminium lamination and/or before or after carrying out alloying technology, or in step 6) before or after also cyclotomy is carried out to described silicon wafer, described silicon wafer to be cut into the disk with preset diameters.Described preset diameters can be such as Φ 73mm, Φ 88mm, Φ 96mm etc.Above-mentioned preset value is determined by chip voltage, current class.
Of the present invention one preferred embodiment in, the present invention includes following steps:
1) any one side of N-type silicon wafer is carried out polishing, or directly select the N-type silicon wafer of single-sided polishing, burnishing surface is chip anode face;
2) carry out aluminium pre-deposition technique, carry out boron ion implantation at silicon wafer burnishing surface afterwards, and carry out oxidation propelling technique, make to form P in silicon wafer
+positive-negative-positive vertical structure;
3) adopt the non-burnishing surface of one side grinding process grinding silicon wafer, silicon wafer is thinned to design thickness, make silicon wafer inside form P
+pN type vertical structure;
4) carry out phosphorus impurities doping diffusion in the N-type side of silicon wafer, make silicon wafer inside form P
+pNN
+type vertical structure;
5) at silicon wafer surface evaporation aluminium lamination, form extraction electrode, and carry out alloying technology, make to form ohmic contact between aluminium, silicon;
6) proton irradiation is carried out to regulate minority carrier life time at chip anode face (burnishing surface);
7) under uniform temperature, pressure, together with chip anode face is bonded to molybdenum sheet;
8) table top moulding and protection technique;
9) electron irradiation;
10) chip end-product is tested, encapsulate and dispatch from the factory test.
Beneficial effect of the present invention is: the present invention has designed and developed a kind of manufacture method being applicable to the FRD device of the supporting application of IGCT, this type device adopts anode linkage technique, compared with total head direct type FRD: FRD involved in the present invention has stronger heat-sinking capability, local overheating can not be there is damage, thus improve the working junction temperature of device, can be applied in more high-power circuit; The enhancing of heat-sinking capability, enables device bear larger reverse recovery loss, therefore, in order to try the softness factor S of device can be brought up to greater value, identical forward current rate of descent-di
funder/dt effect, the Reverse recovery crest voltage V of this device
rMless, enable to bear larger forward current rate of descent-di
f/ dt.Under same application condition, FRD involved in the present invention has higher reliability, and can be applied in the more harsh application of condition and not lose efficacy.
Accompanying drawing explanation
Fig. 1 is the manufacturing process flow diagram of FRD of the present invention.
Fig. 2 is molybdenum sheet bonding face silverskin compression joint technique schematic diagram.
Fig. 3 is low-temperature bonding process schematic representation.
Fig. 4 is FRD Reverse recovery waveform schematic diagram.Wherein, I
fMfor diode peak on-state electric current ,-di
f/ dt is forward current rate of descent, I
rMfor inverse peak current, V
fMfor forward on state voltage, V
rfor reverse voltage, V
rMfor peak-inverse voltage, t
afor memory time, t
bfor recombination time, t
rrfor reverse recovery time, t
rr=t
a+ t
b, di
r (REC)/ dt is Reverse recovery di/dt, Q
rrfor QRR, S is the Reverse recovery softness factor, S=t
b/ t
a.
Embodiment
Below in conjunction with non-limiting specific embodiment, the invention will be further described, but protection scope of the present invention is not limited to following embodiment.
Embodiment 1:
Manufacture method of the present invention is adopted to manufacture the supporting FRD (ZK of IGCT
x2000-45).Comprise the steps:
1, the N-type silicon wafer that cut-off footpath is 76.2mm, thickness is 0.80mm, crystal orientation is <111>, resistivity is 260 Ω cm, carries out single-sided polishing process.
2, above-mentioned silicon wafer is after the standard RCA clean of semiconductor manufacturing industry, is placed in aluminium pre-deposition diffusion furnace and carries out aluminium pre-deposition technique, and after aluminium pre-deposition technique, the aluminium impurity concentration on silicon wafer burnishing surface top layer is 10
16cm
-3.
3, above-mentioned silicon wafer is after the standard RCA clean of semiconductor manufacturing industry, is placed in oxide-diffused stove and carries out oxidation technology, makes the SiO that silicon wafer burnishing surface formation 0.04 ± 0.01 μm is thick
2.
4, inject boron ion at the burnishing surface of above-mentioned silicon wafer, implantation dosage is 10
16cm
-2.
5, above-mentioned silicon wafer is after the standard RCA clean of semiconductor manufacturing industry, be placed in oxide-diffused stove and carry out oxidation propelling technique, after oxidation advances technique, the aluminium impurity junction depth of silicon wafer burnishing surface is 110 ± 10 μm, and the SiO that silicon wafer burnishing surface formation 2 ± 0.1 μm is thick
2, make to form P in silicon wafer
+positive-negative-positive vertical structure.
6, adopt the non-burnishing surface of one side grinding process grinding silicon chip, by silicon wafer reduced thickness to 0.6mm, make silicon wafer inside form P
+pN type vertical structure.
7, above-mentioned silicon wafer is after the standard RCA clean of semiconductor manufacturing industry, is placed in phosphorus impurities doping diffusion furnace and carries out phosphorus impurities doping process, makes silicon wafer inside form P
+pNN
+type vertical structure, after phosphorus impurities doping process, the phosphorus impurities concentration on the non-burnishing surface top layer of silicon wafer is 10
20cm
-3, silicon wafer surface can form certain thickness phosphorosilicate glass simultaneously.
8, above-mentioned silicon wafer is soaked hydrofluoric acid to remove the phosphorosilicate glass on silicon wafer surface.
9, above-mentioned silicon wafer is after the standard RCA clean of semiconductor manufacturing industry, be placed in phosphorus propelling diffusion furnace and carry out phosphorus propelling technique, after phosphorus advances technique, the junction depth of the phosphorus impurities of the non-burnishing surface of silicon wafer is 40 ± 5 μm, the junction depth of the aluminium impurity of silicon wafer burnishing surface is 120 ± 10 μm, and silicon wafer surface can form certain thickness SiO simultaneously
2.
10, above-mentioned silicon wafer is soaked hydrofluoric acid to remove the SiO on silicon wafer surface
2.
11, above-mentioned silicon wafer is after the standard RCA clean of semiconductor manufacturing industry, is placed in aluminium lamination vapourizing furnace and carries out aluminium lamination evaporation technology, makes the burnishing surface of silicon wafer, non-burnishing surface all forms the thick aluminium lamination of 15 ± 2um, forms extraction electrode.
12, above-mentioned silicon wafer is placed in alloying furnace carries out alloying technology, make to form ohmic contact between aluminium, silicon.
13, by above-mentioned silicon wafer cyclotomy to diameter 73mm.
14, proton irradiation technique: the burnishing surface (i.e. the anode surface of chip) of above-mentioned silicon wafer is carried out proton irradiation technique, and irradiation dose is 10
13cm
-2.
15, low-temperature bonding technique:
1) silver metal layer that sputtering 3 μm is thick on the aluminium lamination of above-mentioned silicon wafer burnishing surface.
2) at the bonding face crimping Ag films of molybdenum sheet, technological temperature is 150 DEG C, and pressure is 1MPa, and the process time is 5 minutes.
3), together with being crimped onto with the bonding face of molybdenum sheet by the bonding face of silicon wafer, technological temperature is 250 DEG C, and pressure is 6MPa, and the process time is 10 minutes.
16, angle lap, makes the formation oblique angle moulding of silicon wafer edge, and corrodes above-mentioned inclination surface, then carries out table top protection technique, forms ZK
x2000-45 chip.
17, to above-mentioned ZK
x2000-45 chip carries out Electron irradiation technology, and control the minority carrier life time of chip at 10-50 μ s, pressure drop controls at 2.3-2.6V.
18, by above-mentioned ZK
x2000-45 chip package, in shell, forms complete ZK
x2000-45 element.
19, to above-mentioned ZK
x2000-45 element carries out test of dispatching from the factory.
After tested, manufacture method of the present invention is adopted to manufacture the supporting FRD (ZK of IGCT
xkey parameter 2000-45) is as follows:
Comparative example 1:
Other conditions are identical with embodiment 1, and difference is only, comparative example 1 does not carry out the step 15 in embodiment 1.
The supporting total head direct type FRD of IGCT in comparative example 1 (ZK
xkey parameter 1100-45) is as follows:
Comparative example 2:
Other conditions are identical with embodiment 1, and difference is only, comparative example 2 does not carry out step 14 in embodiment 1 and step 15.
The supporting total head direct type FRD of IGCT in comparative example 2 (ZK
xkey parameter 1100-45) is as follows:
It should be noted that above-described embodiment only for explaining the present invention, not forming any limitation of the invention.By referring to exemplary embodiments, invention has been described, but to should be understood to word wherein used be descriptive and explanatory vocabulary, instead of limited vocabulary.Can modify the present invention by the scope being defined in the claims in the present invention, and the present invention be revised not deviating from scope and spirit of the present invention.Although the present invention wherein described relates to specific method, material and embodiment, and do not mean that the present invention is limited to particular case disclosed in it, on the contrary, easily extensible of the present invention is to other all methods and applications with identical function.
Claims (10)
1. a preparation method for the supporting fast recovery diode of integrated gate commutated thyristor, comprises the steps:
1) any one side of N-type silicon wafer is carried out polishing, the burnishing surface of described N-type silicon wafer is chip anode face;
2) carry out aluminium pre-deposition, before or after carrying out aluminium pre-deposition, carry out boron ion implantation at the burnishing surface of described silicon wafer, and carry out oxidation propelling technique, make to form P in silicon wafer
+positive-negative-positive vertical structure;
3) grind the non-burnishing surface of described silicon wafer, described silicon wafer is thinned to default thickness, make silicon wafer inside form P
+pN type vertical structure;
4) carry out phosphorus impurities doping diffusion in the N-type side of described silicon wafer, make silicon wafer inside form P
+pNN
+type vertical structure;
5) at described silicon wafer surface evaporation aluminium lamination, form extraction electrode, after described silicon wafer surface evaporation aluminium lamination, carry out alloying technology, make to form ohmic contact between aluminium, silicon;
6) proton irradiation is carried out in chip anode face, to regulate the softness factor S of minority carrier life time and/or chip;
7) under uniform temperature, pressure, together with being bonded to molybdenum sheet in chip anode face, chip semi-finished product are obtained;
8) to step 7) obtained chip semi-finished product carry out moulding, preferably carry out the moulding of knot terminal, more preferably carry out table top moulding, and carry out conservation treatment, form complete chip;
9) to step 8) obtained complete chip carries out electron irradiation, obtains chip end-product.
2. method according to claim 1, it is characterized in that, step 2) described in aluminium pre-deposition for silicon wafer is loaded in source capsule, then source capsule is put into aluminium pre-deposition diffusion furnace, the doping of aluminium impurity is carried out to silicon wafer, until the aluminium impurity concentration on the burnishing surface top layer of silicon wafer reaches design load, and
Step 2) described in oxidation advance technique carry out in diffusion furnace.
3. method according to claim 1 and 2, is characterized in that, step 2) described in boron ion implantation comprise the steps:
A) described silicon wafer is put into diffusion furnace and carry out oxidation technology, make described silicon wafer surface form SiO
2protective layer is to protect boron ion implantation face;
B) boron ion is injected at the burnishing surface of described silicon wafer.
4., according to the method in claim 1-3 described in any one, it is characterized in that, step 4) described in carry out in the N-type side of described silicon wafer phosphorus impurities doping diffusion comprise the steps:
I) described silicon wafer is put into diffusion furnace and carry out phosphorus pre-deposition technique, make the non-burnishing surface of described silicon wafer form the N-type impurity layer of high concentration, then remove the phosphorosilicate glass on described silicon wafer surface;
Ii) described silicon wafer being put into phosphorus advances diffusion furnace to carry out phosphorus impurities and deeply tie diffusion, makes phosphorus impurities diffuse to the default degree of depth, then removes the SiO on silicon wafer surface
2layer.
5., according to the method in claim 1-4 described in any one, it is characterized in that, step 3) described grinding adopts one side grinding process to carry out, and step 5) described in evaporation aluminium lamination carry out in a vacuum.
6., according to the method in claim 1-5 described in any one, it is characterized in that, step 7) described under uniform temperature, pressure, specifically comprise the steps: together with chip anode face is bonded to molybdenum sheet
A) at chip anode face sputtering bonding metal layer;
B) at the bonding face sputtering bonding metal layer of molybdenum sheet, or single or double is directly selected to sputter the molybdenum sheet having bonding metal layer;
C) at molybdenum sheet bonding face crimping Ag films, under being crimped on the temperature of 100-200 DEG C preferably, carry out under the pressure of 0.3-2MPa;
D), together with chip anode face is crimped onto with the bonding face of molybdenum sheet, under being crimped on the temperature of 150-300 DEG C preferably, carry out under the pressure of 3-8MPa.
7. method according to claim 6, is characterized in that, step a) described in bonding metal layer be any one in the following: Ag metal level, Ti, Ag metal level, Ni, Ag metal level, and Ti, Ni, Ag metal level;
Step b) described in bonding metal layer be any one in the following: Ag metal level, Ti, Ag metal level, Ni, Ag metal level, and Ti, Ni, Ag metal level.
8. according to the method in claim 1-7 described in any one, it is characterized in that, in step 9) in electron irradiation is carried out to chip after also carry out chip testing, whether reach preset value with detection chip minority carrier life time and chip pressure drop; If do not reach preset value, then proceed electron irradiation until chip minority carrier life time and chip pressure drop reach preset value.
9. according to the method in claim 1-8 described in any one, it is characterized in that, described method also comprises the steps:
10) test of chip end-product is carried out to chip end-product, encapsulate and dispatch from the factory test in any one or multiple.
10. according to the method in claim 1-9 described in any one, it is characterized in that, in step 5) at described silicon wafer surface evaporation aluminium lamination and/or before or after carrying out alloying technology, or in step 6) before or after also cyclotomy is carried out to described silicon wafer, described silicon wafer to be cut into the disk with preset diameters.
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| CN107680907A (en) * | 2016-08-01 | 2018-02-09 | 株洲中车时代电气股份有限公司 | Fast recovery diode preparation method and the fast recovery diode made by this method |
| CN112309842A (en) * | 2019-07-26 | 2021-02-02 | 株洲中车时代半导体有限公司 | Manufacturing method of fast recovery diode |
| CN113223953A (en) * | 2021-03-31 | 2021-08-06 | 青岛惠科微电子有限公司 | Manufacturing method and manufacturing equipment of fast recovery chip and fast recovery chip |
| CN115083892A (en) * | 2022-07-28 | 2022-09-20 | 山东芯源微电子有限公司 | Method for diffusing wider pressure-resistant area of high-voltage and ultrahigh-voltage chips |
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| CN107680907A (en) * | 2016-08-01 | 2018-02-09 | 株洲中车时代电气股份有限公司 | Fast recovery diode preparation method and the fast recovery diode made by this method |
| CN107680907B (en) * | 2016-08-01 | 2020-04-17 | 株洲中车时代电气股份有限公司 | Fast recovery diode manufacturing method and fast recovery diode manufactured by same |
| CN112309842A (en) * | 2019-07-26 | 2021-02-02 | 株洲中车时代半导体有限公司 | Manufacturing method of fast recovery diode |
| CN113223953A (en) * | 2021-03-31 | 2021-08-06 | 青岛惠科微电子有限公司 | Manufacturing method and manufacturing equipment of fast recovery chip and fast recovery chip |
| CN115083892A (en) * | 2022-07-28 | 2022-09-20 | 山东芯源微电子有限公司 | Method for diffusing wider pressure-resistant area of high-voltage and ultrahigh-voltage chips |
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|---|---|
| CN105355552B (en) | 2018-05-29 |
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