CN113206033A - Wafer bonding method, wafer and wafer bonding structure - Google Patents

Wafer bonding method, wafer and wafer bonding structure Download PDF

Info

Publication number
CN113206033A
CN113206033A CN202110476268.2A CN202110476268A CN113206033A CN 113206033 A CN113206033 A CN 113206033A CN 202110476268 A CN202110476268 A CN 202110476268A CN 113206033 A CN113206033 A CN 113206033A
Authority
CN
China
Prior art keywords
notch
wafer
bonding
bonding method
sector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110476268.2A
Other languages
Chinese (zh)
Inventor
缪威
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Wuhan Xinxin Semiconductor Manufacturing Corp
Original Assignee
Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan Xinxin Semiconductor Manufacturing Co Ltd filed Critical Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority to CN202110476268.2A priority Critical patent/CN113206033A/en
Publication of CN113206033A publication Critical patent/CN113206033A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number

Abstract

The invention provides a wafer bonding method, a wafer and a wafer bonding structure, wherein a second notch with a smaller size is preset on a bearing wafer, and after a device wafer and the bearing wafer are aligned and bonded, the projection of the second notch on the device wafer completely falls into a first notch; trimming the second notch, and adapting to the first notch to enable the trimmed second notch to be superposed with the first notch; under the condition that the alignment precision of the bonding equipment is not high, the precise alignment of the device wafer and the bearing wafer is finally realized, and the precision requirement of the subsequent photoetching process on the bonding alignment is met. Alignment marks are not required to be manufactured on the bearing wafer through a photoetching process, so that the process flow of the bearing wafer can be reduced, and the cost is saved. The performance requirements of the bonding equipment can be reduced, so that the bonding equipment can be manufactured at low cost.

Description

Wafer bonding method, wafer and wafer bonding structure
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a wafer bonding method, a wafer and a wafer bonding structure.
Background
Wafer bonding has become a key technology for the integrated development and implementation of semiconductor manufacturing technology. Wafer bonding refers to bonding two flat wafer surfaces together, and applying external conditions such as a certain pressure, temperature, voltage, etc. to generate bonding force between atoms or molecules, such as covalent bond, metal bond, molecular bond, etc., at the interface between the two wafers, so that the bonding between the two surfaces can reach a certain strength, and the two wafers are integrated.
To achieve high-precision alignment bonding, two modes are mainly adopted at present, the first mode is: realizing bonding by aligning the respective alignment marks of the two wafers; and the second method comprises the following steps: bonding is achieved by finding the wafer boundary and notch (notch) alignment.
Advantages of the first mode: the precision is high; the disadvantages are as follows: the cost is high, a high-precision bonder is needed, bonding alignment marks need to be designed for bonding wafers, the process is complex, and the cost is high.
The advantages of the second mode: the cost is low, and the bonded wafer does not need to be provided with an alignment mark, so that a plurality of process flows are saved; the disadvantages are as follows: the alignment precision is low, so that the subsequent photoetching process (the identification notch precision is less than 44 mu m) is unacceptable and the subsequent photoetching process is easy to scrap, the bonding process capability is about 400 mu m by the wafer boundary and notch alignment at present, and the alignment precision error of the left and right rotation directions of two wafers is mainly caused by poor quality of the wafer notch.
Disclosure of Invention
The invention aims to provide a wafer bonding method, a wafer and a wafer bonding structure, which can finally realize the accurate alignment of a device wafer and a bearing wafer under the condition of low accuracy of bonding equipment and meet the accuracy requirement of a subsequent photoetching process on bonding alignment.
The invention provides a wafer bonding method, which comprises the following steps:
providing a device wafer and a bearing wafer with the same diameter, wherein the device wafer is provided with a first gap, and the bearing wafer is provided with a second gap;
aligning and bonding the device wafer and the bearing wafer, wherein the projection of the second notch on the device wafer completely falls into the first notch after bonding;
and trimming the second notch to enable the trimmed second notch to be superposed with the first notch.
Furthermore, the misalignment error of the trimmed second notch and the trimmed first notch is less than or equal to 3 μm.
Furthermore, in the top view direction of the device wafer and the carrier wafer, the first notch and the second notch are both fan-shaped.
Further, when the symmetry axis of the first notch and the symmetry axis of the second notch coincide, the length of the sector arc corresponding to the first notch is 850-1030 μm larger than that of the sector arc corresponding to the second notch.
Furthermore, the central angle of the sector corresponding to the first notch is 89-95 degrees, the radius of the sector corresponding to the first notch is 1100 μm +/-35 μm, and the arc length of the sector corresponding to the first notch is 1670 μm-1780 μm.
Furthermore, the central angle of the sector corresponding to the second notch is 89-95 degrees, the radius of the sector corresponding to the second notch is 500 μm +/-20 μm, and the arc length of the sector corresponding to the second notch is 750 μm-820 μm.
Further, after the device wafer and the carrier wafer are aligned and bonded, the central axis of the device wafer coincides with the central axis of the carrier wafer.
Further, the aligning and bonding the device wafer and the carrier wafer comprises:
and bonding the device wafer and the bearing wafer, and then carrying out an annealing process to realize covalent bond bonding.
Further, no component pattern is disposed on the carrier wafer.
Further, the second notch is trimmed by laser cutting or grinding with a grinding knife.
Furthermore, the central angle of the sector corresponding to the second notch is 89-95 degrees, and the radius of the sector corresponding to the second notch is 500 μm +/-50 μm.
The present invention also provides a wafer bonding structure, including:
the device wafer and the bearing wafer are bonded and have the same notch, the notch is in a fan shape, the central angle of the fan shape corresponding to the notch is 89-95 degrees, the radius of the fan shape corresponding to the notch is 1100 microns +/-35 microns, and the arc length of the fan shape corresponding to the notch is 1670 microns-1780 microns.
The invention also provides a wafer which comprises a notch, wherein the central angle of the sector corresponding to the notch is 89-95 degrees, and the radius of the sector corresponding to the notch is 500 microns +/-50 microns.
Furthermore, the radius of the sector corresponding to the notch is 500 microns +/-20 microns, and the arc length of the sector corresponding to the notch is 750 microns to 820 microns.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a wafer bonding method, wherein a second notch with a smaller size is preset on a bearing wafer, and after a device wafer and the bearing wafer are aligned and bonded, the projection of the second notch on the device wafer completely falls into a first notch; trimming the second notch, and adapting to the first notch to enable the trimmed second notch to be superposed with the first notch; namely, according to the size of the first gap of the device wafer, the second gap for bearing the wafer is ground and cut into the size of the first gap of the device wafer. Under the condition that the alignment precision of the bonding equipment is not high, the precise alignment of the device wafer and the bearing wafer is finally realized, the precision capability of the wafer edge bonding process is improved, and the precision requirement of the subsequent photoetching process on the bonding alignment is met. Alignment marks (marks) are not required to be manufactured on the bearing wafer through a photoetching process, so that the process flow of the bearing wafer can be reduced, and the cost is saved. The performance requirements of the bonding equipment can be reduced, so that the bonding equipment can be manufactured at low cost.
The scheme also provides a novel wafer, and compared with a conventional wafer, the novel wafer has a smaller notch design, but as described above, the design of the smaller notch cannot be understood as a simple change of the size, and the wafer with the smaller notch changes the design idea of the wafer notch, namely, the inertia thinking of the conventional wafer design is overcome, so that the alignment efficiency can be improved when the wafer is bonded and aligned, and the cost can be reduced while the requirement of the precision can be met.
Drawings
Fig. 1 is a schematic flow chart of a wafer bonding method according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a device wafer according to an embodiment of the invention.
Fig. 3 is a schematic view of a carrier wafer according to an embodiment of the invention.
Fig. 4 shows a first case of bonding two wafers according to the embodiment of the present invention.
Fig. 5 shows a second situation after bonding two wafers according to the embodiment of the present invention.
Fig. 6 is a partially enlarged view of the second notch and the first notch in fig. 5.
Fig. 7 shows a third situation after bonding two wafers according to the embodiment of the present invention.
Fig. 8 is a schematic diagram illustrating the trimmed second notch according to the embodiment of the invention.
Wherein the reference numbers are as follows:
10-a device wafer; n 1-first gap; 20-carrying the wafer; n 2-second notch; w-bonding the wafer.
Detailed Description
Based on the above research, an embodiment of the present invention provides a wafer bonding method. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.
An embodiment of the present invention provides a wafer bonding method, as shown in fig. 1, including:
providing a device wafer and a bearing wafer with the same diameter, wherein the device wafer is provided with a first gap, and the bearing wafer is provided with a second gap;
aligning and bonding the device wafer and the bearing wafer, wherein the projection of the second notch on the device wafer completely falls into the first notch after bonding;
and trimming the second notch to enable the trimmed second notch to be superposed with the first notch.
The steps of the wafer bonding method according to the embodiment of the invention will be described with reference to fig. 2 to 8.
FIG. 2 is a schematic view of a device wafer 10 according to an embodiment of the present invention; fig. 3 is a schematic view of a carrier wafer 20 according to an embodiment of the invention. As shown in fig. 2 and 3, a device wafer 10 and a handle wafer 20 having the same diameter are provided, the device wafer having a first notch (notch) n1, and the handle wafer 20 having a second notch (notch) n 2. The carrier wafer 20 is mainly used for supporting or carrying the device wafer 10, the device wafer 10 has two opposite surfaces, and one side surface of the device wafer 10 is fixed on the carrier wafer 20 so as to process the other side surface of the device wafer 10. For example, the carrier wafer 20 is not provided with a device pattern (for example, a plain wafer), that is, the carrier wafer 20 and the device wafer 10 do not need to achieve mutual alignment of patterns on the two wafers, what is needed is to achieve alignment of the perimeter boundary profile of the device wafer 10 and the perimeter boundary profile of the carrier wafer 20 in the thickness direction of the two wafers (that is, to achieve central axis coincidence of the two wafers), and alignment of the boundary profile of the first notch (notch) n1 and the boundary profile of the second notch (notch) n2 in the thickness direction of the two wafers, and errors of misalignment (misalignment) of the perimeter boundary profile and the notch boundary profile are within an error range allowed by a subsequent photolithography process. It should be appreciated that the alignment of the perimeter boundary profiles of the two wafers is easy to achieve because the two wafers have the same diameter, and the main difficulty is to achieve the alignment of the notch boundary profiles of the two wafers.
As shown in fig. 4 to 7, the device wafer 10 and the carrier wafer 20 are aligned and bonded, and after bonding, the projection of the second notch n2 on the device wafer 10 completely falls into the first notch n 1. The perimeter profile edge of the device wafer is aligned with the perimeter profile edge of the handle wafer (i.e., the center axes of the two wafers are coincident). The alignment bonding includes: and aligning and bonding the device wafer and the bearing wafer, and then carrying out an annealing process to realize covalent bond bonding so as to increase the bonding strength.
The first notch n1 and the second notch n2 are sized during the step of providing a device wafer 10 and a handle wafer 20 having the same diameter. Fig. 4 shows the first case after bonding of two wafers, the second notch n2 being to the left of the first notch n 1. Fig. 5 shows a second case after bonding of two wafers, in which the second notch n2 falls in the middle of the first notch n1, which is a preferable state. Fig. 6 is a partially enlarged schematic view of the second notch n2 and the first notch n1 in fig. 5. Fig. 7 shows a third case after bonding of two wafers, where the second notch n2 is located to the right of the first notch n 1.
As shown in fig. 5 and 6, the first notch n1 and the second notch n2 are fan-shaped when the device wafer 10 and the carrier wafer 20 are viewed from above; in other embodiments, the first notch n1 and the second notch n2 may have other shapes, such as a square notch recessed toward the center of the wafer. Illustratively, the fan-shaped central angle a corresponding to the first notch n1 is 89-95 °, the fan-shaped radius AB corresponding to the first notch n1 is 1100 μm ± 35 μm, and the fan-shaped arc length BC corresponding to the first notch is 1670 μm-1780 μm. The sector central angle D corresponding to the second notch n2 is 89-95 degrees, and the sector radius DE corresponding to the second notch can be 500 mu m +/-50 mu m; furthermore, the sector radius DE corresponding to the second notch n2 can also be 500 μm +/-20 μm, and the sector arc length EF corresponding to the second notch n2 is 750 μm to 820 μm. Preferably, when the symmetry axis of the first notch n1 and the symmetry axis of the second notch n2 coincide, the fan-shaped arc length BC corresponding to the first notch n1 is 850 μm to 1030 μm larger than the fan-shaped arc length EF corresponding to the second notch n2, that is, under the condition that the precision of the existing bonding equipment is not high: spaces of 425-515 mu m (such as BE and CF) can BE left and right respectively, the defect of insufficient alignment precision of a wafer bonding process is compatible, and the wafer bonding process capability can BE well adapted to the process capability of realizing the bonding process capability of about 400 mu m through the wafer boundary and notch alignment at present.
The second notch n2 in fig. 4, 5 or 7 is trimmed, and as shown in fig. 8, the trimmed second notch and the first notch are overlapped (aligned notches), so that a bonded wafer composed of the carrier wafer 20 and the device wafer 10 is obtained. It should be understood that perfect registration is an ideal state, and in an actual process, the misalignment error of the trimmed second notch and the trimmed first notch is required to be less than or equal to 3 μm so as to meet the precision requirement of a subsequent photolithography process on bonding alignment. The boundary contour of the first notch (notch) n1 and the boundary contour of the second notch (notch) n2 are aligned in the thickness direction of the two wafers, in the subsequent photoetching process, light rays emitted by a light source in an optical acquisition system irradiate the aligned notches of the bonded wafers, image data of the aligned notches (in a designated direction) and image data of at least three points on the wafer edges of the bonded wafers (the bearing wafer 20 and the device wafer 10) are acquired, the circle centers of the bonded wafers are calculated, and the wafer direction can also be determined; namely, the center of a circle and the direction of a wafer are determined by the aligned gaps.
And trimming the second notch by adopting laser cutting or grinding by adopting a grinding knife. The grinding knife is arranged on the wafer edge trimmer, and the edge of the wafer is ground by the grinding knife. Under the normal condition, the maximum rotation speed of the grinding knife is 60000 rpm, the normal working rotation speed is 3000 rpm, and in order to ensure the personal safety, the grinding knife can be replaced only under the condition that the rotation speed is lower than 10 rpm. And when the surface temperature of the grinding knife is lower than 30 ℃, the human body can be ensured to be prevented from being scalded by contacting the grinding knife.
This embodiment still further provides a wafer bonding structure, includes:
the device wafer and the bearing wafer are bonded and have the same notch, the notch is in a fan shape, the central angle of the fan shape corresponding to the notch is 89-95 degrees, the radius of the fan shape corresponding to the notch is 1100 microns +/-35 microns, and the arc length of the fan shape corresponding to the notch is 1670 microns-1780 microns. The notch is the notch after the second notch and the first notch after trimming in the wafer bonding method are overlapped and aligned.
The invention also provides a wafer which comprises a notch, wherein the central angle of the sector corresponding to the notch is 89-95 degrees, and the radius of the sector corresponding to the notch is 500 microns +/-50 microns. Furthermore, the radius of the sector corresponding to the notch is 500 microns +/-20 microns, and the arc length of the sector corresponding to the notch is 750 microns to 820 microns. Compared with the conventional wafer, the wafer of the scheme has a smaller notch design, but the design of the smaller notch cannot be understood as simple change of the size, the conventional design thought of the wafer notch is changed by the small notch wafer, the inertial thought of the conventional wafer design is overcome, the alignment efficiency can be improved during wafer bonding alignment, and the cost can be reduced while the requirement of the precision can be met.
In summary, in the embodiment, the second notch (notch) n2 with a smaller size is preset on the carrier wafer 20, and after the device wafer and the carrier wafer are aligned and bonded, the projection of the second notch n2 on the device wafer 10 completely falls into the first notch n 1; trimming the second notch n2 to fit the first notch n1, so that the trimmed second notch is superposed with the first notch; namely, according to the size of the first notch n1 of the device wafer, the second notch n2 of the carrier wafer is ground and cut into the size of the first notch n1 of the device wafer. Under the condition that the alignment precision of the bonding equipment is not high, the precise alignment of the device wafer and the bearing wafer is finally realized, and the precision requirement of the subsequent photoetching process on the bonding alignment is met. Alignment marks (marks) do not need to be designed on the bearing wafer, so that the process flow of the bearing wafer can be reduced, the cost is saved, and the performance requirement of bonding equipment can be reduced.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the device disclosed by the embodiment, and the relevant points can be referred to the description of the method part.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (14)

1. A wafer bonding method, comprising:
providing a device wafer and a bearing wafer with the same diameter, wherein the device wafer is provided with a first gap, and the bearing wafer is provided with a second gap;
aligning and bonding the device wafer and the bearing wafer, wherein the projection of the second notch on the device wafer completely falls into the first notch after bonding;
and trimming the second notch to enable the trimmed second notch to be superposed with the first notch.
2. The wafer bonding method of claim 1, wherein a misalignment error between the trimmed second notch and the trimmed first notch is less than or equal to 3 μm.
3. The wafer bonding method of claim 1, wherein the first notch and the second notch are fan-shaped in a top view of the device wafer and the carrier wafer.
4. The wafer bonding method of claim 3, wherein when the symmetry axis of the first notch and the symmetry axis of the second notch coincide, the arc length of the first notch is 850 μm to 1030 μm longer than the arc length of the second notch.
5. The wafer bonding method of claim 1, wherein the central angle of the sector corresponding to the first notch is 89-95 °, the radius of the sector corresponding to the first notch is 1100 μm ± 35 μm, and the arc length of the sector corresponding to the first notch is 1670 μm-1780 μm.
6. The wafer bonding method of claim 1, wherein a central angle of a sector corresponding to the second notch is 89-95 °, a radius of a sector corresponding to the second notch is 500 μm ± 20 μm, and a length of a sector corresponding to the second notch is 750 μm-820 μm.
7. The wafer bonding method of any one of claims 1 to 6, wherein after the device wafer and the carrier wafer are aligned and bonded, a central axis of the device wafer coincides with a central axis of the carrier wafer.
8. The wafer bonding method of any of claims 1 to 6, wherein the aligned bonding of the device wafer and the carrier wafer comprises:
and bonding the device wafer and the bearing wafer, and then carrying out an annealing process to realize covalent bond bonding.
9. The wafer bonding method according to any one of claims 1 to 6, wherein no component pattern is disposed on the carrier wafer.
10. The wafer bonding method of any one of claims 1 to 6, wherein the second notch is trimmed using a laser cutting or a grinding blade.
11. The wafer bonding method of claim 1, wherein the second notch corresponds to a sector central angle of 89 ° to 95 °, and the second notch corresponds to a sector radius of 500 μm ± 50 μm.
12. A wafer bonding structure, comprising:
the device wafer and the bearing wafer are bonded and have the same notch, the notch is in a fan shape, the central angle of the fan shape corresponding to the notch is 89-95 degrees, the radius of the fan shape corresponding to the notch is 1100 microns +/-35 microns, and the arc length of the fan shape corresponding to the notch is 1670 microns-1780 microns.
13. A wafer, comprising: the wafer comprises a notch, the central angle of a fan-shaped corresponding to the notch is 89-95 degrees, and the radius of the fan-shaped corresponding to the notch is 500 mu m +/-50 mu m.
14. The wafer of claim 13, wherein the notch corresponds to a sector radius of 500 μm ± 20 μm and a sector arc length of 750 μm to 820 μm.
CN202110476268.2A 2021-04-29 2021-04-29 Wafer bonding method, wafer and wafer bonding structure Pending CN113206033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110476268.2A CN113206033A (en) 2021-04-29 2021-04-29 Wafer bonding method, wafer and wafer bonding structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110476268.2A CN113206033A (en) 2021-04-29 2021-04-29 Wafer bonding method, wafer and wafer bonding structure

Publications (1)

Publication Number Publication Date
CN113206033A true CN113206033A (en) 2021-08-03

Family

ID=77029582

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110476268.2A Pending CN113206033A (en) 2021-04-29 2021-04-29 Wafer bonding method, wafer and wafer bonding structure

Country Status (1)

Country Link
CN (1) CN113206033A (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002052447A (en) * 2000-08-09 2002-02-19 Nippei Toyama Corp Notch grinding device for semiconductor wafer and notched groove chamfering method
JP2008041985A (en) * 2006-08-08 2008-02-21 Tokyo Ohka Kogyo Co Ltd Support plate
KR20090046172A (en) * 2007-11-05 2009-05-11 주식회사 동부하이텍 An appartus for wafer bonding and a method for wafer bonding
JP2010114466A (en) * 2004-03-26 2010-05-20 Fujifilm Corp Device and method for joining substrates
JP2010287816A (en) * 2009-06-15 2010-12-24 Canon Inc Apparatus and method for positioning substrate
CN104979223A (en) * 2014-04-03 2015-10-14 中芯国际集成电路制造(上海)有限公司 Wafer bonding process
WO2020103226A1 (en) * 2018-11-20 2020-05-28 中芯集成电路（宁波）有限公司 Semiconductor device and manufacturing method therefor, and alignment marker manufacturing method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002052447A (en) * 2000-08-09 2002-02-19 Nippei Toyama Corp Notch grinding device for semiconductor wafer and notched groove chamfering method
JP2010114466A (en) * 2004-03-26 2010-05-20 Fujifilm Corp Device and method for joining substrates
JP2008041985A (en) * 2006-08-08 2008-02-21 Tokyo Ohka Kogyo Co Ltd Support plate
KR20090046172A (en) * 2007-11-05 2009-05-11 주식회사 동부하이텍 An appartus for wafer bonding and a method for wafer bonding
JP2010287816A (en) * 2009-06-15 2010-12-24 Canon Inc Apparatus and method for positioning substrate
CN104979223A (en) * 2014-04-03 2015-10-14 中芯国际集成电路制造(上海)有限公司 Wafer bonding process
WO2020103226A1 (en) * 2018-11-20 2020-05-28 中芯集成电路（宁波）有限公司 Semiconductor device and manufacturing method therefor, and alignment marker manufacturing method

Similar Documents

Publication Publication Date Title
CN105643396B (en) The grinding and milling processing method of large-scale bore off-axis aspheric surface lens
JP6043150B2 (en) Breaking apparatus for laminated brittle material substrate and method for breaking laminated brittle material substrate
CN107984303A (en) The processing method of uniform thickness off-axis aspheric surface speculum
JP2003240914A (en) Method of forming fiducial mark
CN110842476B (en) Method for manufacturing pentahedron reflector applied to high-speed scanning system
JP2000206312A (en) Optical element
CN113206033A (en) Wafer bonding method, wafer and wafer bonding structure
TW201516012A (en) Breaking device
CN106181477A (en) The processing method of special-shaped groove between a kind of assembling clamp and stator blade
US20030232578A1 (en) Curved surface cutting processing method
CN114894188A (en) Table body for hemispherical resonator gyroscope inertial navigation system and processing method thereof
JP2892459B2 (en) Blade position adjustment method for precision cutting equipment
JP4427000B2 (en) Workpiece holding device and workpiece holding position adjusting method
JPH0745516A (en) Saw-cut method for forming position alignment marks on two surfaces of a substrate
CN105710747A (en) Processing method of micro cylindrical mirror
JP5156990B1 (en) Mold processing method
JP2004345017A (en) Method and device for grooving
Lapshin et al. Machining of linear negative matrices for Fresnel lenses and prisms
JP2000052217A (en) Tool and processing method
JP2001255138A (en) Measurement jig
KR102659151B1 (en) Stylus and measurement method
US7757373B2 (en) Method and tool head for machining optically active surfaces, particularly surfaces of progressive spectacle lenses, which are symmetrical in pairs
JP3842916B2 (en) Positioning device and positioning method
JP6625009B2 (en) Manufacturing method of package device chip
JPS62152621A (en) Method of machining air groove in air bearing

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination